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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

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  • This comparison shows the changes necessary to convert path 
    /wb2axip/trunk/doc
    from Rev 8 to Rev 16
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  •

Rev 8 → Rev 16

/Makefile
10,7 → 10,7
## Targets include:
## all Builds all documents
##
## gpl-3.0.pdf Builds the GPL license these files are released
## lgpl-3.0.pdf Builds the LGPL license these files are released
## under.
##
## spec.pdf Builds the specification for the SDSPI
21,43 → 21,47
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
## Copyright (C) 2015-2016,2018 Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
## This file is part of the pipelined Wishbone to AXI converter project, a
## project that contains multiple bus bridging designs and formal bus property
## sets.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
## The bus bridge designs and property sets are free RTL designs: you can
## redistribute them and/or modify any of them under the terms of the GNU
## Lesser General Public License as published by the Free Software Foundation,
## either version 3 of the License, or (at your option) any later version.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## The bus bridge designs and property sets are distributed in the hope that
## they will be useful, but WITHOUT ANY WARRANTY; without even the implied
## warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License
## along with these designs. (It's in the $(ROOT)/doc directory. Run make
## with no target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
## License: LGPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/lgpl.html
##
##
################################################################################
##
##
all: gpl
pdf: gpl spec
all: lgpl
pdf: lgpl spec
DSRC := src
 
.PHONY: gpl
gpl: gpl-3.0.pdf
.PHONY: lgpl
LICENSE := lgpl-3.0
lgpl: $(LICENSE).pdf
 
gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex
latex $(DSRC)/gpl-3.0.tex
latex $(DSRC)/gpl-3.0.tex
dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi
ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf
rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps
$(LICENSE).pdf: $(DSRC)/$(LICENSE).tex
latex $(DSRC)/$(LICENSE).tex
latex $(DSRC)/$(LICENSE).tex
dvips -q -z -t letter -P pdf -o $(LICENSE).ps $(LICENSE).dvi
ps2pdf -dAutoRotatePages=/All $(LICENSE).ps $(LICENSE).pdf
rm $(LICENSE).dvi $(LICENSE).log $(LICENSE).aux $(LICENSE).ps
 
.PHONY: spec
spec: spec.pdf
79,5 → 83,4
rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc
rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof
rm -f $(DSRC)/spec.out spec.ps spec.pdf
rm -f gpl-3.0.pdf
 
rm -f $(LICENSE).pdf
/src/spec.tex
3,21 → 3,48
%%
%% Filename: spec.tex
%%
%% Project:
%% Project: Pipelined Wishbone to AXI coverter
%%
%% Purpose:
%% Purpose: This document is a LaTeX description describing how to build
%% a specification document for the cores within this Pipelined
%% WB2AXI repository.
%%
%% Creator:
%% Creator: Dan Gisselquist, Ph.D.
%% Gisselquist Technology, LLC
%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%% Copyright (C) 2018, Gisselquist Technology, LLC
%%
%% This program is free software (firmware): you can redistribute it and/or
%% modify it under the terms of the GNU General Public License as published
%% by the Free Software Foundation, either version 3 of the License, or (at
%% your option) any later version.
%%
%% This program is distributed in the hope that it will be useful, but WITHOUT
%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
%% for more details.
%%
%% You should have received a copy of the GNU General Public License along
%% with this program. (It's in the $(ROOT)/doc directory, run make with no
%% target there if the PDF file isn't present.) If not, see
%% <http://www.gnu.org/licenses/> for a copy.
%%
%% License: GPL, v3, as defined and found on www.gnu.org,
%% http://www.gnu.org/licenses/gpl.html
%%
%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%%
\usepackage{import}
\usepackage{bytefield}
\project{Wishbone to AXI}
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq (at) opencores.org}
\revision{Rev.~0.0}
\email{zipcpu (at) gmail.com}
\revision{Rev.~0.1}
\begin{document}
\pagestyle{gqtekspecplain}
\titlepage
25,17 → 52,27
Copyright (C) \theyear\today, Gisselquist Technology, LLC
 
This project is free software (firmware): you can redistribute it and/or
modify it under the terms of the GNU General Public License as published
modify it under the terms of the GNU General Public License as published
by the Free Software Foundation, either version 3 of the License, or (at
your option) any later version.
 
Some files within this repository have been released under the GNU Lesser
General Public License. These components may be separated from this repository,
and redistributed or modified under the terms of the Lesser GNU
Public License, again as published by the Free Software Foundation,
either vversion 3 of the License or (at your option) any later
version. These files will identified as such in their headers.
 
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
for more details, or the GNU Lesser General Public License as appropriate.
 
You should have received a copy of the GNU General Public License along
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
You should have received a copy of both the GNU General Public License as
well as the GNU Lesser General Public License along with this repository.
(They are both in the \$(ROOT)/doc directory. Run make with no target there
if the PDF files are not present.) If not, see If not, see
\texttt{http://www.gnu.org/licenses/} for a copy.
\end{license}
\begin{revisionhistory}
0.0 & 9/6/2016 & D. Gisselquist & First draft\\\hline
46,13 → 83,19
\listoffigures
\listoftables
\begin{preface}
This controller is born of necessity. As long as Xilinx's proprietary IP
makes it difficult to access memory, providing only access via the proprietary
AXI bus, some conversion will be necessary for anyone who wishes to use a
wishbone interface.
The wishbone to AXI controller is born of necessity. As long as Xilinx's
proprietary IP makes it difficult to access memory, providing only access
via the proprietary AXI bus, some conversion will be necessary for anyone
who wishes to use a wishbone interface.
 
A special shout out and thanks go to Stephan Wallentowitz, for his first
draft of such a converter, and to Olofk for encouraging me to write it.
draft of such a converter, and to Olofk for encouraging me to write this
initial core.
 
The project has since grown into a general purpose set of both bus bridges
and formal bus properties, to include support for Wishbone, AXI-lite, and
Avalon busses. The full AXI implementation, together with the bridges
between full AXI and other busses, remains a work in progress.
\end{preface}
 
\chapter{Introduction}\label{ch:intro}
99,9 → 142,9
\begin{wishboneds}
Revision level of wishbone & WB B4 spec \\\hline
Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
Port size & 128--bit or 32--bit \\\hline
Port size & Various and configurable \\\hline
Port granularity & 8--bit \\\hline
Maximum Operand Size & 128--bit or 32--bit \\\hline
Maximum Operand Size & Various and configurable\\\hline
Data transfer ordering & (Preserved) \\\hline
Clock constraints & None.\\\hline
Signal Names & \begin{tabular}{ll}

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