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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

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    /wb2axip/trunk/rtl
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Rev 7 → Rev 8

/Makefile
30,7 → 30,7
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
52,6 → 52,12
.PHONY: testwb
.PHONY: testaxi
 
.PHONY: wbm2axisp
wbm2axisp: testwb
 
.PHONY: axim2wbsp
axim2wbsp: testaxi
 
testwb: $(VDIRFB)/Vwbm2axisp__ALL.a
testaxi: $(VDIRFB)/Vaxim2wbsp__ALL.a
 
/axim2wbsp.v
0,0 → 1,396
////////////////////////////////////////////////////////////////////////////////
//
// Filename: axim2wbsp.v
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose: So ... this converter works in the other direction. This
// converter takes AXI commands, and organizes them into pipelined
// wishbone commands.
//
//
// We'll treat AXI as two separate busses: one for writes, another for
// reads, further, we'll insist that the two channels AXI uses for writes
// combine into one channel for our purposes.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module axim2wbsp( i_clk, i_axi_reset_n,
//
o_axi_awready, // Slave is ready to accept
i_axi_awid, i_axi_awaddr, i_axi_awlen, i_axi_awsize, i_axi_awburst,
i_axi_awlock, i_axi_awcache, i_axi_awprot, i_axi_awqos, i_axi_awvalid,
//
o_axi_wready, i_axi_wdata, i_axi_wstrb, i_axi_wlast, i_axi_wvalid,
//
o_axi_bid, o_axi_bresp, o_axi_bvalid, i_axi_bready,
//
o_axi_arready, // Read address ready
i_axi_arid, // Read ID
i_axi_araddr, // Read address
i_axi_arlen, // Read Burst Length
i_axi_arsize, // Read Burst size
i_axi_arburst, // Read Burst type
i_axi_arlock, // Read lock type
i_axi_arcache, // Read Cache type
i_axi_arprot, // Read Protection type
i_axi_arqos, // Read Protection type
i_axi_arvalid, // Read address valid
//
o_axi_rid, // Response ID
o_axi_rresp, // Read response
o_axi_rvalid, // Read reponse valid
o_axi_rdata, // Read data
o_axi_rlast, // Read last
i_axi_rready, // Read Response ready
// Wishbone interface
o_reset, o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
//
parameter C_AXI_ID_WIDTH = 6; // The AXI id width used for R&W
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 32;// Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28; // AXI Address width
localparam DW = C_AXI_DATA_WIDTH;
localparam AW = (C_AXI_DATA_WIDTH== 8) ? (C_AXI_ADDR_WIDTH)
:((C_AXI_DATA_WIDTH== 16) ? (C_AXI_ADDR_WIDTH-1)
:((C_AXI_DATA_WIDTH== 32) ? (C_AXI_ADDR_WIDTH-2)
:((C_AXI_DATA_WIDTH== 64) ? (C_AXI_ADDR_WIDTH-3)
:((C_AXI_DATA_WIDTH==128) ? (C_AXI_ADDR_WIDTH-4)
:(C_AXI_ADDR_WIDTH-5)))));
//
input wire i_clk; // System clock
input wire i_axi_reset_n;
 
// AXI write address channel signals
output wire o_axi_awready; // Slave is ready to accept
input wire [C_AXI_ID_WIDTH-1:0] i_axi_awid; // Write ID
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_awaddr; // Write address
input wire [7:0] i_axi_awlen; // Write Burst Length
input wire [2:0] i_axi_awsize; // Write Burst size
input wire [1:0] i_axi_awburst; // Write Burst type
input wire [0:0] i_axi_awlock; // Write lock type
input wire [3:0] i_axi_awcache; // Write Cache type
input wire [2:0] i_axi_awprot; // Write Protection type
input wire [3:0] i_axi_awqos; // Write Quality of Svc
input wire i_axi_awvalid; // Write address valid
// AXI write data channel signals
output wire o_axi_wready; // Write data ready
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_wdata; // Write data
input wire [C_AXI_DATA_WIDTH/8-1:0] i_axi_wstrb; // Write strobes
input wire i_axi_wlast; // Last write transaction
input wire i_axi_wvalid; // Write valid
// AXI write response channel signals
output wire [C_AXI_ID_WIDTH-1:0] o_axi_bid; // Response ID
output wire [1:0] o_axi_bresp; // Write response
output wire o_axi_bvalid; // Write reponse valid
input wire i_axi_bready; // Response ready
// AXI read address channel signals
output wire o_axi_arready; // Read address ready
input wire [C_AXI_ID_WIDTH-1:0] i_axi_arid; // Read ID
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr; // Read address
input wire [7:0] i_axi_arlen; // Read Burst Length
input wire [2:0] i_axi_arsize; // Read Burst size
input wire [1:0] i_axi_arburst; // Read Burst type
input wire [0:0] i_axi_arlock; // Read lock type
input wire [3:0] i_axi_arcache; // Read Cache type
input wire [2:0] i_axi_arprot; // Read Protection type
input wire [3:0] i_axi_arqos; // Read Protection type
input wire i_axi_arvalid; // Read address valid
// AXI read data channel signals
output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid; // Response ID
output wire [1:0] o_axi_rresp; // Read response
output wire o_axi_rvalid; // Read reponse valid
output wire [C_AXI_DATA_WIDTH-1:0] o_axi_rdata; // Read data
output wire o_axi_rlast; // Read last
input wire i_axi_rready; // Read Response ready
 
// We'll share the clock and the reset
output wire o_reset;
output wire o_wb_cyc;
output wire o_wb_stb;
output wire o_wb_we;
output wire [(AW-1):0] o_wb_addr;
output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data;
output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel;
input wire i_wb_ack;
input wire i_wb_stall;
input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data;
input wire i_wb_err;
 
 
//
//
//
 
 
wire [(AW-1):0] w_wb_addr, r_wb_addr;
wire [(C_AXI_DATA_WIDTH-1):0] w_wb_data;
wire [(C_AXI_DATA_WIDTH/8-1):0] w_wb_sel;
wire r_wb_err, r_wb_cyc, r_wb_stb, r_wb_stall, r_wb_ack;
wire w_wb_err, w_wb_cyc, w_wb_stb, w_wb_stall, w_wb_ack;
 
// verilator lint_off UNUSED
wire r_wb_we, w_wb_we;
 
assign r_wb_we = 1'b0;
assign w_wb_we = 1'b1;
// verilator lint_on UNUSED
 
aximwr2wbsp #(
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AW(AW))
axi_write_decoder(
.i_axi_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
//
.o_axi_awready(o_axi_awready),
.i_axi_awid( i_axi_awid),
.i_axi_awaddr( i_axi_awaddr),
.i_axi_awlen( i_axi_awlen),
.i_axi_awsize( i_axi_awsize),
.i_axi_awburst(i_axi_awburst),
.i_axi_awlock( i_axi_awlock),
.i_axi_awcache(i_axi_awcache),
.i_axi_awprot( i_axi_awprot),
.i_axi_awqos( i_axi_awqos),
.i_axi_awvalid(i_axi_awvalid),
//
.o_axi_wready( o_axi_wready),
.i_axi_wdata( i_axi_wdata),
.i_axi_wstrb( i_axi_wstrb),
.i_axi_wlast( i_axi_wlast),
.i_axi_wvalid( i_axi_wvalid),
//
.o_axi_bid(o_axi_bid),
.o_axi_bresp(o_axi_bresp),
.o_axi_bvalid(o_axi_bvalid),
.i_axi_bready(i_axi_bready),
//
.o_wb_cyc( w_wb_cyc),
.o_wb_stb( w_wb_stb),
.o_wb_addr( w_wb_addr),
.o_wb_data( w_wb_data),
.o_wb_sel( w_wb_sel),
.i_wb_ack( w_wb_ack),
.i_wb_stall(w_wb_stall),
.i_wb_err( w_wb_err));
assign w_wb_we = 1'b1;
 
aximrd2wbsp #(
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AW(AW))
axi_read_decoder(
.i_axi_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
//
.o_axi_arready(o_axi_arready),
.i_axi_arid( i_axi_arid),
.i_axi_araddr( i_axi_araddr),
.i_axi_arlen( i_axi_arlen),
.i_axi_arsize( i_axi_arsize),
.i_axi_arburst(i_axi_arburst),
.i_axi_arlock( i_axi_arlock),
.i_axi_arcache(i_axi_arcache),
.i_axi_arprot( i_axi_arprot),
.i_axi_arqos( i_axi_arqos),
.i_axi_arvalid(i_axi_arvalid),
//
.o_axi_rid( o_axi_rid),
.o_axi_rresp( o_axi_rresp),
.o_axi_rvalid(o_axi_rvalid),
.o_axi_rdata( o_axi_rdata),
.o_axi_rlast( o_axi_rlast),
.i_axi_rready(i_axi_rready),
//
.o_wb_cyc( r_wb_cyc),
.o_wb_stb( r_wb_stb),
.o_wb_addr( r_wb_addr),
.i_wb_ack( r_wb_ack),
.i_wb_stall(r_wb_stall),
.i_wb_data( i_wb_data),
.i_wb_err( r_wb_err));
 
wbarbiter #(
`ifdef FORMAL
.F_LGDEPTH(C_AXI_DATA_WIDTH),
`endif
.DW(C_AXI_DATA_WIDTH),
.AW(AW))
readorwrite(i_clk, !i_axi_reset_n,
r_wb_cyc, r_wb_stb, 1'b0, r_wb_addr, w_wb_data, w_wb_sel,
r_wb_ack, r_wb_stall, r_wb_err,
w_wb_cyc, w_wb_stb, 1'b1, w_wb_addr, w_wb_data, w_wb_sel,
w_wb_ack, w_wb_stall, w_wb_err,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_err);
 
assign o_reset = (i_axi_reset_n == 1'b0);
 
`ifdef FORMAL
 
`ifdef AXIM2WBSP
reg f_last_clk;
 
initial f_last_clk = 0;
always @($global_clock)
begin
assume(i_clk == f_last_clk);
f_last_clk <= !f_last_clk;
end
`else
`endif
 
reg f_past_valid;
 
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid = 1'b1;
 
wire [(C_AXI_ID_WIDTH-1):0] f_axi_rd_outstanding,
f_axi_wr_outstanding,
f_axi_awr_outstanding;
wire [((1<<C_AXI_ID_WIDTH)-1):0] f_axi_rd_id_outstanding,
f_axi_awr_id_outstanding,
f_axi_wr_id_outstanding;
wire [(C_AXI_ID_WIDTH-1):0] f_wb_nreqs,
f_wb_nacks, f_wb_outstanding;
wire [(C_AXI_ID_WIDTH-1):0] f_wb_wr_nreqs,
f_wb_wr_nacks, f_wb_wr_outstanding;
wire [(C_AXI_ID_WIDTH-1):0] f_wb_rd_nreqs,
f_wb_rd_nacks, f_wb_rd_outstanding;
 
fwb_slave #(.DW(DW), .AW(AW),
.F_MAX_STALL(0),
.F_MAX_ACK_DELAY(0),
.F_LGDEPTH(C_AXI_ID_WIDTH),
.F_OPT_RMW_BUS_OPTION(1),
.F_OPT_DISCONTINUOUS(1))
f_wb_wr(i_clk, !i_axi_reset_n,
w_wb_cyc, w_wb_stb, w_wb_we, w_wb_addr, w_wb_data,
w_wb_sel,
w_wb_ack, w_wb_stall, i_wb_data, w_wb_err,
f_wb_wr_nreqs, f_wb_wr_nacks, f_wb_wr_outstanding);
 
fwb_slave #(.DW(DW), .AW(AW),
.F_MAX_STALL(0),
.F_MAX_ACK_DELAY(0),
.F_LGDEPTH(C_AXI_ID_WIDTH),
.F_OPT_RMW_BUS_OPTION(1),
.F_OPT_DISCONTINUOUS(1))
f_wb_rd(i_clk, !i_axi_reset_n,
r_wb_cyc, r_wb_stb, r_wb_we, r_wb_addr, w_wb_data, w_wb_sel,
r_wb_ack, r_wb_stall, i_wb_data, r_wb_err,
f_wb_rd_nreqs, f_wb_rd_nacks, f_wb_rd_outstanding);
 
fwb_master #(.DW(DW), .AW(AW),
.F_MAX_STALL(3),
.F_MAX_ACK_DELAY(3),
.F_LGDEPTH(C_AXI_ID_WIDTH))
f_wb(i_clk, !i_axi_reset_n,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
 
always @(*)
assume(i_axi_awlen < 8'h4);
 
always @(*)
assume(i_axi_arlen < 8'h4);
 
always @(*)
assume(i_axi_arvalid == 0);
 
faxi_slave #(
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.F_AXI_MAXSTALL(0),
.F_AXI_MAXDELAY(0))
f_axi(.i_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
// AXI write address channnel
.i_axi_awready(o_axi_awready),
.i_axi_awid( i_axi_awid),
.i_axi_awaddr( i_axi_awaddr),
.i_axi_awlen( i_axi_awlen),
.i_axi_awsize( i_axi_awsize),
.i_axi_awburst(i_axi_awburst),
.i_axi_awlock( i_axi_awlock),
.i_axi_awcache(i_axi_awcache),
.i_axi_awprot( i_axi_awprot),
.i_axi_awqos( i_axi_awqos),
.i_axi_awvalid(i_axi_awvalid),
// AXI write data channel
.i_axi_wready( o_axi_wready),
.i_axi_wdata( i_axi_wdata),
.i_axi_wstrb( i_axi_wstrb),
.i_axi_wlast( i_axi_wlast),
.i_axi_wvalid( i_axi_wvalid),
// AXI write acknowledgement channel
.i_axi_bid( o_axi_bid), // Response ID
.i_axi_bresp( o_axi_bresp), // Write response
.i_axi_bvalid(o_axi_bvalid), // Write reponse valid
.i_axi_bready(i_axi_bready), // Response ready
// AXI read address channel
.i_axi_arready(o_axi_arready), // Read address ready
.i_axi_arid( i_axi_arid), // Read ID
.i_axi_araddr( i_axi_araddr), // Read address
.i_axi_arlen( i_axi_arlen), // Read Burst Length
.i_axi_arsize( i_axi_arsize), // Read Burst size
.i_axi_arburst(i_axi_arburst), // Read Burst type
.i_axi_arlock( i_axi_arlock), // Read lock type
.i_axi_arcache(i_axi_arcache), // Read Cache type
.i_axi_arprot( i_axi_arprot), // Read Protection type
.i_axi_arqos( i_axi_arqos), // Read Protection type
.i_axi_arvalid(i_axi_arvalid), // Read address valid
// AXI read data return
.i_axi_rid( o_axi_rid), // Response ID
.i_axi_rresp( o_axi_rresp), // Read response
.i_axi_rvalid( o_axi_rvalid), // Read reponse valid
.i_axi_rdata( o_axi_rdata), // Read data
.i_axi_rlast( o_axi_rlast), // Read last
.i_axi_rready( i_axi_rready), // Read Response ready
// Quantify where we are within a transaction
.f_axi_rd_outstanding( f_axi_rd_outstanding),
.f_axi_wr_outstanding( f_axi_wr_outstanding),
.f_axi_awr_outstanding(f_axi_awr_outstanding),
.f_axi_rd_id_outstanding(f_axi_rd_id_outstanding),
.f_axi_awr_id_outstanding(f_axi_awr_id_outstanding),
.f_axi_wr_id_outstanding(f_axi_wr_id_outstanding));
 
`endif
endmodule
 
/aximrd2wbsp.v
0,0 → 1,318
////////////////////////////////////////////////////////////////////////////////
//
// Filename: aximrd2wbsp.v
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose: Bridge an AXI read channel pair to a single wishbone read
// channel.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module aximrd2wbsp #(
parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width
parameter AW = 26, // AXI Address width
parameter LGFIFO = 4
// parameter WBMODE = "B4PIPELINE"
// Could also be "BLOCK"
) (
input wire i_axi_clk, // Bus clock
input wire i_axi_reset_n, // Bus reset
 
// AXI read address channel signals
output wire o_axi_arready, // Read address ready
input wire [C_AXI_ID_WIDTH-1:0] i_axi_arid, // Read ID
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr, // Read address
input wire [7:0] i_axi_arlen, // Read Burst Length
input wire [2:0] i_axi_arsize, // Read Burst size
input wire [1:0] i_axi_arburst, // Read Burst type
input wire [0:0] i_axi_arlock, // Read lock type
input wire [3:0] i_axi_arcache, // Read Cache type
input wire [2:0] i_axi_arprot, // Read Protection type
input wire [3:0] i_axi_arqos, // Read Protection type
input wire i_axi_arvalid, // Read address valid
// AXI read data channel signals
output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Response ID
output wire [1:0] o_axi_rresp, // Read response
output reg o_axi_rvalid, // Read reponse valid
output wire [C_AXI_DATA_WIDTH-1:0] o_axi_rdata, // Read data
output wire o_axi_rlast, // Read last
input wire i_axi_rready, // Read Response ready
 
// We'll share the clock and the reset
output reg o_wb_cyc,
output reg o_wb_stb,
output wire [(AW-1):0] o_wb_addr,
input wire i_wb_ack,
input wire i_wb_stall,
input [(C_AXI_DATA_WIDTH-1):0] i_wb_data,
input wire i_wb_err
);
 
localparam DW = C_AXI_DATA_WIDTH;
 
wire w_reset;
assign w_reset = (i_axi_reset_n == 1'b0);
 
 
reg [(C_AXI_ID_WIDTH+AW+1)-1:0] afifo [0:((1<<(LGFIFO))-1)];
reg [(DW+1)-1:0] dfifo [0:((1<<(LGFIFO))-1)];
reg [(C_AXI_ID_WIDTH+AW+1)-1:0] fifo_at_neck, afifo_at_tail;
reg [(DW+1)-1:0] dfifo_at_tail;
 
// We're going to need to keep track of transaction bursts in progress,
// since the wishbone doesn't. For this, we'll use a FIFO, but with
// multiple pointers:
//
// fifo_head - pointer to where to write the next incoming
// bus request .. adjusted when
// (o_axi_arready)&&(i_axi_arvalid)
// fifo_neck - pointer to where to read from the FIFO in
// order to issue another request. Used
// when (o_wb_stb)&&(!i_wb_stall)
// fifo_torso - pointer to where to write a wishbone
// transaction upon return.
// when (i_ack)
// fifo_tail - pointer to where the last transaction is to
// be retired when
// (i_axi_rvalid)&&(i_axi_rready)
//
// All of these are to be set to zero upon a reset signal.
//
reg [LGFIFO-1:0] fifo_head, fifo_neck, fifo_torso, fifo_tail;
 
// Since we need to insure that these pointers wrap properly at
// LGFIFO bits, and since it is confusing to do that within IF
// statements,
wire [LGFIFO-1:0] next_head, next_neck, next_torso, next_tail,
almost_head;
wire fifo_full;
assign next_head = fifo_head + 1;
assign next_neck = fifo_neck + 1;
assign next_torso = fifo_torso + 1;
assign next_tail = fifo_tail + 1;
assign almost_head = fifo_head + 1;
 
assign fifo_full = (almost_head == fifo_tail);
 
reg wr_last, filling_fifo, incr;
reg [7:0] len;
reg [(AW-1):0] wr_fifo_addr;
reg [(C_AXI_ID_WIDTH-1):0] wr_fifo_id;
 
//
//
//
//
// Here's our plan: Any time READY & VALID are both true, initiate a
// transfer (unless one is ongoing). Hold READY false while initiating
// any burst transaction. Keep the request RID and burst length stuffs
// into a FIFO.
// queue are both valid, issue the wishbone read request. Once a read
// request returns, retire the value in the FIFO queue.
//
// The FIFO queue *must* include:
//
// RQ, ADDR, LAST
//
initial len = 0;
initial filling_fifo = 0;
initial fifo_head = 0;
always @(posedge i_axi_clk)
begin
wr_last <= 1'b0;
 
if (filling_fifo)
begin
if (!fifo_full)
begin
len <= len - 1;
if (len == 1)
filling_fifo <= 1'b0;
fifo_head <= next_head;
wr_fifo_addr <= wr_fifo_addr
+ {{(AW-1){1'b0}}, incr};
wr_last <= (len == 1);
end
end else begin
wr_fifo_addr <= i_axi_araddr[(C_AXI_ADDR_WIDTH-1):(C_AXI_ADDR_WIDTH-AW)];
wr_fifo_id <= i_axi_arid;
incr <= i_axi_arburst[0];
if ((o_axi_arready)&&(i_axi_arvalid))
begin
fifo_head <= next_head;
len <= i_axi_arlen;
filling_fifo <= (i_axi_arlen != 0);
wr_last <= 1'b1;
end
end
 
if (w_reset)
begin
len <= 0;
filling_fifo <= 1'b0;
fifo_head <= 0;
end
end
 
always @(posedge i_axi_clk)
afifo[fifo_head] <= { wr_fifo_id, wr_last, wr_fifo_addr };
 
reg err_state;
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
initial fifo_neck = 0;
initial fifo_torso = 0;
initial err_state = 0;
always @(posedge i_axi_clk)
begin
if (w_reset)
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
 
fifo_neck <= 0;
fifo_torso <= 0;
 
err_state <= 0;
end else if (o_wb_stb)
begin
if (i_wb_err)
begin
o_wb_stb <= 1'b0;
err_state <= 1'b1;
end else if (!i_wb_stall)
begin
o_wb_stb <= (fifo_head != next_neck);
// && (WBMODE != "B3SINGLE");
// o_wb_cyc <= (WBMODE != "B3SINGLE");
end
 
if (!i_wb_stall)
fifo_neck <= next_neck;
if (i_wb_ack)
fifo_torso <= next_torso;
end else if (err_state)
begin
fifo_torso <= next_torso;
if (fifo_neck == next_torso)
err_state <= 1'b0;
o_wb_cyc <= 1'b0;
end else if (o_wb_cyc)
begin
if (i_wb_ack)
fifo_torso <= next_torso;
if (fifo_neck == next_torso)
o_wb_cyc <= 1'b0;
end else if (fifo_neck != fifo_head)
begin
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
end
end
 
always @(posedge i_axi_clk)
fifo_at_neck <= afifo[fifo_neck];
assign o_wb_addr = fifo_at_neck[(AW-1):0];
 
always @(posedge i_axi_clk)
dfifo[fifo_torso] <= { (err_state)||(i_wb_err), i_wb_data };
 
 
always @(posedge i_axi_clk)
if (w_reset)
fifo_tail <= 0;
else if ((o_axi_rvalid)&&(i_axi_rready))
fifo_tail <= next_tail;
 
always @(posedge i_axi_clk)
begin
afifo_at_tail <= afifo[fifo_tail];
dfifo_at_tail <= dfifo[fifo_tail];
// o_axi_rdata <= dfifo[fifo_tail];
// o_axi_rlast <= afifo[fifo_tail];
// o_axi_rid <= afifo[fifo_tail];
end
assign o_axi_rlast = afifo_at_tail[AW];
assign o_axi_rid = afifo_at_tail[(C_AXI_ID_WIDTH+AW):(AW+1)];
assign o_axi_rresp = { (2){dfifo_at_tail[DW]} };
assign o_axi_rdata = dfifo_at_tail[(DW-1):0];
 
initial o_axi_rvalid = 1'b0;
always @(posedge i_axi_clk)
if (w_reset)
o_axi_rvalid <= 0;
else if (fifo_tail != fifo_neck)
o_axi_rvalid <= (fifo_tail != fifo_neck + 1);
 
assign o_axi_arready = (!fifo_full)&&(!filling_fifo);
 
// Make Verilator happy
// verilator lint_off UNUSED
wire [(C_AXI_ID_WIDTH+1)+(C_AXI_ADDR_WIDTH-AW)
+3+1+1+4+3+4-1:0] unused;
assign unused = { i_axi_arsize, i_axi_arburst[1],
i_axi_arlock, i_axi_arcache, i_axi_arprot,
i_axi_arqos,
fifo_at_neck[(C_AXI_ID_WIDTH+AW+1)-1:AW],
i_axi_araddr[(C_AXI_ADDR_WIDTH-AW-1):0] };
// verilator lint_on UNUSED
 
`ifdef FORMAL
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge i_axi_clk)
f_past_valid <= 1'b1;
 
wire [LGFIFO-1:0] f_fifo_used, f_fifo_neck_used,
f_fifo_torso_used;
assign f_fifo_used = fifo_head - fifo_tail;
assign f_fifo_neck_used = fifo_head - fifo_neck;
assign f_fifo_torso_used = fifo_head - fifo_torso;
 
always @(*)
assert((f_fifo_used < {(LGFIFO){1'b1}})||(!o_axi_arready));
always @(*)
assert(f_fifo_neck_used <= f_fifo_used);
always @(*)
assert(f_fifo_torso_used <= f_fifo_used);
 
always @(posedge i_axi_clk)
if ((f_past_valid)&&(!$past(i_axi_reset_n)))
assert(f_fifo_used == 0);
 
`endif
endmodule
/aximwr2wbsp.v
0,0 → 1,315
////////////////////////////////////////////////////////////////////////////////
//
// Filename: aximwr2wbsp.v
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose: Convert the three AXI4 write channels to a single wishbone
// channel to write the results.
//
// Still need to implement the lock feature.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
//
module aximwr2wbsp #(
parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width
parameter AW = 26,
parameter LGFIFO = 4
) (
input wire i_axi_clk, // System clock
input wire i_axi_reset_n,
 
// AXI write address channel signals
output wire o_axi_awready, // Slave is ready to accept
input wire [C_AXI_ID_WIDTH-1:0] i_axi_awid, // Write ID
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_awaddr, // Write address
input wire [7:0] i_axi_awlen, // Write Burst Length
input wire [2:0] i_axi_awsize, // Write Burst size
input wire [1:0] i_axi_awburst, // Write Burst type
input wire [0:0] i_axi_awlock, // Write lock type
input wire [3:0] i_axi_awcache, // Write Cache type
input wire [2:0] i_axi_awprot, // Write Protection type
input wire [3:0] i_axi_awqos, // Write Quality of Svc
input wire i_axi_awvalid, // Write address valid
// AXI write data channel signals
output wire o_axi_wready, // Write data ready
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_wdata, // Write data
input wire [C_AXI_DATA_WIDTH/8-1:0] i_axi_wstrb, // Write strobes
input wire i_axi_wlast, // Last write transaction
input wire i_axi_wvalid, // Write valid
// AXI write response channel signals
output wire [C_AXI_ID_WIDTH-1:0] o_axi_bid, // Response ID
output wire [1:0] o_axi_bresp, // Write response
output wire o_axi_bvalid, // Write reponse valid
input wire i_axi_bready, // Response ready
// We'll share the clock and the reset
output reg o_wb_cyc,
output reg o_wb_stb,
output wire [(AW-1):0] o_wb_addr,
output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data,
output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel,
input wire i_wb_ack,
input wire i_wb_stall,
// input [(C_AXI_DATA_WIDTH-1):0] i_wb_data,
input wire i_wb_err
);
 
localparam DW = C_AXI_DATA_WIDTH;
 
wire w_reset;
assign w_reset = (i_axi_reset_n == 1'b0);
 
//
//
//
reg [LGFIFO-1:0] fifo_ahead, fifo_dhead, fifo_neck, fifo_torso,
fifo_tail;
wire [LGFIFO-1:0] next_ahead, next_dhead, next_neck, next_torso,
next_tail;
assign next_ahead = fifo_ahead + 1;
assign next_dhead = fifo_dhead + 1;
assign next_neck = fifo_neck + 1;
assign next_torso = fifo_torso + 1;
assign next_tail = fifo_tail + 1;
 
reg [(C_AXI_ID_WIDTH+AW)-1:0] afifo [0:((1<<(LGFIFO))-1)];
reg [(DW + DW/8)-1:0] dfifo [0:((1<<(LGFIFO))-1)];
reg [((1<<(LGFIFO))-1):0] efifo;
 
reg [(C_AXI_ID_WIDTH+AW)-1:0] afifo_at_neck, afifo_at_tail;
reg [(DW + DW/8)-1:0] dfifo_at_neck;
reg efifo_at_tail;
 
reg filling_fifo, incr;
reg [7:0] len;
reg [(AW-1):0] wr_fifo_addr;
reg [(C_AXI_ID_WIDTH-1):0] wr_fifo_id;
 
wire axi_aw_req, axi_wr_req;
assign axi_aw_req = (o_axi_awready)&&(i_axi_awvalid);
assign axi_wr_req = (o_axi_wready)&&(i_axi_wvalid);
 
wire fifo_full;
assign fifo_full = (next_ahead == fifo_tail)||(next_dhead ==fifo_tail);
 
initial fifo_ahead = 0;
initial fifo_dhead = 0;
always @(posedge i_axi_clk)
begin
if (filling_fifo)
begin
if (!fifo_full)
begin
len <= len - 1;
if (len == 1)
filling_fifo <= 1'b0;
fifo_ahead <= next_ahead;
wr_fifo_addr <= wr_fifo_addr
+ {{(AW-1){1'b0}},incr};
end
end else begin
wr_fifo_addr <= i_axi_awaddr[(C_AXI_ADDR_WIDTH-1):(C_AXI_ADDR_WIDTH-AW)];
wr_fifo_id <= i_axi_awid;
incr <= i_axi_awburst[0];
if (axi_aw_req)
begin
fifo_ahead <= next_ahead;
len <= i_axi_awlen;
filling_fifo <= (i_axi_awlen != 0);
end
end
 
if (w_reset)
begin
fifo_ahead <= 0;
len <= 0;
filling_fifo <= 0;
end
end
 
always @(posedge i_axi_clk)
afifo[fifo_ahead] <= { wr_fifo_id, wr_fifo_addr };
 
initial fifo_dhead = 0;
always @(posedge i_axi_clk)
if (w_reset)
fifo_dhead <= 0;
else if (axi_wr_req)
fifo_dhead <= next_dhead;
 
always @(posedge i_axi_clk)
dfifo[fifo_dhead] <= { i_axi_wstrb, i_axi_wdata };
 
 
reg err_state;
 
initial o_wb_cyc = 0;
initial o_wb_stb = 0;
initial fifo_neck = 0;
initial fifo_torso = 0;
initial err_state = 0;
always @(posedge i_axi_clk)
begin
if (w_reset)
begin
o_wb_cyc <= 0;
o_wb_stb <= 0;
 
fifo_neck <= 0;
fifo_torso <= 0;
 
err_state <= 0;
end else if (o_wb_stb)
begin
if (i_wb_err)
begin
o_wb_stb <= 1'b0;
err_state <= 1'b0;
end
else if (!i_wb_stall)
o_wb_stb <= (fifo_ahead != next_neck)
&&(fifo_dhead != next_neck);
 
if ((!i_wb_stall)&&(fifo_neck != fifo_ahead)&&(fifo_neck != fifo_dhead))
fifo_neck <= next_neck;
 
if (i_wb_ack)
fifo_torso <= next_torso;
 
if (fifo_neck == next_torso)
o_wb_cyc <= 1'b0;
end else if (err_state)
begin
o_wb_cyc <= 1'b0;
if (fifo_torso != fifo_neck)
fifo_torso <= next_torso;
if (fifo_neck == next_torso)
err_state <= 1'b0;
end else if (o_wb_cyc)
begin
if (i_wb_ack)
fifo_torso <= next_torso;
if (fifo_neck == next_torso)
o_wb_cyc <= 1'b0;
end else if((fifo_ahead!= fifo_neck)&&(fifo_dhead != fifo_neck))
begin
o_wb_cyc <= 1;
o_wb_stb <= 1;
end
end
 
initial efifo = 0;
always @(posedge i_axi_clk)
if(w_reset)
efifo <= 0;
else
efifo[fifo_torso] <= (i_wb_err)||(err_state);
 
always @(posedge i_axi_clk)
afifo_at_neck <= afifo[fifo_neck];
assign o_wb_addr = afifo_at_neck[(AW-1):0];
 
always @(posedge i_axi_clk)
dfifo_at_neck <= dfifo[fifo_neck];
assign o_wb_data = dfifo_at_neck[DW-1:0];
assign o_wb_sel = dfifo_at_neck[(DW+(DW/8))-1:DW];
 
initial fifo_tail = 0;
always @(posedge i_axi_clk)
if (w_reset)
fifo_tail <= 0;
else if ((o_axi_bvalid)&&(i_axi_bready))
fifo_tail <= next_tail;
 
always @(posedge i_axi_clk)
afifo_at_tail <= afifo[fifo_tail];
always @(posedge i_axi_clk)
efifo_at_tail <= efifo[fifo_tail];
 
assign o_axi_bid = afifo_at_tail[(C_AXI_ID_WIDTH+AW)-1:AW];
assign o_axi_bresp = {(2){efifo_at_tail}};
 
assign o_axi_bvalid = (fifo_tail != fifo_torso);
assign o_axi_awready = (next_ahead != fifo_tail);
assign o_axi_wready = (next_dhead != fifo_tail);
 
// Make Verilator happy
// verilator lint_on UNUSED
wire [(C_AXI_ID_WIDTH+AW+C_AXI_ADDR_WIDTH-AW)
+(1)+1+3+1+4+3+4-1:0] unused;
assign unused = { i_axi_awburst[1], i_axi_awsize,
i_axi_awlock, i_axi_awcache, i_axi_awprot,
i_axi_awqos, i_axi_wlast,
afifo_at_neck[(C_AXI_ID_WIDTH+AW-1):AW],
afifo_at_tail[(AW-1):0],
i_axi_awaddr[(C_AXI_ADDR_WIDTH-AW)-1:0] };
// verilator lint_off UNUSED
 
`ifdef FORMAL
always @(*)
assume(!i_axi_awburst[1]);
 
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge i_axi_clk)
f_past_valid <= 1'b1;
 
wire [LGFIFO-1:0] f_afifo_used, f_dfifo_used,
f_fifo_neck_used, f_fifo_torso_used;
 
assign f_afifo_used = fifo_ahead - fifo_tail;
assign f_dfifo_used = fifo_dhead - fifo_tail;
assign f_fifo_neck_used = fifo_dhead - fifo_neck;
assign f_fifo_torso_used = fifo_dhead - fifo_torso;
 
always @(*)
assert((f_afifo_used < {(LGFIFO){1'b1}})||(!o_axi_awready));
always @(*)
assert((f_dfifo_used < {(LGFIFO){1'b1}})||(!o_axi_wready));
always @(*)
assert(f_fifo_neck_used <= f_dfifo_used);
always @(*)
assert(f_fifo_torso_used <= f_dfifo_used);
always @(*)
assert((!o_wb_stb)||
((fifo_neck != fifo_ahead)
&&(fifo_neck != fifo_dhead)));
`endif
endmodule
 
/migsdram.v
8,14 → 8,21
// of the wb2axip project itself, but rather it is an example
// of how the wb2axip project can be used to connect a MIG generated
// IP component.
//
//
// This implementation depends upon the existence of a MIG generated
// core, named "mig_axis", and illustrates how such a core might be
// connected to the wbm2axip bridge. Specific options of the mig_axis
// setup include 6 identifier bits, and a full-sized bus width of 128
// bits. These two settings are both appropriate for driving a DDR3
// memory (whose minimum transfer size is 128 bits), but may need to be
// adjusted to support other memories.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
28,7 → 35,7
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
39,6 → 46,8
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset,
// Wishbone components
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
71,14 → 80,14
: RAMABITS-5)); // (WBDATAWIDTH==256)
localparam SELW= (WBDATAWIDTH/8);
//
input i_clk, i_clk_200mhz, i_rst;
output o_sys_clk;
input wire i_clk, i_clk_200mhz, i_rst;
output wire o_sys_clk;
output reg o_sys_reset;
//
input i_wb_cyc, i_wb_stb, i_wb_we;
input [(AW-1):0] i_wb_addr;
input [(DW-1):0] i_wb_data;
input [(SELW-1):0] i_wb_sel;
input wire i_wb_cyc, i_wb_stb, i_wb_we;
input wire [(AW-1):0] i_wb_addr;
input wire [(DW-1):0] i_wb_data;
input wire [(SELW-1):0] i_wb_sel;
output wire o_wb_ack, o_wb_stall;
output wire [(DW-1):0] o_wb_data;
output wire o_wb_err;
135,6 → 144,7
wire [2:0] s_axi_arprot;
wire [3:0] s_axi_arqos;
wire s_axi_arvalid;
wire s_axi_arready;
// Read response/data channel
wire [(AXIDWIDTH-1):0] s_axi_rid;
wire [(AXIWIDTH-1):0] s_axi_rdata;
141,6 → 151,7
wire [1:0] s_axi_rresp;
wire s_axi_rlast;
wire s_axi_rvalid;
wire s_axi_rready;
 
// Other wires ...
wire init_calib_complete, mmcm_locked;
/wbarbiter.v
0,0 → 1,303
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbarbiter.v
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose: This is a priority bus arbiter. It allows two separate wishbone
// masters to connect to the same bus, while also guaranteeing
// that one master can have the bus with no delay any time the other
// master is not using the bus. The goal is to eliminate as much
// combinatorial logic as possible, while still guarateeing minimum access
// time for the priority (last, or alternate) channel.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
`define WBA_ALTERNATING
//
module wbarbiter(i_clk, i_reset,
// Bus A -- the priority bus
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel,
o_a_ack, o_a_stall, o_a_err,
// Bus B
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
o_b_ack, o_b_stall, o_b_err,
// Combined/arbitrated bus
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
parameter DW=32, AW=32;
parameter SCHEME="ALTERNATING";
parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0;
`ifdef FORMAL
parameter F_LGDEPTH=3;
`endif
 
//
input wire i_clk, i_reset;
// Bus A
input wire i_a_cyc, i_a_stb, i_a_we;
input wire [(AW-1):0] i_a_adr;
input wire [(DW-1):0] i_a_dat;
input wire [(DW/8-1):0] i_a_sel;
output wire o_a_ack, o_a_stall, o_a_err;
// Bus B
input wire i_b_cyc, i_b_stb, i_b_we;
input wire [(AW-1):0] i_b_adr;
input wire [(DW-1):0] i_b_dat;
input wire [(DW/8-1):0] i_b_sel;
output wire o_b_ack, o_b_stall, o_b_err;
//
output wire o_cyc, o_stb, o_we;
output wire [(AW-1):0] o_adr;
output wire [(DW-1):0] o_dat;
output wire [(DW/8-1):0] o_sel;
input wire i_ack, i_stall, i_err;
 
// Go high immediately (new cycle) if ...
// Previous cycle was low and *someone* is requesting a bus cycle
// Go low immadiately if ...
// We were just high and the owner no longer wants the bus
// WISHBONE Spec recommends no logic between a FF and the o_cyc
// This violates that spec. (Rec 3.15, p35)
reg r_a_owner;
 
assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc;
initial r_a_owner = 1'b1;
 
generate if (SCHEME == "PRIORITY")
begin : PRI
 
always @(posedge i_clk)
if (!i_b_cyc)
r_a_owner <= 1'b1;
// Allow B to set its CYC line w/o activating this
// interface
else if ((i_b_stb)&&(!i_a_cyc))
r_a_owner <= 1'b0;
 
end else if (SCHEME == "ALTERNATING")
begin : ALT
 
reg last_owner;
initial last_owner = 1'b0;
always @(posedge i_clk)
if ((i_a_cyc)&&(r_a_owner))
last_owner <= 1'b1;
else if ((i_b_cyc)&&(!r_a_owner))
last_owner <= 1'b0;
 
always @(posedge i_clk)
if ((!i_a_cyc)&&(!i_b_cyc))
r_a_owner <= !last_owner;
else if ((r_a_owner)&&(!i_a_cyc))
begin
 
if (i_b_stb)
r_a_owner <= 1'b0;
 
end else if ((!r_a_owner)&&(!i_b_cyc))
begin
 
if (i_a_stb)
r_a_owner <= 1'b1;
 
end
 
end else // if (SCHEME == "LAST")
begin : LST
always @(posedge i_clk)
if ((!i_a_cyc)&&(i_b_stb))
r_a_owner <= 1'b0;
else if ((!i_b_cyc)&&(i_a_stb))
r_a_owner <= 1'b1;
end endgenerate
 
 
// Realistically, if neither master owns the bus, the output is a
// don't care. Thus we trigger off whether or not 'A' owns the bus.
// If 'B' owns it all we care is that 'A' does not. Likewise, if
// neither owns the bus than the values on the various lines are
// irrelevant.
assign o_we = (r_a_owner) ? i_a_we : i_b_we;
 
generate if (OPT_ZERO_ON_IDLE)
begin
//
// OPT_ZERO_ON_IDLE will use up more logic and may even slow
// down the master clock if set. However, it may also reduce
// the power used by the FPGA by preventing things from toggling
// when the bus isn't in use. The option is here because it
// also makes it a lot easier to look for when things happen
// on the bus via VERILATOR when timing and logic counts
// don't matter.
//
assign o_stb = (o_cyc)? ((r_a_owner) ? i_a_stb : i_b_stb):0;
assign o_adr = (o_stb)? ((r_a_owner) ? i_a_adr : i_b_adr):0;
assign o_dat = (o_stb)? ((r_a_owner) ? i_a_dat : i_b_dat):0;
assign o_sel = (o_stb)? ((r_a_owner) ? i_a_sel : i_b_sel):0;
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0;
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
end else begin
 
assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb;
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
 
// We cannot allow the return acknowledgement to ever go high if
// the master in question does not own the bus. Hence we force
// it low if the particular master doesn't own the bus.
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0;
 
// Stall must be asserted on the same cycle the input master
// asserts the bus, if the bus isn't granted to him.
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
 
//
//
assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (!r_a_owner) ? i_err : 1'b0;
end endgenerate
 
// Make Verilator happy
// verilator lint_off UNUSED
wire unused;
assign unused = i_reset;
// verilator lint_on UNUSED
 
`ifdef FORMAL
 
`ifdef WBARBITER
reg f_last_clk;
initial assume(!i_clk);
always @($global_clock)
begin
assume(i_clk != f_last_clk);
f_last_clk <= i_clk;
end
`define ASSUME assume
`else
`define ASSUME assert
`endif
 
reg f_past_valid;
initial f_past_valid = 1'b0;
always @($global_clock)
f_past_valid <= 1'b1;
 
initial `ASSUME(!i_a_cyc);
initial `ASSUME(!i_a_stb);
 
initial `ASSUME(!i_b_cyc);
initial `ASSUME(!i_b_stb);
 
initial `ASSUME(!i_ack);
initial `ASSUME(!i_err);
 
always @(posedge i_clk)
begin
if (o_cyc)
assert((i_a_cyc)||(i_b_cyc));
if ((f_past_valid)&&($past(o_cyc))&&(o_cyc))
assert($past(r_a_owner) == r_a_owner);
end
 
wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding,
f_a_nreqs, f_a_nacks, f_a_outstanding,
f_b_nreqs, f_b_nacks, f_b_outstanding;
 
fwb_master #(.DW(DW), .AW(AW),
.F_MAX_STALL(0),
.F_LGDEPTH(F_LGDEPTH),
.F_MAX_ACK_DELAY(0),
.F_OPT_RMW_BUS_OPTION(1),
.F_OPT_DISCONTINUOUS(1))
f_wbm(i_clk, i_reset,
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel,
i_ack, i_stall, 32'h0, i_err,
f_nreqs, f_nacks, f_outstanding);
 
fwb_slave #(.DW(DW), .AW(AW),
.F_MAX_STALL(0),
.F_LGDEPTH(F_LGDEPTH),
.F_MAX_ACK_DELAY(0),
.F_OPT_RMW_BUS_OPTION(1),
.F_OPT_DISCONTINUOUS(1))
f_wba(i_clk, i_reset,
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel,
o_a_ack, o_a_stall, 32'h0, o_a_err,
f_a_nreqs, f_a_nacks, f_a_outstanding);
 
fwb_slave #(.DW(DW), .AW(AW),
.F_MAX_STALL(0),
.F_LGDEPTH(F_LGDEPTH),
.F_MAX_ACK_DELAY(0),
.F_OPT_RMW_BUS_OPTION(1),
.F_OPT_DISCONTINUOUS(1))
f_wbb(i_clk, i_reset,
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
o_b_ack, o_b_stall, 32'h0, o_b_err,
f_b_nreqs, f_b_nacks, f_b_outstanding);
 
always @(posedge i_clk)
if (r_a_owner)
begin
assert(f_b_nreqs == 0);
assert(f_b_nacks == 0);
assert(f_a_outstanding == f_outstanding);
end else begin
assert(f_a_nreqs == 0);
assert(f_a_nacks == 0);
assert(f_b_outstanding == f_outstanding);
end
 
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))
&&($past(i_a_stb))&&(!$past(i_b_cyc)))
assert(r_a_owner);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))
&&(!$past(i_a_cyc))&&($past(i_b_stb)))
assert(!r_a_owner);
 
always @(posedge i_clk)
if ((f_past_valid)&&(r_a_owner != $past(r_a_owner)))
assert(!$past(o_cyc));
 
`endif
endmodule
 
/wbm2axisp.v
1,6 → 1,6
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbm2axisp.v
// Filename: wbm2axisp.v (Wishbone master to AXI slave, pipelined)
//
// Project: Pipelined Wishbone to AXI converter
//
19,7 → 19,7
// transiting from the Wishbone (as master) to the AXI bus (as slave) and
// back again.
//
// Since the AXI bus allows transactions to be reordered, whereas the
// Since the AXI bus allows transactions to be reordered, whereas the
// wishbone does not, this core can be configured to reorder return
// transactions as well.
//
52,14 → 52,16
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module wbm2axisp #(
parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
parameter C_AXI_ID_WIDTH = 3, // The AXI id width used for R&W
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width
parameter DW = 32, // Wishbone data width
parameter AW = 26, // Wishbone address width
parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width (log wordsize)
parameter DW = 8, // Wishbone data width
parameter AW = 26, // Wishbone address width (log wordsize)
parameter [0:0] STRICT_ORDER = 1 // Reorder, or not? 0 -> Reorder
) (
input i_clk, // System clock
// input i_reset,// Wishbone reset signal--unused
76,20 → 78,20
output wire [2:0] o_axi_awprot, // Write Protection type
output wire [3:0] o_axi_awqos, // Write Quality of Svc
output reg o_axi_awvalid, // Write address valid
 
// AXI write data channel signals
input i_axi_wready, // Write data ready
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data
output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes
output wire o_axi_wlast, // Last write transaction
output wire o_axi_wlast, // Last write transaction
output reg o_axi_wvalid, // Write valid
 
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID
input [1:0] i_axi_bresp, // Write response
input i_axi_bvalid, // Write reponse valid
output wire o_axi_bready, // Response ready
 
// AXI read address channel signals
input i_axi_arready, // Read address ready
output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID
102,8 → 104,8
output wire [2:0] o_axi_arprot, // Read Protection type
output wire [3:0] o_axi_arqos, // Read Protection type
output reg o_axi_arvalid, // Read address valid
// AXI read data channel signals
 
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID
input [1:0] i_axi_rresp, // Read response
input i_axi_rvalid, // Read reponse valid
128,17 → 130,30
// Parameter declarations
//*****************************************************************************
 
localparam CTL_SIG_WIDTH = 3; // Control signal width
localparam RD_STS_WIDTH = 16; // Read status signal width
localparam WR_STS_WIDTH = 16; // Write status signal width
localparam LG_AXI_DW = ( C_AXI_DATA_WIDTH == 8) ? 3
: ((C_AXI_DATA_WIDTH == 16) ? 4
: ((C_AXI_DATA_WIDTH == 32) ? 5
: ((C_AXI_DATA_WIDTH == 64) ? 6
: ((C_AXI_DATA_WIDTH == 128) ? 7
: 8))));
 
localparam LG_WB_DW = ( DW == 8) ? 3
: ((DW == 16) ? 4
: ((DW == 32) ? 5
: ((DW == 64) ? 6
: ((DW == 128) ? 7
: 8))));
localparam LGFIFOLN = C_AXI_ID_WIDTH;
localparam FIFOLN = (1<<LGFIFOLN);
 
 
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
 
// Things we're not changing ...
assign o_axi_awlen = 8'h0; // Burst length is one
assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
assign o_axi_awlen = 8'h0; // Burst length is one
assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
assign o_axi_awburst = 2'b01; // Incrementing address (ignored)
assign o_axi_arburst = 2'b01; // Incrementing address (ignored)
assign o_axi_awlock = 1'b0; // Normal signaling
147,159 → 162,296
assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer
assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access
assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access
assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
 
reg wb_mid_cycle, wb_last_cyc_stb, wb_mid_abort;
wire wb_cyc_stb;
// Command logic
// Transaction ID logic
wire [(LGFIFOLN-1):0] fifo_head;
reg [(C_AXI_ID_WIDTH-1):0] transaction_id;
 
initial transaction_id = 0;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
transaction_id <= transaction_id + 1'b1;
 
assign fifo_head = transaction_id;
 
wire [(DW/8-1):0] no_sel;
wire [(LG_AXI_DW-4):0] axi_bottom_addr;
assign no_sel = 0;
assign axi_bottom_addr = 0;
 
 
// Write address logic
 
initial o_axi_awvalid = 0;
always @(posedge i_clk)
o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
||(o_axi_awvalid)&&(!i_axi_awready);
 
generate
if (DW == 32)
 
initial o_axi_awid = -1;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
o_axi_awid <= transaction_id;
 
if (C_AXI_DATA_WIDTH == DW)
begin
always @(posedge i_clk)
if (!o_wb_stall) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:2], 4'b00 };
end else if (DW == 128)
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:0], axi_bottom_addr };
end else if (C_AXI_DATA_WIDTH / DW == 2)
begin
 
always @(posedge i_clk)
if (!o_wb_stall) // 28 bit address ...
o_axi_awaddr <= { i_wb_addr[AW-1:0], 4'b00 };
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:1], axi_bottom_addr };
 
end else if (C_AXI_DATA_WIDTH / DW == 4)
begin
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:2], axi_bottom_addr };
end endgenerate
 
reg [5:0] transaction_id;
always @(posedge i_clk)
if (!i_wb_cyc)
transaction_id <= 6'h00;
else if ((i_wb_stb)&&(~o_wb_stall))
transaction_id <= transaction_id + 6'h01;
always @(posedge i_clk)
if ((i_wb_stb)&&(~o_wb_stall))
o_axi_awid <= transaction_id;
 
// Read address logic
assign o_axi_arid = o_axi_awid;
assign o_axi_arid = o_axi_awid;
assign o_axi_araddr = o_axi_awaddr;
assign o_axi_arlen = o_axi_awlen;
assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
initial o_axi_arvalid = 1'b0;
always @(posedge i_clk)
o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
||(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);
||(o_axi_arvalid)&&(!i_axi_arready);
 
 
// Write data logic
generate
if (DW == 32)
if (C_AXI_DATA_WIDTH == DW)
begin
 
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
if ((i_wb_stb)&&(!o_wb_stall))
o_axi_wdata <= i_wb_data;
 
always @(posedge i_clk)
if (!o_wb_stall)
case(i_wb_addr[1:0])
2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0,i_wb_sel};
2'b01:o_axi_wstrb<={ 4'h0, 4'h0,i_wb_sel, 4'h0};
2'b10:o_axi_wstrb<={ 4'h0,i_wb_sel, 4'h0, 4'h0};
2'b11:o_axi_wstrb<={i_wb_sel, 4'h0, 4'h0, 4'h0};
if ((i_wb_stb)&&(!o_wb_stall))
o_axi_wstrb<= i_wb_sel;
 
end else if (C_AXI_DATA_WIDTH/2 == DW)
begin
 
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
o_axi_wdata <= { i_wb_data, i_wb_data };
 
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
case(i_wb_addr[0])
1'b0:o_axi_wstrb<={ no_sel,i_wb_sel };
1'b1:o_axi_wstrb<={i_wb_sel, no_sel };
endcase
end else if (DW == 128)
 
end else if (C_AXI_DATA_WIDTH/4 == DW)
begin
 
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wdata <= i_wb_data;
if ((i_wb_stb)&&(!o_wb_stall))
o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
 
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wstrb <= i_wb_sel;
if ((i_wb_stb)&&(!o_wb_stall))
case(i_wb_addr[1:0])
2'b00:o_axi_wstrb<={ no_sel, no_sel, no_sel, i_wb_sel };
2'b01:o_axi_wstrb<={ no_sel, no_sel, i_wb_sel, no_sel };
2'b10:o_axi_wstrb<={ no_sel, i_wb_sel, no_sel, no_sel };
2'b11:o_axi_wstrb<={ i_wb_sel, no_sel, no_sel, no_sel };
endcase
 
end endgenerate
 
assign o_axi_wlast = 1'b1;
initial o_axi_wvalid = 0;
always @(posedge i_clk)
o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
||(o_axi_wvalid)&&(!i_axi_wready);
 
// Read data channel / response logic
// Read data channel / response logic
assign o_axi_rready = 1'b1;
assign o_axi_bready = 1'b1;
 
wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
assign n_fifo_head = fifo_head+1'b1;
assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
 
 
wire w_fifo_full;
reg [(LGFIFOLN-1):0] fifo_tail;
 
generate
if (STRICT_ORDER == 0)
if (C_AXI_DATA_WIDTH == DW)
begin
// Reorder FIFO
//
localparam LGFIFOLN = C_AXI_ID_WIDTH;
localparam FIFOLN = (1<<LGFIFOLN);
// FIFO reorder buffer
reg [(LGFIFOLN-1):0] fifo_tail;
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
reg [(FIFOLN-1):0] reorder_fifo_valid;
reg [(FIFOLN-1):0] reorder_fifo_err;
if (STRICT_ORDER == 0)
begin
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
 
initial reorder_fifo_valid = 0;
initial reorder_fifo_err = 0;
always @(posedge i_clk)
if ((o_axi_rready)&&(i_axi_rvalid))
reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
always @(posedge i_clk)
o_wb_data <= reorder_fifo_data[fifo_tail];
end else begin
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;
 
if (DW == 32)
always @(posedge i_clk)
reorder_fifo_data <= i_axi_rdata;
always @(posedge i_clk)
o_wb_data <= reorder_fifo_data;
end
end else if (C_AXI_DATA_WIDTH / DW == 2)
begin
reg reorder_fifo_addr [0:(FIFOLN-1)];
 
reg low_addr;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
low_addr <= i_wb_addr[0];
always @(posedge i_clk)
if ((o_axi_arvalid)&&(i_axi_arready))
reorder_fifo_addr[o_axi_arid] <= low_addr;
 
if (STRICT_ORDER == 0)
begin
reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
 
always @(posedge i_clk)
if ((o_axi_rready)&&(i_axi_rvalid))
reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
always @(posedge i_clk)
reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
always @(posedge i_clk)
case(reorder_fifo_addr[fifo_tail])
1'b0: o_wb_data <=reorder_fifo_data[fifo_tail][( DW-1): 0 ];
1'b1: o_wb_data <=reorder_fifo_data[fifo_tail][(2*DW-1):( DW)];
endcase
end else begin
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;
 
reg [1:0] low_addr;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
low_addr <= i_wb_addr[1:0];
reorder_fifo_data <= i_axi_rdata;
always @(posedge i_clk)
if ((o_axi_arvalid)&&(i_axi_arready))
reorder_fifo_addr[o_axi_arid] <= low_addr;
case(reorder_fifo_addr[fifo_tail])
1'b0: o_wb_data <=reorder_fifo_data[( DW-1): 0 ];
1'b1: o_wb_data <=reorder_fifo_data[(2*DW-1):( DW)];
endcase
end
end else if (C_AXI_DATA_WIDTH / DW == 4)
begin
reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
 
 
reg [1:0] low_addr;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
low_addr <= i_wb_addr[1:0];
always @(posedge i_clk)
if ((o_axi_arvalid)&&(i_axi_arready))
reorder_fifo_addr[o_axi_arid] <= low_addr;
 
if (STRICT_ORDER == 0)
begin
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
 
always @(posedge i_clk)
if ((o_axi_rready)&&(i_axi_rvalid))
reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
always @(posedge i_clk)
case(reorder_fifo_addr[fifo_tail][1:0])
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][( DW-1): 0 ];
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][(2*DW-1):( DW)];
2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][(3*DW-1):(2*DW)];
2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][(4*DW-1):(3*DW)];
endcase
end else begin
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;
 
end else if (DW == 128)
begin
always @(posedge i_clk)
o_wb_data <= reorder_fifo_data[fifo_tail];
reorder_fifo_data <= i_axi_rdata;
always @(posedge i_clk)
case(reorder_fifo_addr[fifo_tail][1:0])
2'b00: o_wb_data <=reorder_fifo_data[( DW-1): 0];
2'b01: o_wb_data <=reorder_fifo_data[(2*DW-1):( DW)];
2'b10: o_wb_data <=reorder_fifo_data[(3*DW-1):(2*DW)];
2'b11: o_wb_data <=reorder_fifo_data[(4*DW-1):(3*DW)];
endcase
end
end
 
endgenerate
 
wire [(LGFIFOLN-1):0] fifo_head;
assign fifo_head = transaction_id;
wire axi_rd_ack, axi_wr_ack, axi_ard_req, axi_awr_req, axi_wr_req,
axi_rd_err, axi_wr_err;
//
assign axi_ard_req = (o_axi_arvalid)&&(i_axi_arready);
assign axi_awr_req = (o_axi_awvalid)&&(i_axi_awready);
assign axi_wr_req = (o_axi_wvalid )&&(i_axi_wready);
//
assign axi_rd_ack = (i_axi_rvalid)&&(o_axi_rready);
assign axi_wr_ack = (i_axi_bvalid)&&(o_axi_bready);
assign axi_rd_err = (axi_rd_ack)&&(i_axi_rresp[1]);
assign axi_wr_err = (axi_wr_ack)&&(i_axi_bresp[1]);
 
// Let's do some math to figure out where the FIFO head will
// point to next, but let's also insist that it be LGFIFOLN
// bits in size as well. This'll be part of the fifo_full
// calculation below.
wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
assign n_fifo_head = fifo_head+1'b1;
assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
//
// We're going to need a FIFO on the return to make certain that we can
// select the right bits from the return value, in the case where
// DW != the axi data width.
//
// If we aren't using a strict order, this FIFO is can be used as a
// reorder buffer as well, to place our out of order bus responses
// back into order. Responses on the wishbone, however, are *always*
// done in order.
`ifdef FORMAL
reg [31:0] reorder_count;
`endif
integer k;
generate
if (STRICT_ORDER == 0)
begin
// Reorder FIFO
//
// FIFO reorder buffer
reg [(FIFOLN-1):0] reorder_fifo_valid;
reg [(FIFOLN-1):0] reorder_fifo_err;
 
initial reorder_fifo_valid = 0;
initial reorder_fifo_err = 0;
 
 
initial fifo_tail = 0;
initial o_wb_ack = 0;
initial o_wb_err = 0;
always @(posedge i_clk)
begin
if ((i_axi_rvalid)&&(o_axi_rready))
reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
if ((i_axi_rvalid)&&(o_axi_rready))
if (axi_rd_ack)
begin
reorder_fifo_valid[i_axi_rid] <= 1'b1;
reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];
reorder_fifo_err[i_axi_rid] <= axi_rd_err;
end
if ((i_axi_bvalid)&&(o_axi_bready))
if (axi_wr_ack)
begin
reorder_fifo_valid[i_axi_bid] <= 1'b1;
reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];
reorder_fifo_err[i_axi_bid] <= axi_wr_err;
end
 
if (reorder_fifo_valid[fifo_tail])
begin
o_wb_ack <= 1'b1;
o_wb_err <= reorder_fifo_err[fifo_tail];
fifo_tail <= fifo_tail + 6'h1;
o_wb_ack <= (!wb_abort)&&(!reorder_fifo_err[fifo_tail]);
o_wb_err <= (!wb_abort)&&( reorder_fifo_err[fifo_tail]);
fifo_tail <= fifo_tail + 1'b1;
reorder_fifo_valid[fifo_tail] <= 1'b0;
reorder_fifo_err[fifo_tail] <= 1'b0;
end else begin
309,23 → 461,47
 
if (!i_wb_cyc)
begin
reorder_fifo_valid <= {(FIFOLN){1'b0}};
reorder_fifo_err <= {(FIFOLN){1'b0}};
fifo_tail <= 6'h0;
// reorder_fifo_valid <= 0;
// reorder_fifo_err <= 0;
o_wb_err <= 1'b0;
o_wb_ack <= 1'b0;
end
end
 
`ifdef FORMAL
always @(*)
begin
reorder_count = 0;
for(k=0; k<FIFOLN; k=k+1)
if (reorder_fifo_valid[k])
reorder_count = reorder_count + 1;
end
 
reg [(FIFOLN-1):0] f_reorder_fifo_valid_zerod,
f_reorder_fifo_err_zerod;
always @(*)
f_reorder_fifo_valid_zerod <=
((reorder_fifo_valid >> fifo_tail)
| (reorder_fifo_valid << (FIFOLN-fifo_tail)));
always @(*)
assert((f_reorder_fifo_valid_zerod & (~((1<<f_fifo_used)-1)))==0);
//
always @(*)
f_reorder_fifo_err_zerod <=
((reorder_fifo_valid >> fifo_tail)
| (reorder_fifo_valid << (FIFOLN-fifo_tail)));
always @(*)
assert((f_reorder_fifo_err_zerod & (~((1<<f_fifo_used)-1)))==0);
`endif
 
reg r_fifo_full;
initial r_fifo_full = 0;
always @(posedge i_clk)
begin
if (!i_wb_cyc)
r_fifo_full <= 1'b0;
else if ((i_wb_stb)&&(~o_wb_stall)
if ((i_wb_stb)&&(!o_wb_stall)
&&(reorder_fifo_valid[fifo_tail]))
r_fifo_full <= (fifo_tail==n_fifo_head);
else if ((i_wb_stb)&&(~o_wb_stall))
else if ((i_wb_stb)&&(!o_wb_stall))
r_fifo_full <= (fifo_tail==nn_fifo_head);
else if (reorder_fifo_valid[fifo_tail])
r_fifo_full <= 1'b0;
335,29 → 511,626
assign w_fifo_full = r_fifo_full;
end else begin
//
// Strict ordering, but can only read every fourth addresses
// Strict ordering
//
assign w_fifo_full = 1'b0;
reg reorder_fifo_valid;
reg reorder_fifo_err;
 
initial reorder_fifo_valid = 1'b0;
initial reorder_fifo_err = 1'b0;
always @(posedge i_clk)
o_wb_data <= i_axi_rdata[31:0];
if (axi_rd_ack)
begin
reorder_fifo_valid <= 1'b1;
reorder_fifo_err <= axi_rd_err;
end else if (axi_wr_ack)
begin
reorder_fifo_valid <= 1'b1;
reorder_fifo_err <= axi_wr_err;
end else begin
reorder_fifo_valid <= 1'b0;
reorder_fifo_err <= 1'b0;
end
 
always @(*)
reorder_count = (reorder_fifo_valid) ? 1 : 0;
 
initial fifo_tail = 0;
always @(posedge i_clk)
o_wb_ack <= (i_wb_cyc)&&(
((i_axi_rvalid)&&(o_axi_rready))
||((i_axi_bvalid)&&(o_axi_bready)));
if (reorder_fifo_valid)
fifo_tail <= fifo_tail + 6'h1;
 
initial o_wb_ack = 0;
always @(posedge i_clk)
o_wb_err <= (i_wb_cyc)&&((o_wb_err)
||((i_axi_rvalid)&&(i_axi_rresp[1]))
||((i_axi_bvalid)&&(i_axi_bresp[1])));
o_wb_ack <= (reorder_fifo_valid)&&(i_wb_cyc)&&(!wb_abort);
 
initial o_wb_err = 0;
always @(posedge i_clk)
o_wb_err <= (reorder_fifo_err)&&(i_wb_cyc)&&(!wb_abort);
 
reg r_fifo_full;
initial r_fifo_full = 0;
always @(posedge i_clk)
begin
if ((i_wb_stb)&&(!o_wb_stall)
&&(reorder_fifo_valid))
r_fifo_full <= (fifo_tail==n_fifo_head);
else if ((i_wb_stb)&&(!o_wb_stall))
r_fifo_full <= (fifo_tail==nn_fifo_head);
else if (reorder_fifo_valid[fifo_tail])
r_fifo_full <= 1'b0;
else
r_fifo_full <= (fifo_tail==n_fifo_head);
end
 
assign w_fifo_full = r_fifo_full;
end endgenerate
 
//
// Wishbone abort logic
//
 
// Did we just accept something?
always @(posedge i_clk)
wb_cyc_stb <= (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall);
 
// Else, are we mid-cycle?
initial wb_mid_cycle = 0;
always @(posedge i_clk)
if ((fifo_head != fifo_tail)
||(o_axi_arvalid)||(o_axi_awvalid)
||(o_axi_wvalid)
||(i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall))
wb_mid_cycle <= 1'b1;
else
wb_mid_cycle <= 1'b0;
 
always @(posedge i_clk)
if (wb_mid_cycle)
wb_mid_abort <= (wb_mid_abort)||(!i_wb_cyc);
else
wb_mid_abort <= 1'b0;
 
wire wb_abort;
assign wb_abort = ((wb_mid_cycle)&&(!i_wb_cyc))||(wb_mid_abort);
 
// Now, the difficult signal ... the stall signal
// Let's build for a single cycle input ... and only stall if something
// outgoing is valid and nothing is ready.
assign o_wb_stall = (i_wb_cyc)&&(
(w_fifo_full)
(w_fifo_full)||(wb_mid_abort)
||((o_axi_awvalid)&&(!i_axi_awready))
||((o_axi_wvalid )&&(!i_axi_wready ))
||((o_axi_arvalid)&&(!i_axi_arready)));
 
 
/////////////////////////////////////////////////////////////////////////
//
//
//
// Formal methods section
//
// These are only relevant when *proving* that this translator works
//
//
//
/////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
reg f_err_state;
//
`ifdef WBM2AXISP
// If we are the top-level of the design ...
`define ASSUME assume
`define FORMAL_CLOCK assume(i_clk == !f_last_clk); f_last_clk <= i_clk;
`else
`define ASSUME assert
`define FORMAL_CLOCK f_last_clk <= i_clk; // Clock will be given to us valid already
`endif
 
// Parameters
initial assert( (C_AXI_DATA_WIDTH / DW == 4)
||(C_AXI_DATA_WIDTH / DW == 2)
||(C_AXI_DATA_WIDTH == DW));
//
initial assert( C_AXI_ADDR_WIDTH - LG_AXI_DW + LG_WB_DW == AW);
 
//
// Setup
//
 
reg f_past_valid, f_last_clk;
 
always @($global_clock)
begin
`FORMAL_CLOCK
 
// Assume our inputs will only change on the positive edge
// of the clock
if (!$rose(i_clk))
begin
// AXI inputs
`ASSUME($stable(i_axi_awready));
`ASSUME($stable(i_axi_wready));
`ASSUME($stable(i_axi_bid));
`ASSUME($stable(i_axi_bresp));
`ASSUME($stable(i_axi_bvalid));
`ASSUME($stable(i_axi_arready));
`ASSUME($stable(i_axi_rid));
`ASSUME($stable(i_axi_rresp));
`ASSUME($stable(i_axi_rvalid));
`ASSUME($stable(i_axi_rdata));
`ASSUME($stable(i_axi_rlast));
// Wishbone inputs
`ASSUME($stable(i_wb_cyc));
`ASSUME($stable(i_wb_stb));
`ASSUME($stable(i_wb_we));
`ASSUME($stable(i_wb_addr));
`ASSUME($stable(i_wb_data));
`ASSUME($stable(i_wb_sel));
end
end
 
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
 
//////////////////////////////////////////////
//
//
// Assumptions about the WISHBONE inputs
//
//
//////////////////////////////////////////////
wire i_reset;
assign i_reset = !f_past_valid;
 
wire [(C_AXI_ID_WIDTH-1):0] f_wb_nreqs, f_wb_nacks,f_wb_outstanding;
fwb_slave #(.DW(DW),.AW(AW),
.F_MAX_STALL(0),
.F_MAX_ACK_DELAY(0),
.F_LGDEPTH(C_AXI_ID_WIDTH),
.F_MAX_REQUESTS((1<<(C_AXI_ID_WIDTH))-2))
f_wb(i_clk, i_reset,
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
i_wb_data, i_wb_sel,
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
 
wire [(C_AXI_ID_WIDTH-1):0] f_axi_rd_outstanding,
f_axi_wr_outstanding,
f_axi_awr_outstanding;
 
wire [((1<<C_AXI_ID_WIDTH)-1):0] f_axi_rd_id_outstanding,
f_axi_wr_id_outstanding,
f_axi_awr_id_outstanding;
 
faxi_master #(
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.F_AXI_MAXSTALL(3),
.F_AXI_MAXDELAY(3),
.F_STRICT_ORDER(STRICT_ORDER),
.F_CONSECUTIVE_IDS(1'b1),
.F_OPT_BURSTS(1'b0),
.F_CHECK_IDS(1'b1))
f_axi(.i_clk(i_clk), .i_axi_reset_n(!i_reset),
// Write address channel
.i_axi_awready(i_axi_awready),
.i_axi_awid( o_axi_awid),
.i_axi_awaddr( o_axi_awaddr),
.i_axi_awlen( o_axi_awlen),
.i_axi_awsize( o_axi_awsize),
.i_axi_awburst(o_axi_awburst),
.i_axi_awlock( o_axi_awlock),
.i_axi_awcache(o_axi_awcache),
.i_axi_awprot( o_axi_awprot),
.i_axi_awqos( o_axi_awqos),
.i_axi_awvalid(o_axi_awvalid),
// Write data channel
.i_axi_wready( i_axi_wready),
.i_axi_wdata( o_axi_wdata),
.i_axi_wstrb( o_axi_wstrb),
.i_axi_wlast( o_axi_wlast),
.i_axi_wvalid( o_axi_wvalid),
// Write response channel
.i_axi_bid( i_axi_bid),
.i_axi_bresp( i_axi_bresp),
.i_axi_bvalid( i_axi_bvalid),
.i_axi_bready( o_axi_bready),
// Read address channel
.i_axi_arready(i_axi_arready),
.i_axi_arid( o_axi_arid),
.i_axi_araddr( o_axi_araddr),
.i_axi_arlen( o_axi_arlen),
.i_axi_arsize( o_axi_arsize),
.i_axi_arburst(o_axi_arburst),
.i_axi_arlock( o_axi_arlock),
.i_axi_arcache(o_axi_arcache),
.i_axi_arprot( o_axi_arprot),
.i_axi_arqos( o_axi_arqos),
.i_axi_arvalid(o_axi_arvalid),
// Read data channel
.i_axi_rid( i_axi_rid),
.i_axi_rresp( i_axi_rresp),
.i_axi_rvalid( i_axi_rvalid),
.i_axi_rdata( i_axi_rdata),
.i_axi_rlast( i_axi_rlast),
.i_axi_rready( o_axi_rready),
// Counts
.f_axi_rd_outstanding( f_axi_rd_outstanding),
.f_axi_wr_outstanding( f_axi_wr_outstanding),
.f_axi_awr_outstanding( f_axi_awr_outstanding),
// Outstanding ID's
.f_axi_rd_id_outstanding( f_axi_rd_id_outstanding),
.f_axi_wr_id_outstanding( f_axi_wr_id_outstanding),
.f_axi_awr_id_outstanding(f_axi_awr_id_outstanding)
);
 
 
 
//////////////////////////////////////////////
//
//
// Assumptions about the AXI inputs
//
//
//////////////////////////////////////////////
 
 
//////////////////////////////////////////////
//
//
// Assertions about the AXI4 ouputs
//
//
//////////////////////////////////////////////
 
wire [(LGFIFOLN-1):0] f_last_transaction_id;
assign f_last_transaction_id = transaction_id- 1;
always @(posedge i_clk)
if (f_past_valid)
begin
assert(o_axi_awid == f_last_transaction_id);
if ($past(o_wb_stall))
assert($stable(o_axi_awid));
end
 
// Write response channel
always @(posedge i_clk)
// We keep bready high, so the other condition doesn't
// need to be checked
assert(o_axi_bready);
 
// AXI read data channel signals
always @(posedge i_clk)
// We keep o_axi_rready high, so the other condition's
// don't need to be checked here
assert(o_axi_rready);
 
//
// Let's look into write requests
//
initial assert(!o_axi_awvalid);
initial assert(!o_axi_wvalid);
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&($past(i_wb_we))&&(!$past(o_wb_stall)))
begin
// Following any write request that we accept, awvalid and
// wvalid should both be true
assert(o_axi_awvalid);
assert(o_axi_wvalid);
end
 
// Let's assume all responses will come within 120 clock ticks
parameter [(C_AXI_ID_WIDTH-1):0] F_AXI_MAXDELAY = 3,
F_AXI_MAXSTALL = 3; // 7'd120;
localparam [(C_AXI_ID_WIDTH):0] F_WB_MAXDELAY = F_AXI_MAXDELAY + 4;
 
//
// AXI write address channel
//
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_cyc))&&(!$past(o_wb_stall)))
begin
if (!$past(i_wb_stb))
assert(!o_axi_awvalid);
else
assert(o_axi_awvalid == $past(i_wb_we));
end
//
generate
if (C_AXI_DATA_WIDTH == DW)
begin
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_cyc))&&($past(i_wb_stb))&&($past(i_wb_we))
&&(!$past(o_wb_stall)))
assert(o_axi_awaddr == { $past(i_wb_addr[AW-1:0]), axi_bottom_addr });
 
end else if (C_AXI_DATA_WIDTH / DW == 2)
begin
 
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_cyc))&&($past(i_wb_stb))&&($past(i_wb_we))
&&(!$past(o_wb_stall)))
assert(o_axi_awaddr == { $past(i_wb_addr[AW-1:1]), axi_bottom_addr });
 
end else if (C_AXI_DATA_WIDTH / DW == 4)
begin
 
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_cyc))&&($past(i_wb_stb))&&($past(i_wb_we))
&&(!$past(o_wb_stall)))
assert(o_axi_awaddr == { $past(i_wb_addr[AW-1:2]), axi_bottom_addr });
 
end endgenerate
 
//
// AXI write data channel
//
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_cyc))&&(!$past(o_wb_stall)))
begin
if (!$past(i_wb_stb))
assert(!o_axi_wvalid);
else
assert(o_axi_wvalid == $past(i_wb_we));
end
//
generate
if (C_AXI_DATA_WIDTH == DW)
begin
 
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&($past(i_wb_we)))
begin
assert(o_axi_wdata == $past(i_wb_data));
assert(o_axi_wstrb == $past(i_wb_sel));
end
 
end else if (C_AXI_DATA_WIDTH / DW == 2)
begin
 
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&($past(i_wb_we)))
begin
case($past(i_wb_addr[0]))
1'b0: assert(o_axi_wdata[( DW-1): 0] == $past(i_wb_data));
1'b1: assert(o_axi_wdata[(2*DW-1):DW] == $past(i_wb_data));
endcase
 
case($past(i_wb_addr[0]))
1'b0: assert(o_axi_wstrb == { no_sel,$past(i_wb_sel)});
1'b1: assert(o_axi_wstrb == { $past(i_wb_sel),no_sel});
endcase
end
 
end else if (C_AXI_DATA_WIDTH / DW == 4)
begin
 
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&(!$past(o_wb_stall))&&($past(i_wb_we)))
begin
case($past(i_wb_addr[1:0]))
2'b00: assert(o_axi_wdata[ (DW-1): 0 ] == $past(i_wb_data));
2'b00: assert(o_axi_wdata[(2*DW-1):( DW)] == $past(i_wb_data));
2'b00: assert(o_axi_wdata[(3*DW-1):(2*DW)] == $past(i_wb_data));
2'b11: assert(o_axi_wdata[(4*DW-1):(3*DW)] == $past(i_wb_data));
endcase
 
case($past(i_wb_addr[1:0]))
2'b00: assert(o_axi_wstrb == { {(3){no_sel}},$past(i_wb_sel)});
2'b01: assert(o_axi_wstrb == { {(2){no_sel}},$past(i_wb_sel), {(1){no_sel}}});
2'b10: assert(o_axi_wstrb == { {(1){no_sel}},$past(i_wb_sel), {(2){no_sel}}});
2'b11: assert(o_axi_wstrb == { $past(i_wb_sel),{(3){no_sel}}});
endcase
end
end endgenerate
 
//
// AXI read address channel
//
initial assert(!o_axi_arvalid);
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_cyc))&&(!$past(o_wb_stall)))
begin
if (!$past(i_wb_stb))
assert(!o_axi_arvalid);
else
assert(o_axi_arvalid == !$past(i_wb_we));
end
//
generate
if (C_AXI_DATA_WIDTH == DW)
begin
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&($past(!i_wb_we))
&&(!$past(o_wb_stall)))
assert(o_axi_araddr == $past({ i_wb_addr[AW-1:0], axi_bottom_addr }));
 
end else if (C_AXI_DATA_WIDTH / DW == 2)
begin
 
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&($past(!i_wb_we))
&&(!$past(o_wb_stall)))
assert(o_axi_araddr == $past({ i_wb_addr[AW-1:1], axi_bottom_addr }));
 
end else if (C_AXI_DATA_WIDTH / DW == 4)
begin
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wb_stb))&&($past(!i_wb_we))
&&(!$past(o_wb_stall)))
assert(o_axi_araddr == $past({ i_wb_addr[AW-1:2], axi_bottom_addr }));
 
end endgenerate
 
//
// AXI write response channel
//
 
 
//
// AXI read data channel signals
//
always @(posedge i_clk)
`ASSUME(f_axi_rd_outstanding <= f_wb_outstanding);
//
always @(posedge i_clk)
`ASSUME(f_axi_rd_outstanding + f_axi_wr_outstanding <= f_wb_outstanding);
always @(posedge i_clk)
`ASSUME(f_axi_rd_outstanding + f_axi_awr_outstanding <= f_wb_outstanding);
//
always @(posedge i_clk)
`ASSUME(f_axi_rd_outstanding + f_axi_wr_outstanding +2 > f_wb_outstanding);
always @(posedge i_clk)
`ASSUME(f_axi_rd_outstanding + f_axi_awr_outstanding +2 > f_wb_outstanding);
 
// Make sure we only create one request at a time
always @(posedge i_clk)
assert((!o_axi_arvalid)||(!o_axi_wvalid));
always @(posedge i_clk)
assert((!o_axi_arvalid)||(!o_axi_awvalid));
 
// Now, let's look into that FIFO. Without it, we know nothing about the ID's
 
// Error handling
always @(posedge i_clk)
if (!i_wb_cyc)
f_err_state <= 0;
else if (o_wb_err)
f_err_state <= 1;
always @(posedge i_clk)
if ((f_past_valid)&&($past(f_err_state))&&(
(!$past(o_wb_stall))||(!$past(i_wb_stb))))
`ASSUME(!i_wb_stb);
 
// Head and tail pointers
 
// The head should only increment when something goes through
always @(posedge i_clk)
if ((f_past_valid)&&((!$past(i_wb_stb))||($past(o_wb_stall))))
assert($stable(fifo_head));
 
// Can't overrun the FIFO
wire [(LGFIFOLN-1):0] f_fifo_tail_minus_one;
assign f_fifo_tail_minus_one = fifo_tail - 1'b1;
always @(posedge i_clk)
if ((f_past_valid)&&($past(fifo_head == f_fifo_tail_minus_one)))
assert(fifo_head != fifo_tail);
 
reg f_pre_ack;
 
wire [(LGFIFOLN-1):0] f_fifo_used;
assign f_fifo_used = fifo_head - fifo_tail;
 
initial assert(fifo_tail == 0);
initial assert(reorder_fifo_valid == 0);
initial assert(reorder_fifo_err == 0);
initial f_pre_ack = 1'b0;
always @(posedge i_clk)
begin
f_pre_ack <= (!wb_abort)&&((axi_rd_ack)||(axi_wr_ack));
if (STRICT_ORDER)
begin
`ASSUME((!axi_rd_ack)||(!axi_wr_ack));
 
if (f_past_valid)
assert((!$past(i_wb_cyc))
||(o_wb_ack == $past(f_pre_ack)));
end
end
 
//
// Verify that there are no outstanding requests outside of the FIFO
// window. This should never happen, but the formal tools need to know
// that.
//
always @(*)
begin
assert((f_axi_rd_id_outstanding&f_axi_wr_id_outstanding)==0);
assert((f_axi_rd_id_outstanding&f_axi_awr_id_outstanding)==0);
 
if (fifo_head == fifo_tail)
begin
assert(f_axi_rd_id_outstanding == 0);
assert(f_axi_wr_id_outstanding == 0);
assert(f_axi_awr_id_outstanding == 0);
end
 
for(k=0; k<(1<<LGFIFOLN); k=k+1)
begin
if ( ((fifo_tail < fifo_head)&&(k < fifo_tail))
||((fifo_tail < fifo_head)&&(k >= fifo_head))
||((fifo_head < fifo_tail)&&(k >= fifo_head)&&(k < fifo_tail))
//||((fifo_head < fifo_tail)&&(k >=fifo_tail))
)
begin
assert(f_axi_rd_id_outstanding[k]==0);
assert(f_axi_wr_id_outstanding[k]==0);
assert(f_axi_awr_id_outstanding[k]==0);
end
end
end
 
generate
if (STRICT_ORDER)
begin : STRICTREQ
 
reg [C_AXI_ID_WIDTH-1:0] f_last_axi_id;
wire [C_AXI_ID_WIDTH-1:0] f_next_axi_id,
f_expected_last_id;
assign f_next_axi_id = f_last_axi_id + 1'b1;
assign f_expected_last_id = fifo_head - 1'b1 - f_fifo_used;
 
initial f_last_axi_id = -1;
always @(posedge i_clk)
if (i_reset)
f_last_axi_id = -1;
else if ((axi_rd_ack)||(axi_wr_ack))
f_last_axi_id <= f_next_axi_id;
else if (f_fifo_used == 0)
assert(f_last_axi_id == fifo_head-1'b1);
 
always @(posedge i_clk)
if (axi_rd_ack)
`ASSUME(i_axi_rid == f_next_axi_id);
else if (axi_wr_ack)
`ASSUME(i_axi_bid == f_next_axi_id);
end endgenerate
 
reg f_pending, f_returning;
initial f_pending = 1'b0;
always @(*)
f_pending <= (o_axi_arvalid)||(o_axi_awvalid);
always @(*)
f_returning <= (axi_rd_ack)||(axi_wr_ack);
 
reg [(LGFIFOLN):0] f_pre_count;
 
always @(*)
f_pre_count <= f_axi_awr_outstanding
+ f_axi_rd_outstanding
+ reorder_count
+ { {(LGFIFOLN){1'b0}}, (o_wb_ack) }
+ { {(LGFIFOLN){1'b0}}, (f_pending) };
always @(posedge i_clk)
assert((wb_abort)||(o_wb_err)||(f_pre_count == f_wb_outstanding));
 
always @(posedge i_clk)
assert((wb_abort)||(o_wb_err)||(f_fifo_used == f_wb_outstanding
// + {{(LGFIFOLN){1'b0}},f_past_valid)(i_wb_stb)&&(!o_wb_ack)}
- {{(LGFIFOLN){1'b0}},(o_wb_ack)}));
 
always @(posedge i_clk)
if (o_axi_wvalid)
assert(f_fifo_used != 0);
always @(posedge i_clk)
if (o_axi_arvalid)
assert(f_fifo_used != 0);
always @(posedge i_clk)
if (o_axi_awvalid)
assert(f_fifo_used != 0);
 
`endif
endmodule
 

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