URL
https://opencores.org/ocsvn/wb2axip/wb2axip/trunk
Subversion Repositories wb2axip
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- This comparison shows the changes necessary to convert path
/wb2axip
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/rtl/wbm2axisp.v
64,50 → 64,51
input i_reset,// Wishbone reset signal |
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// AXI write address channel signals |
input i_axi_wready, // Slave is ready to accept |
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wid, // Write ID |
output reg [AW-1:0] o_axi_waddr, // Write address |
output wire [7:0] o_axi_wlen, // Write Burst Length |
output wire [2:0] o_axi_wsize, // Write Burst size |
output wire [1:0] o_axi_wburst, // Write Burst type |
output wire [1:0] o_axi_wlock, // Write lock type |
output wire [3:0] o_axi_wcache, // Write Cache type |
output wire [2:0] o_axi_wprot, // Write Protection type |
output reg o_axi_wvalid, // Write address valid |
input i_axi_awready, // Slave is ready to accept |
output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID |
output reg [AW-1:0] o_axi_awaddr, // Write address |
output wire [7:0] o_axi_awlen, // Write Burst Length |
output wire [2:0] o_axi_awsize, // Write Burst size |
output wire [1:0] o_axi_awburst, // Write Burst type |
output wire [1:0] o_axi_awlock, // Write lock type |
output wire [3:0] o_axi_awcache, // Write Cache type |
output wire [2:0] o_axi_awprot, // Write Protection type |
output wire [3:0] o_axi_awqos, // Write Quality of Svc |
output reg o_axi_awvalid, // Write address valid |
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// AXI write data channel signals |
input i_axi_wd_wready, // Write data ready |
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag |
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data |
output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes |
output wire o_axi_wd_last, // Last write transaction |
output reg o_axi_wd_valid, // Write valid |
input i_axi_wready, // Write data ready |
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data |
output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes |
output wire o_axi_wlast, // Last write transaction |
output reg o_axi_wvalid, // Write valid |
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// AXI write response channel signals |
input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID |
input [1:0] i_axi_wd_bresp, // Write response |
input i_axi_wd_bvalid, // Write reponse valid |
output wire o_axi_wd_bready, // Response ready |
input [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID |
input [1:0] i_axi_bresp, // Write response |
input i_axi_bvalid, // Write reponse valid |
output wire o_axi_bready, // Response ready |
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// AXI read address channel signals |
input i_axi_rready, // Read address ready |
output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Read ID |
output wire [AW-1:0] o_axi_raddr, // Read address |
output wire [7:0] o_axi_rlen, // Read Burst Length |
output wire [2:0] o_axi_rsize, // Read Burst size |
output wire [1:0] o_axi_rburst, // Read Burst type |
output wire [1:0] o_axi_rlock, // Read lock type |
output wire [3:0] o_axi_rcache, // Read Cache type |
output wire [2:0] o_axi_rprot, // Read Protection type |
output reg o_axi_rvalid, // Read address valid |
input i_axi_arready, // Read address ready |
output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID |
output wire [AW-1:0] o_axi_araddr, // Read address |
output wire [7:0] o_axi_arlen, // Read Burst Length |
output wire [2:0] o_axi_arsize, // Read Burst size |
output wire [1:0] o_axi_arburst, // Read Burst type |
output wire [1:0] o_axi_arlock, // Read lock type |
output wire [3:0] o_axi_arcache, // Read Cache type |
output wire [2:0] o_axi_arprot, // Read Protection type |
output wire [3:0] o_axi_arqos, // Read Protection type |
output reg o_axi_arvalid, // Read address valid |
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// AXI read data channel signals |
input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID |
input [1:0] i_axi_rd_rresp, // Read response |
input i_axi_rd_rvalid, // Read reponse valid |
input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data |
input i_axi_rd_last, // Read last |
output wire o_axi_rd_rready, // Read Response ready |
input [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID |
input [1:0] i_axi_rresp, // Read response |
input i_axi_rvalid, // Read reponse valid |
input [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data |
input i_axi_rlast, // Read last |
output wire o_axi_rready, // Read Response ready |
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// We'll share the clock and the reset |
input i_wb_cyc, |
162,28 → 163,28
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// Things we're not changing ... |
assign o_axi_wlen = 8'h0; // Burst length is one |
assign o_axi_wsize = 3'b101; // maximum bytes per burst is 32 |
assign o_axi_wburst = 2'b01; // Incrementing address (ignored) |
assign o_axi_rburst = 2'b01; // Incrementing address (ignored) |
assign o_axi_wlock = 2'b00; // Normal signaling |
assign o_axi_rlock = 2'b00; // Normal signaling |
assign o_axi_wcache = 4'h2; // Normal: no cache, no buffer |
assign o_axi_rcache = 4'h2; // Normal: no cache, no buffer |
assign o_axi_wprot = 3'h010; // Unpriviledged, unsecure, data access |
assign o_axi_rprot = 3'h010; // Unpriviledged, unsecure, data access |
assign o_axi_awlen = 8'h0; // Burst length is one |
assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32 |
assign o_axi_awburst = 2'b01; // Incrementing address (ignored) |
assign o_axi_arburst = 2'b01; // Incrementing address (ignored) |
assign o_axi_awlock = 2'b00; // Normal signaling |
assign o_axi_arlock = 2'b00; // Normal signaling |
assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer |
assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer |
assign o_axi_awprot = 3'h010; // Unpriviledged, unsecure, data access |
assign o_axi_arprot = 3'h010; // Unpriviledged, unsecure, data access |
assign o_axi_awqos = 4'h0; // Lowest quality of service (unused) |
assign o_axi_arqos = 4'h0; // Lowest quality of service (unused) |
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// Command logic |
assign o_wb_stall = (i_wb_we)&&(~i_axi_wready) |
||(~i_wb_we)&&(!i_axi_rready); |
// Write address logic |
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always @(posedge i_clk) |
o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we) |
||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready); |
o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we) |
||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready); |
always @(posedge i_clk) |
if (!o_wb_stall) |
o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits |
o_axi_awaddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits |
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reg [5:0] transaction_id; |
always @(posedge i_clk) |
191,53 → 192,51
transaction_id <= 6'h00; |
else if ((i_wb_stb)&&(~o_wb_stall)) |
transaction_id <= transaction_id + 6'h01; |
assign o_axi_wid = transaction_id; |
assign o_axi_awid = transaction_id; |
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// Read address logic |
assign o_axi_rid = transaction_id; |
assign o_axi_raddr = o_axi_waddr; |
assign o_axi_rlen = o_axi_wlen; |
assign o_axi_rsize = 3'b101; // maximum bytes per burst is 32 |
assign o_axi_arid = transaction_id; |
assign o_axi_araddr = o_axi_awaddr; |
assign o_axi_arlen = o_axi_awlen; |
assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32 |
always @(posedge i_clk) |
o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we) |
||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready); |
o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we) |
||(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready); |
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// Write data logic |
assign o_axi_wd_wid = transaction_id; |
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generate |
if (DW == 32) |
begin |
always @(posedge i_clk) |
if (!o_wb_stall) |
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data }; |
o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data }; |
always @(posedge i_clk) |
if (!o_wb_stall) |
case(i_wb_addr[1:0]) |
2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel }; |
2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 }; |
2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 }; |
2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 }; |
2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0, i_wb_sel }; |
2'b01:o_axi_wstrb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 }; |
2'b10:o_axi_wstrb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 }; |
2'b11:o_axi_wstrb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 }; |
endcase |
end else if (DW == 128) |
begin |
always @(posedge i_clk) |
if (!o_wb_stall) |
o_axi_wd_data <= i_wb_data; |
o_axi_wdata <= i_wb_data; |
always @(posedge i_clk) |
if (!o_wb_stall) |
o_axi_wd_strb <= i_wb_sel; |
o_axi_wstrb <= i_wb_sel; |
end endgenerate |
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assign o_axi_wd_last = 1'b1; |
assign o_axi_wlast = 1'b1; |
always @(posedge i_clk) |
o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)) |
||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready); |
o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)) |
||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready); |
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// Read data channel / response logic |
assign o_axi_rd_rready = 1'b1; |
assign o_axi_wd_bready = 1'b1; |
assign o_axi_rready = 1'b1; |
assign o_axi_bready = 1'b1; |
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wire w_fifo_full; |
generate |
263,8 → 262,8
if ((i_wb_stb)&&(!o_wb_stall)) |
low_addr <= i_wb_addr[1:0]; |
always @(posedge i_clk) |
if ((o_axi_rvalid)&&(i_axi_rready)) |
reorder_fifo_addr[o_axi_rid] <= low_addr; |
if ((o_axi_arvalid)&&(i_axi_arready)) |
reorder_fifo_addr[o_axi_arid] <= low_addr; |
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always @(posedge i_clk) |
case(reorder_fifo_addr[1:0]) |
293,17 → 292,17
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always @(posedge i_clk) |
begin |
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready)) |
reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data; |
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready)) |
if ((i_axi_rvalid)&&(o_axi_rready)) |
reorder_fifo_data[i_axi_rid]<= i_axi_rdata; |
if ((i_axi_rvalid)&&(o_axi_rready)) |
begin |
reorder_fifo_valid[i_axi_rd_bid] <= 1'b1; |
reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1]; |
reorder_fifo_valid[i_axi_rid] <= 1'b1; |
reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1]; |
end |
if ((i_axi_wd_bvalid)&&(o_axi_wd_bready)) |
if ((i_axi_bvalid)&&(o_axi_bready)) |
begin |
reorder_fifo_valid[i_axi_wd_bid] <= 1'b1; |
reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1]; |
reorder_fifo_valid[i_axi_bid] <= 1'b1; |
reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1]; |
end |
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if (reorder_fifo_valid[fifo_tail]) |
347,14 → 346,14
end else begin |
assign w_fifo_full = 1'b0; |
always @(posedge i_clk) |
o_wb_data <= i_axi_rd_data; |
o_wb_data <= i_axi_rdata; |
always @(posedge i_clk) |
o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready)) |
||((i_axi_wd_bvalid)&&(o_axi_wd_bready)); |
o_wb_ack <= ((i_axi_rvalid)&&(o_axi_rready)) |
||((i_axi_bvalid)&&(o_axi_bready)); |
always @(posedge i_clk) |
o_wb_err <= (!i_wb_cyc)&&((o_wb_err) |
||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1])) |
||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1]))); |
||((i_axi_rvalid)&&(i_axi_rresp[1])) |
||((i_axi_bvalid)&&(i_axi_bresp[1]))); |
end endgenerate |
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363,7 → 362,8
// outgoing is valid and nothing is ready. |
assign o_wb_stall = (i_wb_cyc)&&( |
(w_fifo_full) |
||((o_axi_wvalid)&&(!i_axi_wready)) |
||((o_axi_wd_valid)&&(!i_axi_wd_wready)) |
||((o_axi_rvalid)&&(!i_axi_rready))); |
||((o_axi_awvalid)&&(!i_axi_awready)) |
||((o_axi_wvalid )&&(!i_axi_wready )) |
||((o_axi_arvalid)&&(!i_axi_arready))); |
endmodule |
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