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URL https://opencores.org/ocsvn/wb2hpi/wb2hpi/trunk

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    /wb2hpi/trunk/apps/pci2dsp
    from Rev 11 to Rev 12
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  •

Rev 11 → Rev 12

/pci/README.TXT
0,0 → 1,63
Put Opencores PCI core here:
-------------------------------------------------
pci_user_constants.v
pci_target_unit.v
pci_target32_trdy_crit.v
pci_target32_stop_crit.v
pci_target32_sm.v
pci_target32_interface.v
pci_target32_devs_crit.v
pci_target32_clk_en.v
pci_rst_int.v
pci_parity_check.v
pci_master32_sm_if.v
pci_master32_sm.v
pci_io_mux_ad_load_crit.v
pci_io_mux_ad_en_crit.v
pci_io_mux.v
pci_in_reg.v
pci_bridge32.v
pci_serr_en_crit.v
pci_serr_crit.v
pci_perr_en_crit.v
pci_perr_crit.v
pci_par_crit.v
pci_wbw_wbr_fifos.v
pci_wb_master.v
pci_pciw_pcir_fifos.v
pci_wbw_fifo_control.v
pci_wbr_fifo_control.v
pci_wb_tpram.v
pci_wb_slave_unit.v
pci_wb_slave.v
pci_wb_decoder.v
pci_wb_addr_mux.v
pci_sync_module.v
pci_pciw_fifo_control.v
pci_pcir_fifo_control.v
pci_pci_tpram.v
pci_pci_decoder.v
pci_out_reg.v
pci_mas_ch_state_crit.v
pci_mas_ad_load_crit.v
pci_mas_ad_en_crit.v
pci_irdy_out_crit.v
pci_frame_load_crit.v
pci_frame_en_crit.v
pci_frame_crit.v
pci_delayed_write_reg.v
pci_delayed_sync.v
pci_cur_out_reg.v
pci_conf_space.v
pci_conf_cyc_addr_dec.v
pci_cbe_en_crit.v
pci_async_reset_flop.v
bus_commands.v
pci_ram_16x40d.v
timescale.v
pci_constants.v
 
Put library files here:
-------------------------------------------------
virtex.v
 
/pci/pci_user_constants.v
0,0 → 1,318
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_user_constants.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - Tadej Markovic (tadej@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/02/20 09:49:48 gvozden
// izmenjeno koprianje strane, i dodato zatvaranje svih stranica odjednom
//
// Revision 1.13 2004/01/24 11:54:18 mihad
// Update! SPOCI Implemented!
//
// Revision 1.12 2003/12/28 09:54:48 fr2201
// def_wb_imagex_addr_map defined correctly
//
// Revision 1.11 2003/12/28 09:20:00 fr2201
// Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO)
//
// Revision 1.10 2003/12/19 11:11:30 mihad
// Compact PCI Hot Swap support added.
// New testcases added.
// Specification updated.
// Test application changed to support WB B3 cycles.
//
// Revision 1.9 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
//
// Revision 1.8 2003/03/14 15:31:57 mihad
// Entered the option to disable no response counter in wb master.
//
// Revision 1.7 2003/01/27 17:05:50 mihad
// Updated.
//
// Revision 1.6 2003/01/27 16:51:19 mihad
// Old files with wrong names removed.
//
// Revision 1.5 2003/01/21 16:06:56 mihad
// Bug fixes, testcases added.
//
// Revision 1.4 2002/09/30 17:22:45 mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.3 2002/08/13 11:03:53 mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.2 2002/03/05 11:53:47 mihad
// Added some testcases, removed un-needed fifo signals
//
// Revision 1.1 2002/02/01 14:43:31 mihad
// *** empty log message ***
//
//
 
// Fifo implementation defines:
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.
 
`define WBW_ADDR_LENGTH 3
`define WBR_ADDR_LENGTH 6
`define PCIW_ADDR_LENGTH 4
`define PCIR_ADDR_LENGTH 4
 
`define FPGA
`define XILINX
 
//`define WB_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE
 
`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
//`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
// `define WB_ARTISAN_SDP
// `define PCI_ARTISAN_SDP
// `define PCI_VS_STP
// `define WB_VS_STP
`endif
 
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
`define ACTIVE_LOW_OE
//`define ACTIVE_HIGH_OE
 
// HOST/GUEST implementation selection - see design document and specification for description of each implementation
// only one can be defined at same time
//`define HOST
`define GUEST
 
// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
// - ENABLED Read-Only access from WISHBONE for GUEST bridges
// - ENABLED Read-Only access from PCI for HOST bridges
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
`define NO_CNF_IMAGE
 
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define PCI_NUM_OF_DEC_ADDR_LINES 12
 
// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
// access.
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
// is no access to Configuration space possible from PCI bus.
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
// or GUEST implementation.
`ifdef HOST
`ifdef NO_CNF_IMAGE
//`define PCI_IMAGE0
`endif
`endif
 
//`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5
 
// initial value for PCI image address masks. Address masks can be defined in enabled state,
// to allow device independent software to detect size of image and map base addresses to
// memory space. If initial mask for an image is defined as 0, then device independent software
// won't detect base address implemented and device dependent software will have to configure
// address masks as well as base addresses!
`define PCI_AM0 20'hffff_f
`define PCI_AM1 20'hffff_f
`define PCI_AM2 20'hffff_f
`define PCI_AM3 20'hffff_f
`define PCI_AM4 20'hffff_f
`define PCI_AM5 20'hffff_f
 
// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
// Device independent software sets the base addresses acording to MEMORY or IO maping!
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
`define PCI_BA1_MEM_IO 1'b0
`define PCI_BA2_MEM_IO 1'b0
`define PCI_BA3_MEM_IO 1'b0
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b0
 
// initial value for PCI translation addresses. The initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images
// are transleted to this adresses whithout access to pci_ta registers.
`define PCI_TA0 20'h0000_0
`define PCI_TA1 20'h0000_0
`define PCI_TA2 20'h0000_0
`define PCI_TA3 20'h0000_0
`define PCI_TA4 20'h0000_0
`define PCI_TA5 20'h0000_0
 
`define PCI_AT_EN0 1'b0
`define PCI_AT_EN1 1'b0
`define PCI_AT_EN2 1'b0
`define PCI_AT_EN3 1'b0
`define PCI_AT_EN4 1'b0
`define PCI_AT_EN5 1'b0
 
// number defined here specifies how many MS bits in WB address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 1
 
// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
//`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5
//Address bar register defines the base address for each image.
//To asccess bus without Software configuration.
`define WB_BA1 20'h0000_0
`define WB_BA2 20'h0000_0
`define WB_BA3 20'h0000_0
`define WB_BA4 20'h0000_0
`define WB_BA5 20'h0000_0
 
// initial value for WB image maping to MEMORY or IO spaces. If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space.
`define WB_BA1_MEM_IO 1'b0
`define WB_BA2_MEM_IO 1'b0
`define WB_BA3_MEM_IO 1'b0
`define WB_BA4_MEM_IO 1'b0
`define WB_BA5_MEM_IO 1'b0
 
// initial value for WB image address masks.
`define WB_AM1 20'h0000_0
`define WB_AM2 20'h0000_0
`define WB_AM3 20'h0000_0
`define WB_AM4 20'h0000_0
`define WB_AM5 20'h0000_0
 
// initial value for WB translation addresses. The initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images
// are transleted to this adresses whithout access to pci_ta registers.
`define WB_TA1 20'h0000_0
`define WB_TA2 20'h0000_0
`define WB_TA3 20'h0000_0
`define WB_TA4 20'h0000_0
`define WB_TA5 20'h0000_0
 
`define WB_AT_EN1 1'b0
`define WB_AT_EN2 1'b0
`define WB_AT_EN3 1'b0
`define WB_AT_EN4 1'b0
`define WB_AT_EN5 1'b0
 
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//When ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
//`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
`define WB_DECODE_FAST
//`define WB_DECODE_MEDIUM
//`define WB_DECODE_SLOW
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'h0000_0
 
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBS_OUTPUTS
 
/*-----------------------------------------------------------------------------------------------------------
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
capable device
-----------------------------------------------------------------------------------------------------------*/
`define PCI33
//`define PCI66
 
/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h2321
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
`define WB_RTY_CNT_MAX 8'hff
 
// define the macro below to disable internal retry generation in the wishbone master interface
// used when wb master accesses extremly slow devices.
//`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
 
//`define PCI_WB_REV_B3
`define PCI_WBS_B3_RTY_DISABLE
 
`ifdef GUEST
`define PCI_CPCI_HS_IMPLEMENT
`define PCI_SPOCI
`endif
/rtl/verilog/top.v
0,0 → 1,738
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "top.v" ////
//// ////
//// This file is part of the WB2HPI sample aplication ////
//// (modified top.v from CRT - PCI Bridge sample application) ////
//// ////
//// http://www.opencores.org/cores/wb2hpi/ ////
//// ////
//// Author(s): ////
//// - Gvozden Marinkovic (gvozden@opencores.org) ////
//// - Dusko Krsmanovic (dusko@opencores.org) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS History
//
// $Author: gvozden $
// $Date: 2004-02-20 10:45:02 $
// $Revision: 1.4 $
 
/*
module TOP
(
CLK,
AD,
CBE,
RST,
INTA,
REQ,
GNT,
FRAME,
IRDY,
IDSEL,
DEVSEL,
TRDY,
STOP,
PAR,
PERR,
SERR,
 
WB_CLK,
 
DSP_HAD,
DSP_HCNTL,
DSP_HBIL,
DSP_HCS,
DSP_HDS1,
DSP_HDS2,
DSP_HRW,
DSP_HRDY,
DSP_RST,
DSP_HAS,
DSP_HINT,
DSP_INT2,
 
LED,
 
OSC_IN,
OSC_AD
);
*/
module TOP
(
CLK,
RST,
INTA,
REQ,
GNT,
FRAME,
IRDY,
IDSEL,
DEVSEL,
TRDY,
STOP,
PAR,
PERR,
SERR,
AD0,
AD1,
AD2,
AD3,
AD4,
AD5,
AD6,
AD7,
AD8,
AD9,
AD10,
AD11,
AD12,
AD13,
AD14,
AD15,
AD16,
AD17,
AD18,
AD19,
AD20,
AD21,
AD22,
AD23,
AD24,
AD25,
AD26,
AD27,
AD28,
AD29,
AD30,
AD31,
CBE0,
CBE1,
CBE2,
CBE3,
DSP_HAD,
DSP_HCNTL,
DSP_HBIL,
DSP_HCS,
DSP_HDS1,
DSP_HDS2,
DSP_HRW,
DSP_HRDY,
DSP_RST,
DSP_HAS,
DSP_HINT,
DSP_INT2,
 
LED,
 
OSC_IN,
OSC_AD
);
 
 
inout [ 7:0] DSP_HAD;
output [ 1:0] DSP_HCNTL;
output DSP_HBIL;
output DSP_HCS;
output DSP_HDS1;
output DSP_HDS2;
output DSP_HRW;
input DSP_HRDY;
output DSP_RST;
output DSP_HAS;
input DSP_HINT;
output DSP_INT2;
 
output LED;
 
input OSC_IN;
output OSC_AD;
 
wire INT_REQ;
 
/*
inout [31:0] AD;
inout [ 3:0] CBE;
*/
 
input CLK ;
inout AD0,
AD1,
AD2,
AD3,
AD4,
AD5,
AD6,
AD7,
AD8,
AD9,
AD10,
AD11,
AD12,
AD13,
AD14,
AD15,
AD16,
AD17,
AD18,
AD19,
AD20,
AD21,
AD22,
AD23,
AD24,
AD25,
AD26,
AD27,
AD28,
AD29,
AD30,
AD31 ;
 
inout CBE0,
CBE1,
CBE2,
CBE3 ;
 
inout RST ;
inout INTA ;
output REQ ;
input GNT ;
inout FRAME ;
inout IRDY ;
input IDSEL ;
inout DEVSEL ;
inout TRDY ;
inout STOP ;
inout PAR ;
inout PERR ;
output SERR ;
 
// WISHBONE system signals
wire RST_I = 1'b0 ;
wire RST_O ;
wire INT_I = 1'b0 ;
wire INT_O ;
 
// WISHBONE slave interface
wire [31:0] ADR_I ;
wire [31:0] SDAT_I;
wire [31:0] SDAT_O;
wire [3:0] SEL_I ;
wire CYC_I ;
wire STB_I ;
wire WE_I ;
wire CAB_I ;
wire ACK_O ;
wire RTY_O ;
wire ERR_O ;
 
// WISHBONE master interface
wire [31:0] ADR_O ;
wire [31:0] MDAT_I;
wire [31:0] MDAT_O;
wire [3:0] SEL_O ;
wire CYC_O ;
wire STB_O ;
wire WE_O ;
wire CAB_O ;
wire ACK_I ;
wire RTY_I ;
wire ERR_I ;
 
wire [31:0] AD_out ;
wire [31:0] AD_en ;
 
/*
wire [31:0] AD_in = AD;
*/
 
wire [31:0] AD_in =
{
AD31,
AD30,
AD29,
AD28,
AD27,
AD26,
AD25,
AD24,
AD23,
AD22,
AD21,
AD20,
AD19,
AD18,
AD17,
AD16,
AD15,
AD14,
AD13,
AD12,
AD11,
AD10,
AD9,
AD8,
AD7,
AD6,
AD5,
AD4,
AD3,
AD2,
AD1,
AD0
} ;
 
/*
wire [ 3:0] CBE_in = CBE;
*/
 
wire [3:0] CBE_in =
{
CBE3,
CBE2,
CBE1,
CBE0
} ;
 
wire [3:0] CBE_out ;
wire [3:0] CBE_en ;
 
wire RST_in = RST ;
wire RST_out ;
wire RST_en ;
 
wire INTA_in = INTA ;
wire INTA_en ;
wire INTA_out ;
 
wire REQ_en ;
wire REQ_out ;
 
wire FRAME_in = FRAME ;
wire FRAME_out ;
wire FRAME_en ;
 
wire IRDY_in = IRDY ;
wire IRDY_out ;
wire IRDY_en ;
 
wire DEVSEL_in = DEVSEL ;
wire DEVSEL_out ;
wire DEVSEL_en ;
 
wire TRDY_in = TRDY ;
wire TRDY_out ;
wire TRDY_en ;
 
wire STOP_in = STOP ;
wire STOP_out ;
wire STOP_en ;
 
wire PAR_in = PAR ;
wire PAR_out ;
wire PAR_en ;
 
wire PERR_in = PERR ;
wire PERR_out ;
wire PERR_en ;
 
wire SERR_out ;
wire SERR_en ;
 
wire [ 7:0] DSP_HAD_in = DSP_HAD;
wire [ 7:0] DSP_HAD_out;
wire DSP_HAD_en;
 
assign OSC_AD = OSC_IN;
/*
pci_bridge32 bridge
(
// WISHBONE system signals
// .CLK_I (WB_CLK),
.CLK_I (CLK),
 
.RST_I (RST_I),
.RST_O (RST_O),
.INT_I (INT_REQ),
.INT_O (INT_O),
 
// WISHBONE slave interface
.ADR_I (ADR_I),
.SDAT_I (SDAT_I),
.SDAT_O (SDAT_O),
.SEL_I (SEL_I),
.CYC_I (CYC_I),
.STB_I (STB_I),
.WE_I (WE_I),
.CAB_I (CAB_I),
.ACK_O (ACK_O),
.RTY_O (RTY_O),
.ERR_O (ERR_O),
 
// WISHBONE master interface
.ADR_O (ADR_O),
.MDAT_I (MDAT_I),
.MDAT_O (MDAT_O),
.SEL_O (SEL_O),
.CYC_O (CYC_O),
.STB_O (STB_O),
.WE_O (WE_O),
.CAB_O (CAB_O),
.ACK_I (ACK_I),
.RTY_I (RTY_I),
.ERR_I (ERR_I),
 
// pci interface - system pins
.PCI_CLK_IN (CLK),
.PCI_RSTn_IN (RST_in),
.PCI_RSTn_OUT (RST_out),
.PCI_INTAn_IN (INTA_in),
.PCI_INTAn_OUT (INTA_out),
.PCI_RSTn_EN_OUT (RST_en),
.PCI_INTAn_EN_OUT (INTA_en),
 
// arbitration pins
.PCI_REQn_OUT (REQ_out),
.PCI_REQn_EN_OUT (REQ_en),
.PCI_GNTn_IN (GNT),
 
// protocol pins
.PCI_FRAMEn_IN (FRAME_in),
.PCI_FRAMEn_OUT (FRAME_out),
.PCI_FRAMEn_EN_OUT (FRAME_en),
.PCI_IRDYn_EN_OUT (IRDY_en),
.PCI_DEVSELn_EN_OUT (DEVSEL_en),
.PCI_TRDYn_EN_OUT (TRDY_en),
.PCI_STOPn_EN_OUT (STOP_en),
.PCI_AD_EN_OUT (AD_en),
.PCI_CBEn_EN_OUT (CBE_en) ,
.PCI_IRDYn_IN (IRDY_in),
.PCI_IRDYn_OUT (IRDY_out),
.PCI_IDSEL_IN (IDSEL),
.PCI_DEVSELn_IN (DEVSEL_in),
.PCI_DEVSELn_OUT (DEVSEL_out),
.PCI_TRDYn_IN (TRDY_in),
.PCI_TRDYn_OUT (TRDY_out),
.PCI_STOPn_IN (STOP_in),
.PCI_STOPn_OUT (STOP_out),
 
// data transfer pins
.PCI_AD_IN (AD_in),
.PCI_AD_OUT (AD_out),
.PCI_CBEn_IN (CBE_in),
.PCI_CBEn_OUT (CBE_out),
 
// parity generation and checking pins
.PCI_PAR_IN (PAR_in),
.PCI_PAR_OUT (PAR_out),
.PCI_PAR_EN_OUT (PAR_en),
.PCI_PERRn_IN (PERR_in),
.PCI_PERRn_OUT (PERR_out),
.PCI_PERRn_EN_OUT (PERR_en),
 
// system error pin
.PCI_SERRn_OUT (SERR_out),
.PCI_SERRn_EN_OUT (SERR_en)
);
*/
 
pci_bridge32 bridge
(
// WISHBONE system signals
.wb_clk_i(CLK),
.wb_rst_i(RST_I),
.wb_rst_o(RST_O),
.wb_int_i(INT_REQ),
.wb_int_o(INT_O),
 
// WISHBONE slave interface
.wbs_adr_i(ADR_I),
.wbs_dat_i(SDAT_I),
.wbs_dat_o(SDAT_O),
.wbs_sel_i(SEL_I),
.wbs_cyc_i(CYC_I),
.wbs_stb_i(STB_I),
.wbs_we_i (WE_I),
// .wbs_cab_i(CAB_I),
.wbs_ack_o(ACK_O),
.wbs_rty_o(RTY_O),
.wbs_err_o(ERR_O),
 
// WISHBONE master interface
.wbm_adr_o(ADR_O),
.wbm_dat_i(MDAT_I),
.wbm_dat_o(MDAT_O),
.wbm_sel_o(SEL_O),
.wbm_cyc_o(CYC_O),
.wbm_stb_o(STB_O),
.wbm_we_o (WE_O),
// .wbm_cab_o(CAB_O),
.wbm_ack_i(ACK_I),
.wbm_rty_i(RTY_I),
.wbm_err_i(ERR_I),
 
// pci interface - system pins
.pci_clk_i ( CLK ),
.pci_rst_i ( RST_in ),
.pci_rst_o ( RST_out ),
.pci_inta_i ( INTA_in ),
.pci_inta_o ( INTA_out),
.pci_rst_oe_o ( RST_en),
.pci_inta_oe_o( INTA_en ),
 
// arbitration pins
.pci_req_o ( REQ_out ),
.pci_req_oe_o( REQ_en ),
.pci_gnt_i ( GNT ),
 
// protocol pins
.pci_frame_i ( FRAME_in),
.pci_frame_o ( FRAME_out ),
.pci_frame_oe_o ( FRAME_en ),
.pci_irdy_oe_o ( IRDY_en ),
.pci_devsel_oe_o ( DEVSEL_en ),
.pci_trdy_oe_o ( TRDY_en ),
.pci_stop_oe_o ( STOP_en ),
.pci_ad_oe_o ( AD_en ),
.pci_cbe_oe_o ( CBE_en) ,
.pci_irdy_i ( IRDY_in ),
.pci_irdy_o ( IRDY_out ),
.pci_idsel_i ( IDSEL ),
.pci_devsel_i ( DEVSEL_in ),
.pci_devsel_o ( DEVSEL_out ),
.pci_trdy_i ( TRDY_in ),
.pci_trdy_o ( TRDY_out ),
.pci_stop_i ( STOP_in ),
.pci_stop_o ( STOP_out ),
 
// data transfer pins
.pci_ad_i (AD_in),
.pci_ad_o (AD_out),
.pci_cbe_i( CBE_in ),
.pci_cbe_o( CBE_out ),
 
// parity generation and checking pins
.pci_par_i ( PAR_in ),
.pci_par_o ( PAR_out ),
.pci_par_oe_o ( PAR_en ),
.pci_perr_i ( PERR_in ),
.pci_perr_o ( PERR_out ),
.pci_perr_oe_o( PERR_en ),
 
// system error pin
.pci_serr_o ( SERR_out ),
.pci_serr_oe_o( SERR_en )
);
 
/*
// PCI IO buffers instantiation
bufif0 AD_buf0 (AD[0], AD_out[0], AD_en[0]);
bufif0 AD_buf1 (AD[1], AD_out[1], AD_en[1]);
bufif0 AD_buf2 (AD[2], AD_out[2], AD_en[2]);
bufif0 AD_buf3 (AD[3], AD_out[3], AD_en[3]);
bufif0 AD_buf4 (AD[4], AD_out[4], AD_en[4]);
bufif0 AD_buf5 (AD[5], AD_out[5], AD_en[5]);
bufif0 AD_buf6 (AD[6], AD_out[6], AD_en[6]);
bufif0 AD_buf7 (AD[7], AD_out[7], AD_en[7]);
bufif0 AD_buf8 (AD[8], AD_out[8], AD_en[8]);
bufif0 AD_buf9 (AD[9], AD_out[9], AD_en[9]);
bufif0 AD_buf10 (AD[10], AD_out[10],AD_en[10]);
bufif0 AD_buf11 (AD[11], AD_out[11],AD_en[11]);
bufif0 AD_buf12 (AD[12], AD_out[12],AD_en[12]);
bufif0 AD_buf13 (AD[13], AD_out[13],AD_en[13]);
bufif0 AD_buf14 (AD[14], AD_out[14],AD_en[14]);
bufif0 AD_buf15 (AD[15], AD_out[15],AD_en[15]);
bufif0 AD_buf16 (AD[16], AD_out[16],AD_en[16]);
bufif0 AD_buf17 (AD[17], AD_out[17],AD_en[17]);
bufif0 AD_buf18 (AD[18], AD_out[18],AD_en[18]);
bufif0 AD_buf19 (AD[19], AD_out[19],AD_en[19]);
bufif0 AD_buf20 (AD[20], AD_out[20],AD_en[20]);
bufif0 AD_buf21 (AD[21], AD_out[21],AD_en[21]);
bufif0 AD_buf22 (AD[22], AD_out[22],AD_en[22]);
bufif0 AD_buf23 (AD[23], AD_out[23],AD_en[23]);
bufif0 AD_buf24 (AD[24], AD_out[24],AD_en[24]);
bufif0 AD_buf25 (AD[25], AD_out[25],AD_en[25]);
bufif0 AD_buf26 (AD[26], AD_out[26],AD_en[26]);
bufif0 AD_buf27 (AD[27], AD_out[27],AD_en[27]);
bufif0 AD_buf28 (AD[28], AD_out[28],AD_en[28]);
bufif0 AD_buf29 (AD[29], AD_out[29],AD_en[29]);
bufif0 AD_buf30 (AD[30], AD_out[30],AD_en[30]);
bufif0 AD_buf31 (AD[31], AD_out[31],AD_en[31]);
 
bufif0 CBE_buf0 (CBE[0], CBE_out[0], CBE_en[0]);
bufif0 CBE_buf1 (CBE[1], CBE_out[1], CBE_en[1]);
bufif0 CBE_buf2 (CBE[2], CBE_out[2], CBE_en[2]);
bufif0 CBE_buf3 (CBE[3], CBE_out[3], CBE_en[3]);
 
bufif0 FRAME_buf (FRAME, FRAME_out, FRAME_en);
bufif0 IRDY_buf (IRDY, IRDY_out, IRDY_en);
bufif0 DEVSEL_buf (DEVSEL, DEVSEL_out, DEVSEL_en);
bufif0 TRDY_buf (TRDY, TRDY_out, TRDY_en);
bufif0 STOP_buf (STOP, STOP_out, STOP_en);
 
bufif0 RST_buf (RST, RST_out, RST_en);
bufif0 INTA_buf (INTA, INTA_out, INTA_en);
bufif0 REQ_buf (REQ, REQ_out, REQ_en);
bufif0 PAR_buf (PAR, PAR_out, PAR_en);
bufif0 PERR_buf (PERR, PERR_out, PERR_en);
bufif0 SERR_buf (SERR, SERR_out, SERR_en);
*/
// PCI IO buffers instantiation
bufif0 AD_buf0 ( AD0, AD_out[0], AD_en[0]) ;
bufif0 AD_buf1 ( AD1, AD_out[1], AD_en[1]) ;
bufif0 AD_buf2 ( AD2, AD_out[2], AD_en[2]) ;
bufif0 AD_buf3 ( AD3, AD_out[3], AD_en[3]) ;
bufif0 AD_buf4 ( AD4, AD_out[4], AD_en[4]) ;
bufif0 AD_buf5 ( AD5, AD_out[5], AD_en[5]) ;
bufif0 AD_buf6 ( AD6, AD_out[6], AD_en[6]) ;
bufif0 AD_buf7 ( AD7, AD_out[7], AD_en[7]) ;
bufif0 AD_buf8 ( AD8, AD_out[8], AD_en[8]) ;
bufif0 AD_buf9 ( AD9, AD_out[9], AD_en[9]) ;
bufif0 AD_buf10 ( AD10, AD_out[10],AD_en[10] ) ;
bufif0 AD_buf11 ( AD11, AD_out[11],AD_en[11] ) ;
bufif0 AD_buf12 ( AD12, AD_out[12],AD_en[12] ) ;
bufif0 AD_buf13 ( AD13, AD_out[13],AD_en[13] ) ;
bufif0 AD_buf14 ( AD14, AD_out[14],AD_en[14] ) ;
bufif0 AD_buf15 ( AD15, AD_out[15],AD_en[15] ) ;
bufif0 AD_buf16 ( AD16, AD_out[16],AD_en[16] ) ;
bufif0 AD_buf17 ( AD17, AD_out[17],AD_en[17] ) ;
bufif0 AD_buf18 ( AD18, AD_out[18],AD_en[18] ) ;
bufif0 AD_buf19 ( AD19, AD_out[19],AD_en[19] ) ;
bufif0 AD_buf20 ( AD20, AD_out[20],AD_en[20] ) ;
bufif0 AD_buf21 ( AD21, AD_out[21],AD_en[21] ) ;
bufif0 AD_buf22 ( AD22, AD_out[22],AD_en[22] ) ;
bufif0 AD_buf23 ( AD23, AD_out[23],AD_en[23] ) ;
bufif0 AD_buf24 ( AD24, AD_out[24],AD_en[24] ) ;
bufif0 AD_buf25 ( AD25, AD_out[25],AD_en[25] ) ;
bufif0 AD_buf26 ( AD26, AD_out[26],AD_en[26] ) ;
bufif0 AD_buf27 ( AD27, AD_out[27],AD_en[27] ) ;
bufif0 AD_buf28 ( AD28, AD_out[28],AD_en[28] ) ;
bufif0 AD_buf29 ( AD29, AD_out[29],AD_en[29] ) ;
bufif0 AD_buf30 ( AD30, AD_out[30],AD_en[30] ) ;
bufif0 AD_buf31 ( AD31, AD_out[31],AD_en[31] ) ;
 
bufif0 CBE_buf0 ( CBE0, CBE_out[0], CBE_en[0] ) ;
bufif0 CBE_buf1 ( CBE1, CBE_out[1], CBE_en[1] ) ;
bufif0 CBE_buf2 ( CBE2, CBE_out[2], CBE_en[2] ) ;
bufif0 CBE_buf3 ( CBE3, CBE_out[3], CBE_en[3] ) ;
 
bufif0 FRAME_buf ( FRAME, FRAME_out, FRAME_en ) ;
bufif0 IRDY_buf ( IRDY, IRDY_out, IRDY_en ) ;
bufif0 DEVSEL_buf ( DEVSEL, DEVSEL_out, DEVSEL_en ) ;
bufif0 TRDY_buf ( TRDY, TRDY_out, TRDY_en ) ;
bufif0 STOP_buf ( STOP, STOP_out, STOP_en ) ;
 
bufif0 RST_buf ( RST, RST_out, RST_en ) ;
bufif0 INTA_buf ( INTA, INTA_out, INTA_en) ;
bufif0 REQ_buf ( REQ, REQ_out, REQ_en ) ;
bufif0 PAR_buf ( PAR, PAR_out, PAR_en ) ;
bufif0 PERR_buf ( PERR, PERR_out, PERR_en ) ;
bufif0 SERR_buf ( SERR, SERR_out, SERR_en ) ;
 
bufif0 DSP_HAD_buf0 (DSP_HAD[0], DSP_HAD_out[0], DSP_HAD_en);
bufif0 DSP_HAD_buf1 (DSP_HAD[1], DSP_HAD_out[1], DSP_HAD_en);
bufif0 DSP_HAD_buf2 (DSP_HAD[2], DSP_HAD_out[2], DSP_HAD_en);
bufif0 DSP_HAD_buf3 (DSP_HAD[3], DSP_HAD_out[3], DSP_HAD_en);
bufif0 DSP_HAD_buf4 (DSP_HAD[4], DSP_HAD_out[4], DSP_HAD_en);
bufif0 DSP_HAD_buf5 (DSP_HAD[5], DSP_HAD_out[5], DSP_HAD_en);
bufif0 DSP_HAD_buf6 (DSP_HAD[6], DSP_HAD_out[6], DSP_HAD_en);
bufif0 DSP_HAD_buf7 (DSP_HAD[7], DSP_HAD_out[7], DSP_HAD_en);
 
wb2hpi WB2HPI
(
// Clock and reset
.WB_CLK_I (CLK),
.WB_RST_I (RST_O),
 
// WISHBONE Master I/F
.WBM_CYC_O (CYC_I),
.WBM_STB_O (STB_I),
.WBM_SEL_O (SEL_I),
.WBM_WE_O (WE_I),
.WBM_ADR_O (ADR_I),
.WBM_DAT_O (SDAT_I),
.WBM_CAB_O (CAB_I),
.WBM_DAT_I (SDAT_O),
.WBM_ACK_I (ACK_O),
.WBM_ERR_I (ERR_O),
.WBM_RTY_I (RTY_O),
 
// WISHBONE Slave I/F
.WBS_CYC_I (CYC_O),
.WBS_STB_I (STB_O),
.WBS_SEL_I (SEL_O),
.WBS_WE_I (WE_O),
.WBS_ADR_I (ADR_O),
.WBS_DAT_I (MDAT_O),
.WBS_CAB_I (CAB_O),
.WBS_DAT_O (MDAT_I),
.WBS_ACK_O (ACK_I),
.WBS_ERR_O (ERR_I),
.WBS_RTY_O (RTY_I),
 
//To PCI
.INT_REQ (INT_REQ),
 
//54x DSP_HPI8 Signals
.DSP_HAD_I (DSP_HAD_in),
.DSP_HAD_O (DSP_HAD_out),
.DSP_HAD_ENn (DSP_HAD_en),
 
.DSP_HCNTL_PAD_O (DSP_HCNTL),
.DSP_HBIL_PAD_O (DSP_HBIL),
.DSP_HCS_PAD_O (DSP_HCS),
.DSP_HDS1_PAD_O (DSP_HDS1),
.DSP_HDS2_PAD_O (DSP_HDS2),
.DSP_HRW_PAD_O (DSP_HRW),
.DSP_HRDY_PAD_I (DSP_HRDY),
.DSP_RST_PAD_O (DSP_RST),
.DSP_HAS_PAD_O (DSP_HAS),
.DSP_HINT_PAD_I (DSP_HINT),
.DSP_INT2_PAD_O (DSP_INT2),
 
.LED (LED)
);
 
endmodule
/syn/synplify/src/regPCI.sdc
0,0 → 1,159
#************************** CVS history ***************************#
# $Author: gvozden $
# $Date: 2004-02-20 10:45:15 $
# $Revision: 1.4 $
# $Name: not supported by cvs2svn $
#************************** CVS history ***************************#
 
#
# Clocks
#
define_clock -name {CLK} -freq 35.000 -clockgroup clkkrp_pci
define_clock -name {WB_CLK} -freq 30.000 -clockgroup clkgrp_wb
 
#
# Inputs/Outputs
#
define_input_delay {AD0} 7.00 -ref CLK:r
define_output_delay {AD0} 11.00 -ref CLK:r
define_input_delay {AD1} 7.00 -ref CLK:r
define_output_delay {AD1} 11.00 -ref CLK:r
define_input_delay {AD10} 7.00 -ref CLK:r
define_output_delay {AD10} 11.00 -ref CLK:r
define_input_delay {AD11} 7.00 -ref CLK:r
define_output_delay {AD11} 11.00 -ref CLK:r
define_input_delay {AD12} 7.00 -ref CLK:r
define_output_delay {AD12} 11.00 -ref CLK:r
define_input_delay {AD13} 7.00 -ref CLK:r
define_output_delay {AD13} 11.00 -ref CLK:r
define_input_delay {AD14} 7.00 -ref CLK:r
define_output_delay {AD14} 11.00 -ref CLK:r
define_input_delay {AD15} 7.00 -ref CLK:r
define_output_delay {AD15} 11.00 -ref CLK:r
define_input_delay {AD16} 7.00 -ref CLK:r
define_output_delay {AD16} 11.00 -ref CLK:r
define_input_delay {AD17} 7.00 -ref CLK:r
define_output_delay {AD17} 11.00 -ref CLK:r
define_input_delay {AD18} 7.00 -ref CLK:r
define_output_delay {AD18} 11.00 -ref CLK:r
define_input_delay {AD19} 7.00 -ref CLK:r
define_output_delay {AD19} 11.00 -ref CLK:r
define_input_delay {AD2} 7.00 -ref CLK:r
define_output_delay {AD2} 11.00 -ref CLK:r
define_input_delay {AD20} 7.00 -ref CLK:r
define_output_delay {AD20} 11.00 -ref CLK:r
define_input_delay {AD21} 7.00 -ref CLK:r
define_output_delay {AD21} 11.00 -ref CLK:r
define_input_delay {AD22} 7.00 -ref CLK:r
define_output_delay {AD22} 11.00 -ref CLK:r
define_input_delay {AD23} 7.00 -ref CLK:r
define_output_delay {AD23} 11.00 -ref CLK:r
define_input_delay {AD24} 7.00 -ref CLK:r
define_output_delay {AD24} 11.00 -ref CLK:r
define_input_delay {AD25} 7.00 -ref CLK:r
define_output_delay {AD25} 11.00 -ref CLK:r
define_input_delay {AD26} 7.00 -ref CLK:r
define_output_delay {AD26} 11.00 -ref CLK:r
define_input_delay {AD27} 7.00 -ref CLK:r
define_output_delay {AD27} 11.00 -ref CLK:r
define_input_delay {AD28} 7.00 -ref CLK:r
define_output_delay {AD28} 11.00 -ref CLK:r
define_input_delay {AD29} 7.00 -ref CLK:r
define_output_delay {AD29} 11.00 -ref CLK:r
define_input_delay {AD3} 7.00 -ref CLK:r
define_output_delay {AD3} 11.00 -ref CLK:r
define_input_delay {AD30} 7.00 -ref CLK:r
define_output_delay {AD30} 11.00 -ref CLK:r
define_input_delay {AD31} 7.00 -ref CLK:r
define_output_delay {AD31} 11.00 -ref CLK:r
define_input_delay {AD4} 7.00 -ref CLK:r
define_output_delay {AD4} 11.00 -ref CLK:r
define_input_delay {AD5} 7.00 -ref CLK:r
define_output_delay {AD5} 11.00 -ref CLK:r
define_input_delay {AD6} 7.00 -ref CLK:r
define_output_delay {AD6} 11.00 -ref CLK:r
define_input_delay {AD7} 7.00 -ref CLK:r
define_output_delay {AD7} 11.00 -ref CLK:r
define_input_delay {AD8} 7.00 -ref CLK:r
define_output_delay {AD8} 11.00 -ref CLK:r
define_input_delay {AD9} 7.00 -ref CLK:r
define_output_delay {AD9} 11.00 -ref CLK:r
define_input_delay {CBE0} 7.00 -ref CLK:r
define_output_delay {CBE0} 11.00 -ref CLK:r
define_input_delay {CBE1} 7.00 -ref CLK:r
define_output_delay {CBE1} 11.00 -ref CLK:r
define_input_delay {CBE2} 7.00 -ref CLK:r
define_output_delay {CBE2} 11.00 -ref CLK:r
define_input_delay {CBE3} 7.00 -ref CLK:r
define_output_delay {CBE3} 11.00 -ref CLK:r
define_input_delay {FRAME} 7.00 -ref CLK:r
define_input_delay {IRDY} 7.00 -ref CLK:r
define_input_delay {IDSEL} 7.00 -ref CLK:r
define_input_delay {TRDY} 7.00 -route 3.00 -ref CLK:r
define_input_delay {STOP} 7.00 -route 1.00 -ref CLK:r
define_input_delay {PAR} 7.00 -ref CLK:r
define_input_delay {PERR} 7.00 -ref CLK:r
define_input_delay {GNT} 10.00 -route 2.00 -ref CLK:r
define_output_delay {FRAME} 11.00 -ref CLK:r
define_output_delay {IRDY} 11.00 -ref CLK:r
define_input_delay {DEVSEL} 11.00 -ref CLK:r
define_output_delay {TRDY} 11.00 -ref CLK:r
define_output_delay {STOP} 11.00 -ref CLK:r
define_output_delay {PAR} 11.00 -ref CLK:r
define_output_delay {PERR} 11.00 -ref CLK:r
define_output_delay {SERR} 11.00 -ref CLK:r
define_output_delay {REQ} 12.00 -ref CLK:r
 
#
# Registers
#
 
#
# Multicycle Path
#
 
#
# False Path
#
define_false_path -from {i:bridge.configuration.*} -to {i:WB2HPI.WB_slave.WBS_DAT_O[31:0]}
 
#
# Attributes
#
define_global_attribute syn_netlist_hierarchy {0}
define_global_attribute syn_forward_io_constraints {1}
define_global_attribute syn_useioff {1}
define_attribute -disable {v:work.pci_io_mux} syn_hier {hard}
define_attribute -disable {v:work.pci_parity_check} syn_hier {hard}
define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
define_attribute {v:work.pci_par_crit} syn_hier {hard}
define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_clk_en} syn_hier {hard}
define_attribute {v:work.pci_perr_crit} syn_hier {hard}
define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
define_attribute {v:work.pci_serr_crit} syn_hier {hard}
define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_cur_out_reg} syn_hier {hard}
define_attribute -disable {v:work.pci_out_reg} syn_hier {hard}
define_attribute {CLK} xc_padtype {BUFGP}
define_attribute {DSP_HINT} syn_noclockbuf {1}
define_attribute {OSC_IN} xc_padtype {BUFGP}
 
#
# Other Constraints
#
 
#
# Order of waveforms
#
/syn/synplify/src/regPCI.prj
0,0 → 1,112
#************************** CVS history ***************************#
# $Author: gvozden $
# $Date: 2004-02-20 10:45:15 $
# $Revision: 1.3 $
# $Name: not supported by cvs2svn $
#************************** CVS history ***************************#
 
#add_file options
add_file -verilog "../../../pci/virtex.v"
add_file -verilog "../../../rtl/verilog/top.v"
add_file -verilog "../../../pci/pci_async_reset_flop.v"
add_file -verilog "../../../pci/pci_bridge32.v"
add_file -verilog "../../../pci/pci_cbe_en_crit.v"
add_file -verilog "../../../pci/pci_conf_cyc_addr_dec.v"
add_file -verilog "../../../pci/pci_conf_space.v"
add_file -verilog "../../../pci/pci_constants.v"
add_file -verilog "../../../pci/pci_cur_out_reg.v"
add_file -verilog "../../../pci/pci_delayed_sync.v"
add_file -verilog "../../../pci/pci_delayed_write_reg.v"
add_file -verilog "../../../pci/pci_frame_crit.v"
add_file -verilog "../../../pci/pci_frame_en_crit.v"
add_file -verilog "../../../pci/pci_frame_load_crit.v"
add_file -verilog "../../../pci/pci_in_reg.v"
add_file -verilog "../../../pci/pci_io_mux.v"
add_file -verilog "../../../pci/pci_io_mux_ad_en_crit.v"
add_file -verilog "../../../pci/pci_io_mux_ad_load_crit.v"
add_file -verilog "../../../pci/pci_irdy_out_crit.v"
add_file -verilog "../../../pci/pci_mas_ad_en_crit.v"
add_file -verilog "../../../pci/pci_mas_ad_load_crit.v"
add_file -verilog "../../../pci/pci_mas_ch_state_crit.v"
add_file -verilog "../../../pci/pci_master32_sm.v"
add_file -verilog "../../../pci/pci_master32_sm_if.v"
add_file -verilog "../../../pci/pci_out_reg.v"
add_file -verilog "../../../pci/pci_par_crit.v"
add_file -verilog "../../../pci/pci_parity_check.v"
add_file -verilog "../../../pci/pci_pci_decoder.v"
add_file -verilog "../../../pci/pci_pci_tpram.v"
add_file -verilog "../../../pci/pci_pcir_fifo_control.v"
add_file -verilog "../../../pci/pci_pciw_fifo_control.v"
add_file -verilog "../../../pci/pci_pciw_pcir_fifos.v"
add_file -verilog "../../../pci/pci_perr_crit.v"
add_file -verilog "../../../pci/pci_perr_en_crit.v"
add_file -verilog "../../../pci/pci_ram_16x40d.v"
add_file -verilog "../../../pci/pci_rst_int.v"
add_file -verilog "../../../pci/pci_serr_crit.v"
add_file -verilog "../../../pci/pci_serr_en_crit.v"
add_file -verilog "../../../pci/pci_sync_module.v"
add_file -verilog "../../../pci/pci_target32_clk_en.v"
add_file -verilog "../../../pci/pci_target32_devs_crit.v"
add_file -verilog "../../../pci/pci_target32_interface.v"
add_file -verilog "../../../pci/pci_target32_sm.v"
add_file -verilog "../../../pci/pci_target32_stop_crit.v"
add_file -verilog "../../../pci/pci_target32_trdy_crit.v"
add_file -verilog "../../../pci/pci_target_unit.v"
add_file -verilog "../../../pci/pci_wb_addr_mux.v"
add_file -verilog "../../../pci/pci_wb_decoder.v"
add_file -verilog "../../../pci/pci_wb_master.v"
add_file -verilog "../../../pci/pci_wb_slave.v"
add_file -verilog "../../../pci/pci_wb_slave_unit.v"
add_file -verilog "../../../pci/pci_wb_tpram.v"
add_file -verilog "../../../pci/pci_wbr_fifo_control.v"
add_file -verilog "../../../pci/pci_wbw_fifo_control.v"
add_file -verilog "../../../pci/pci_wbw_wbr_fifos.v"
add_file -verilog "../../../pci/pci_spoci_ctrl.v"
add_file -verilog "../../../pci/pci_synchronizer_flop.v"
add_file -verilog "../../../pci/pci_wbs_wbb3_2_wbb2.v"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBmaster.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBslave.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_control.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_interface.vhd"
add_file -constraint "regPCI.sdc"
 
#reporting options
 
 
#implementation: "syn"
impl -add syn
 
#device options
set_option -technology SPARTAN2
set_option -part XC2S200
set_option -package PQ208
set_option -speed_grade -5
 
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "TOP"
 
#map options
set_option -frequency 30.000
set_option -fanout_limit 32
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 1
set_option -modular 0
 
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_format "edif"
project -log_file "../log/pci2dsp.log"
project -result_file "../out/pci2dsp.edn"
impl -active "syn"
/syn/xilinxISE/ucf/pci2dsp.ucf
0,0 → 1,218
#************************** CVS history ***************************#
# $Author: gvozden $
# $Date: 2003-02-28 14:10:54 $
# $Revision: 1.2 $
# $Name: not supported by cvs2svn $
#************************** CVS history ***************************#
 
CONFIG PART = XC2S200-PQ208-5;
 
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 30 ns HIGH 50 %;
 
INST "AD0.PAD" TNM = "PCI_AD";
INST "AD1.PAD" TNM = "PCI_AD";
INST "AD2.PAD" TNM = "PCI_AD";
INST "AD3.PAD" TNM = "PCI_AD";
INST "AD4.PAD" TNM = "PCI_AD";
INST "AD5.PAD" TNM = "PCI_AD";
INST "AD6.PAD" TNM = "PCI_AD";
INST "AD7.PAD" TNM = "PCI_AD";
INST "AD8.PAD" TNM = "PCI_AD";
INST "AD9.PAD" TNM = "PCI_AD";
INST "AD10.PAD" TNM = "PCI_AD";
INST "AD11.PAD" TNM = "PCI_AD";
INST "AD12.PAD" TNM = "PCI_AD";
INST "AD13.PAD" TNM = "PCI_AD";
INST "AD14.PAD" TNM = "PCI_AD";
INST "AD15.PAD" TNM = "PCI_AD";
INST "AD16.PAD" TNM = "PCI_AD";
INST "AD17.PAD" TNM = "PCI_AD";
INST "AD18.PAD" TNM = "PCI_AD";
INST "AD19.PAD" TNM = "PCI_AD";
INST "AD20.PAD" TNM = "PCI_AD";
INST "AD21.PAD" TNM = "PCI_AD";
INST "AD22.PAD" TNM = "PCI_AD";
INST "AD23.PAD" TNM = "PCI_AD";
INST "AD24.PAD" TNM = "PCI_AD";
INST "AD25.PAD" TNM = "PCI_AD";
INST "AD26.PAD" TNM = "PCI_AD";
INST "AD27.PAD" TNM = "PCI_AD";
INST "AD28.PAD" TNM = "PCI_AD";
INST "AD29.PAD" TNM = "PCI_AD";
INST "AD30.PAD" TNM = "PCI_AD";
INST "AD31.PAD" TNM = "PCI_AD";
 
TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK";
TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "AD0" IOSTANDARD = PCI33_5;
NET "AD1" IOSTANDARD = PCI33_5;
NET "AD2" IOSTANDARD = PCI33_5;
NET "AD3" IOSTANDARD = PCI33_5;
NET "AD4" IOSTANDARD = PCI33_5;
NET "AD5" IOSTANDARD = PCI33_5;
NET "AD6" IOSTANDARD = PCI33_5;
NET "AD7" IOSTANDARD = PCI33_5;
NET "AD8" IOSTANDARD = PCI33_5;
NET "AD9" IOSTANDARD = PCI33_5;
NET "AD10" IOSTANDARD = PCI33_5;
NET "AD11" IOSTANDARD = PCI33_5;
NET "AD12" IOSTANDARD = PCI33_5;
NET "AD13" IOSTANDARD = PCI33_5;
NET "AD14" IOSTANDARD = PCI33_5;
NET "AD15" IOSTANDARD = PCI33_5;
NET "AD16" IOSTANDARD = PCI33_5;
NET "AD17" IOSTANDARD = PCI33_5;
NET "AD18" IOSTANDARD = PCI33_5;
NET "AD19" IOSTANDARD = PCI33_5;
NET "AD20" IOSTANDARD = PCI33_5;
NET "AD21" IOSTANDARD = PCI33_5;
NET "AD22" IOSTANDARD = PCI33_5;
NET "AD23" IOSTANDARD = PCI33_5;
NET "AD24" IOSTANDARD = PCI33_5;
NET "AD25" IOSTANDARD = PCI33_5;
NET "AD26" IOSTANDARD = PCI33_5;
NET "AD27" IOSTANDARD = PCI33_5;
NET "AD28" IOSTANDARD = PCI33_5;
NET "AD29" IOSTANDARD = PCI33_5;
NET "AD30" IOSTANDARD = PCI33_5;
NET "AD31" IOSTANDARD = PCI33_5;
 
INST "CBE0.PAD" TNM = "PCI_CBE";
INST "CBE1.PAD" TNM = "PCI_CBE";
INST "CBE2.PAD" TNM = "PCI_CBE";
INST "CBE3.PAD" TNM = "PCI_CBE";
 
NET "CBE0" IOSTANDARD = PCI33_5;
NET "CBE1" IOSTANDARD = PCI33_5;
NET "CBE2" IOSTANDARD = PCI33_5;
NET "CBE3" IOSTANDARD = PCI33_5;
 
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK";
TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "DEVSEL" IOSTANDARD = PCI33_5;
NET "DEVSEL" OFFSET = IN 7 ns BEFORE "CLK";
NET "DEVSEL" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "FRAME" IOSTANDARD = PCI33_5;
NET "FRAME" OFFSET = IN 7 ns BEFORE "CLK";
NET "FRAME" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "GNT" IOSTANDARD = PCI33_5;
NET "GNT" OFFSET = IN 10 ns BEFORE "CLK";
 
NET "INTA" IOSTANDARD = PCI33_5;
 
NET "RST" IOSTANDARD = PCI33_5;
 
NET "IRDY" IOSTANDARD = PCI33_5;
NET "IRDY" OFFSET = IN 7 ns BEFORE "CLK";
NET "IRDY" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "PAR" IOSTANDARD = PCI33_5;
NET "PAR" OFFSET = IN 7 ns BEFORE "CLK";
NET "PAR" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "PERR" IOSTANDARD = PCI33_5;
NET "PERR" OFFSET = IN 7 ns BEFORE "CLK";
NET "PERR" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "REQ" IOSTANDARD = PCI33_5;
NET "REQ" OFFSET = OUT 12 ns AFTER "CLK";
 
NET "SERR" IOSTANDARD = PCI33_5;
NET "SERR" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "STOP" IOSTANDARD = PCI33_5;
NET "STOP" OFFSET = IN 7 ns BEFORE "CLK";
NET "STOP" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "TRDY" IOSTANDARD = PCI33_5;
NET "TRDY" OFFSET = IN 7 ns BEFORE "CLK";
NET "TRDY" OFFSET = OUT 10 ns AFTER "CLK";
 
NET "IDSEL" IOSTANDARD = PCI33_5;
 
####################################################################
# Pin locations
####################################################################
NET "CLK" LOC = "P185";
NET "INTA" LOC = "P195";
NET "RST" LOC = "P199";
NET "GNT" LOC = "P200";
NET "REQ" LOC = "P201";
 
NET "AD0" LOC = "P67";
NET "AD1" LOC = "P63";
NET "AD2" LOC = "P62";
NET "AD3" LOC = "P61";
NET "AD4" LOC = "P59";
NET "AD5" LOC = "P58";
NET "AD6" LOC = "P57";
NET "AD7" LOC = "P49";
NET "AD8" LOC = "P47";
NET "AD9" LOC = "P46";
NET "AD10" LOC = "P45";
NET "AD11" LOC = "P43";
NET "AD12" LOC = "P42";
NET "AD13" LOC = "P41";
NET "AD14" LOC = "P37";
NET "AD15" LOC = "P36";
NET "AD16" LOC = "P21";
NET "AD17" LOC = "P20";
NET "AD18" LOC = "P18";
NET "AD19" LOC = "P17";
NET "AD20" LOC = "P16";
NET "AD21" LOC = "P15";
NET "AD22" LOC = "P14";
NET "AD23" LOC = "P10";
NET "AD24" LOC = "P6";
NET "AD25" LOC = "P5";
NET "AD26" LOC = "P4";
NET "AD27" LOC = "P3";
NET "AD28" LOC = "P206";
NET "AD29" LOC = "P205";
NET "AD30" LOC = "P204";
NET "AD31" LOC = "P203";
 
NET "CBE0" LOC = "P48";
NET "CBE1" LOC = "P35";
NET "CBE2" LOC = "P22";
NET "CBE3" LOC = "P8";
 
NET "IDSEL" LOC = "P9";
NET "FRAME" LOC = "P23";
NET "IRDY" LOC = "P24";
NET "TRDY" LOC = "P27";
NET "DEVSEL" LOC = "P29";
NET "STOP" LOC = "P30";
NET "PERR" LOC = "P31";
NET "SERR" LOC = "P33";
NET "PAR" LOC = "P34";
 
NET "DSP_HINT" LOC = "P127";
NET "DSP_INT2" LOC = "P115";
NET "DSP_RST" LOC = "P101";
 
NET "DSP_HAD[0]" LOC = "P123";
NET "DSP_HAD[1]" LOC = "P112";
NET "DSP_HAD[2]" LOC = "P109";
NET "DSP_HAD[3]" LOC = "P102";
NET "DSP_HAD[4]" LOC = "P166";
NET "DSP_HAD[5]" LOC = "P165";
NET "DSP_HAD[6]" LOC = "P162";
NET "DSP_HAD[7]" LOC = "P161";
 
NET "DSP_HCNTL[0]" LOC = "P147";
NET "DSP_HCNTL[1]" LOC = "P139";
NET "DSP_HBIL" LOC = "P121";
NET "DSP_HCS" LOC = "P154";
NET "DSP_HDS1" LOC = "P164";
NET "DSP_HDS2" LOC = "P163";
NET "DSP_HRW" LOC = "P152";
NET "DSP_HRDY" LOC = "P125";
NET "DSP_HAS" LOC = "P160";
 
NET "LED" LOC = "P202";
/syn/xilinxISE/src/xilinx.npl
0,0 → 1,21
JDF E
// Created by ISE ver 1.0
PROJECT xilinx
DESIGN xilinx Normal
DEVKIT xc2s200-5pq208
DEVFAM spartan2
FLOW EDIF
MODULE ..\..\synplify\out\pci2dsp.edn
MODSTYLE TOP Normal
[STRATEGY-LIST]
Normal=True, 1034858003
[Normal]
xilxNgdbldUCF=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1038923296, ..\ucf\pci2dsp.ucf
xilxMapPackRegInto=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1035374944, For Inputs and Outputs
xilxPAReffortLevel=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, Highest
xilxPARroutingPasses=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, 0
xilxPARdelayBasedPasses=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, 0
mpprStartingPlacerCostTbl=edif, SPARTAN2, Implementation.t_mppr, 1027686417, 20
mpprPARiterations=edif, SPARTAN2, Implementation.t_mppr, 1027687139, 0
mpprResultsToSave=edif, SPARTAN2, Implementation.t_mppr, 1027687139, 1
xilxBitgCfg_GenOpt_MaskFile=edif, SPARTAN2, Implementation.t_bitFile, 1034850741, True
/syn/xilinxISE/src/README.txt
0,0 → 1,21
Just start Multipass Place & Route

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