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URL https://opencores.org/ocsvn/wb4pb/wb4pb/trunk

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/pbwbuart.psm
0,0 → 1,435
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; This sourcecode is released under BSD license.
;; Please see http://www.opensource.org/licenses/bsd-license.php for details!
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
;; All rights reserved.
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright notice,
;; this list of conditions and the following disclaimer in the documentation
;; and/or other materials provided with the distribution.
;; * Neither the name of the author nor the names of his contributors may be
;; used to endorse or promote products derived from this software without
;; specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;; POSSIBILITY OF SUCH DAMAGE.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; filename: pbwbuart.psm
;; description: uart example, demonstrating access to wishbone peripherals
;; todo4user: modify main program and uart code as needed, i. e. non-blocking
;; read and write transactions or data burst transfers
;; version: 0.0.0
;; changelog: - 0.0.0, initial release
;; - ...
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
; wishbone variables
NAMEREG sF , wb_addr
NAMEREG sE , wb_data ; also used as tmp-reg for status polling
 
; uart variables
NAMEREG sD , uart_data
 
 
ADDRESS 000
 
; main entry point
;;;;;;;;;;;;;;;;;;
 
DISABLE INTERRUPT
 
CALL uart_init
 
; obligatory "Hello World!" message
 
; new line
LOAD uart_data , ASCII_CR_CHAR
CALL uart_wr_byte
LOAD uart_data , ASCII_LF_CHAR
CALL uart_wr_byte
; H
LOAD uart_data , ASCII_H_UC
CALL uart_wr_byte
; e
LOAD uart_data , ASCII_E_LC
CALL uart_wr_byte
; l
LOAD uart_data , ASCII_L_LC
CALL uart_wr_byte
; l
LOAD uart_data , ASCII_L_LC
CALL uart_wr_byte
; o
LOAD uart_data , ASCII_O_LC
CALL uart_wr_byte
; space
LOAD uart_data , ASCII_SP_CHAR
CALL uart_wr_byte
; W
LOAD uart_data , ASCII_W_UC
CALL uart_wr_byte
; o
LOAD uart_data , ASCII_O_LC
CALL uart_wr_byte
; r
LOAD uart_data , ASCII_R_LC
CALL uart_wr_byte
; l
LOAD uart_data , ASCII_L_LC
CALL uart_wr_byte
; d
LOAD uart_data , ASCII_D_LC
CALL uart_wr_byte
; !
LOAD uart_data , ASCII_EXCLAMATION_MARK_SIGN
CALL uart_wr_byte
; new line
LOAD uart_data , ASCII_CR_CHAR
CALL uart_wr_byte
LOAD uart_data , ASCII_LF_CHAR
CALL uart_wr_byte
 
; simple loopback of uart data
mainloop:
CALL uart_rd_byte
CALL uart_wr_byte
JUMP mainloop
; wbs_uart module subroutines and settings
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
; usage:
; 1. set baud rate in uart_init subroutine
; 2. call uart_init subroutine to configure wbs_uart module for operation
; 3. use uart_wr_byte and uart_rd_byte subroutines to access uart transceiver,
; all accesses are blocking, subroutines do not return, if wbs_uart tx buffer
; is full or rx buffer is empty
; uart write code =>
; LOAD uart_data , <user data> ; setting up data
; CALL uart_wr_byte ; writing data to uart module
; <next user instruction>
; uart read code =>
; CALL uart_rd_byte ; reading data from uart module
; LOAD <user data> , uart_data ; uart_data is updated now
; <next user instruction>
; 4. uart_clr_buff subroutine can be used to discard wbs_uart rx buffer contents
; during software runtime
 
; uart start-up configuration, i. e. baudrate
uart_init:
; setting baud rate
LOAD wb_addr , UART_BAUD_LO_ADDR
LOAD wb_data , UART_BAUD_LO_115200_VALUE
CALL wb_wr
LOAD wb_addr , UART_BAUD_HI_ADDR
LOAD wb_data , UART_BAUD_HI_115200_VALUE
CALL wb_wr
; clear uart receive buffer, after power up and change of baud rate, there is
; maybe invalid data in it
CALL uart_clr_buff
RETURN
 
; blocking write byte to uart
uart_wr_byte:
LOAD wb_addr , UART_RXTX_ADDR
LOAD wb_data , uart_data
CALL wb_wr
RETURN
 
; blocking read byte from uart
uart_rd_byte:
LOAD wb_addr , UART_RXTX_ADDR
CALL wb_rd
LOAD uart_data , wb_data
RETURN
 
; uart rx buffer clear
uart_clr_buff:
; uart receive buffer software reset, checking status register for level and
; reading out all available data
LOAD wb_addr , UART_SR_ADDR ; setting status register address
CALL wb_rd
; checking data present flag
TEST wb_data , UART_SR_RX_DP_FLAG
; if flag is not set, returning immediately
JUMP NZ , uart_clr_buff_l0
RETURN
; else reading out next byte and checking flag again
uart_clr_buff_l0:
CALL uart_rd_byte
JUMP uart_clr_buff
 
; register and flag addressing
CONSTANT UART_RXTX_ADDR , 00 ; receive/transmit data pipe
CONSTANT UART_SR_ADDR , 01 ; status register
CONSTANT UART_SR_RX_F_FLAG , 01 ; status rx full
CONSTANT UART_SR_RX_HF_FLAG , 02 ; status rx half full
CONSTANT UART_SR_RX_DP_FLAG , 04 ; status rx data present
CONSTANT UART_SR_TX_F_FLAG , 10 ; status tx full
CONSTANT UART_SR_TX_HF_FLAG , 20 ; status tx half full
CONSTANT UART_BAUD_LO_ADDR , 02 ; baud rate cfg. register / low byte
CONSTANT UART_BAUD_HI_ADDR , 03 ; baud rate cfg. register / high byte
 
; baud rate configuration:
; baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
; i. e. 9600 baud at 50 MHz system clock =>
; baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
 
; WARNING, baud rate error should not exceed 1.0 % for reliable operation!
 
; baud rate settings for 50.0E6 Hz system reference clock
; max. 3125000.0 baud
; min. 48.0 baud (16 bit baud timer)
CONSTANT UART_BAUD_LO_300_VALUE , B0 ; actual baud rate 299.99
CONSTANT UART_BAUD_HI_300_VALUE , 28 ; => baud rate error 0.003 %
CONSTANT UART_BAUD_LO_600_VALUE , 57 ; actual baud rate 600.04
CONSTANT UART_BAUD_HI_600_VALUE , 14 ; => baud rate error 0.006 %
CONSTANT UART_BAUD_LO_1200_VALUE , 2B ; actual baud rate 1200.08
CONSTANT UART_BAUD_HI_1200_VALUE , 0A ; => baud rate error 0.006 %
CONSTANT UART_BAUD_LO_2400_VALUE , 15 ; actual baud rate 2400.15
CONSTANT UART_BAUD_HI_2400_VALUE , 05 ; => baud rate error 0.006 %
CONSTANT UART_BAUD_LO_4800_VALUE , 8A ; actual baud rate 4800.31
CONSTANT UART_BAUD_HI_4800_VALUE , 02 ; => baud rate error 0.006 %
CONSTANT UART_BAUD_LO_9600_VALUE , 45 ; actual baud rate 9585.89
CONSTANT UART_BAUD_HI_9600_VALUE , 01 ; => baud rate error 0.147 %
CONSTANT UART_BAUD_LO_19200_VALUE , A2 ; actual baud rate 19171.78
CONSTANT UART_BAUD_HI_19200_VALUE , 00 ; => baud rate error 0.147 %
CONSTANT UART_BAUD_LO_38400_VALUE , 50 ; actual baud rate 38580.25
CONSTANT UART_BAUD_HI_38400_VALUE , 00 ; => baud rate error 0.467 %
CONSTANT UART_BAUD_LO_57600_VALUE , 35 ; actual baud rate 57870.37
CONSTANT UART_BAUD_HI_57600_VALUE , 00 ; => baud rate error 0.467 %
CONSTANT UART_BAUD_LO_115200_VALUE , 1A ; actual baud rate 115740.74
CONSTANT UART_BAUD_HI_115200_VALUE , 00 ; => baud rate error 0.467 %
;CONSTANT UART_BAUD_LO_230400_VALUE , 0D ; actual baud rate 223214.29
;CONSTANT UART_BAUD_HI_230400_VALUE , 00 ; => baud rate error 3.219 %
;CONSTANT UART_BAUD_LO_460800_VALUE , 06 ; actual baud rate 446428.57
;CONSTANT UART_BAUD_HI_460800_VALUE , 00 ; => baud rate error 3.219 %
;CONSTANT UART_BAUD_LO_921600_VALUE , 02 ; actual baud rate 1041666.67
;CONSTANT UART_BAUD_HI_921600_VALUE , 00 ; => baud rate error 11.526 %
 
 
; wbm_picoblaze module subroutines and settings
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
; is a supporting subroutine, which should not be called directly
;
; transfer principle wishbone write:
; 1. OUTPUT cycle to set up wishbone address, data and control signals from
; PORT_ID, OUT_PORT and WRITE_STROBE
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
; => at least one OUTPUT and one INPUT cycle for a write
;
; transfer principle wishbone read:
; 1. INPUT cycle to set up wishbone address and control signals from PORT_ID
; and READ_STROBE
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
; 3. the very next INPUT cycle after acknowledgement contains valid wishbone
; data from IN_PORT
; => at least three INPUT cycles for a read
;
; calling examples:
;
; wishbone write code =>
;
; LOAD wb_addr , <user address> ; setting up address
; LOAD wb_data , <user data> ; setting up data
; CALL wb_wr ; starting wishbone write cycle
; <next user instruction> ; wishbone cycle finished
;
; wishbone read code =>
;
; LOAD wb_addr , <user address> ; setting up address
; CALL wb_rd ; starting wishbone read cycle
; LOAD <user data> , wb_data ; wb_data is updated now
; <next user instruction> ; wishbone cycle finished
 
; wishbone write access
wb_wr:
OUTPUT wb_data , (wb_addr)
CALL wb_wait_on_ack
RETURN
 
; wishbone read access
wb_rd:
CALL wb_wait_on_ack
INPUT wb_data , (wb_addr)
RETURN
 
; waiting on wishbone cycle to complete
wb_wait_on_ack:
INPUT wb_data , (wb_addr)
TEST wb_data , WB_ACK_FLAG
JUMP Z , wb_wait_on_ack
RETURN
 
CONSTANT WB_ACK_FLAG , 01
 
 
; interrupt subroutines and settings
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
; IMPORTANT NOTICE!
; be carefull, if using interrupts. wishbone cycles must be atomar, as any
; other processor local bus cycles are normally be. interrupting wishbone
; access may cause a crash of external wishbone master fsm, especially, if
; program flow through isr leads to another wishbone cycle!
 
; interrupt handling template, if needed
isr:
RETURNI DISABLE
ADDRESS 3FF
JUMP isr
 
 
; ascii table
;;;;;;;;;;;;;
 
CONSTANT ASCII_NUL_CHAR , 00 ; NUL
CONSTANT ASCII_SOH_CHAR , 01 ; SOH
CONSTANT ASCII_STX_CHAR , 02 ; STX
CONSTANT ASCII_ETX_CHAR , 03 ; ETX
CONSTANT ASCII_EOT_CHAR , 04 ; EOT
CONSTANT ASCII_ENQ_CHAR , 05 ; ENQ
CONSTANT ASCII_ACK_CHAR , 06 ; ACK
CONSTANT ASCII_BEL_CHAR , 07 ; BEL
CONSTANT ASCII_BS_CHAR , 08 ; BS
CONSTANT ASCII_TAB_CHAR , 09 ; TAB
CONSTANT ASCII_LF_CHAR , 0A ; LF
CONSTANT ASCII_VT_CHAR , 0B ; VT
CONSTANT ASCII_FF_CHAR , 0C ; FF
CONSTANT ASCII_CR_CHAR , 0D ; CR
CONSTANT ASCII_SO_CHAR , 0E ; SO
CONSTANT ASCII_SI_CHAR , 0F ; SI
CONSTANT ASCII_DLE_CHAR , 10 ; DLE
CONSTANT ASCII_DC1_CHAR , 11 ; DC1
CONSTANT ASCII_DC2_CHAR , 12 ; DC2
CONSTANT ASCII_DC3_CHAR , 13 ; DC3
CONSTANT ASCII_DC4_CHAR , 14 ; DC4
CONSTANT ASCII_NAK_CHAR , 15 ; NAK
CONSTANT ASCII_SYN_CHAR , 16 ; SYN
CONSTANT ASCII_ETB_CHAR , 17 ; ETB
CONSTANT ASCII_CAN_CHAR , 18 ; CAN
CONSTANT ASCII_EM_CHAR , 19 ; EM
CONSTANT ASCII_SUB_CHAR , 1A ; SUB
CONSTANT ASCII_ESC_CHAR , 1B ; ESC
CONSTANT ASCII_FS_CHAR , 1C ; FS
CONSTANT ASCII_GS_CHAR , 1D ; GS
CONSTANT ASCII_RS_CHAR , 1E ; RS
CONSTANT ASCII_US_CHAR , 1F ; US
CONSTANT ASCII_SP_CHAR , 20 ; SP
CONSTANT ASCII_EXCLAMATION_MARK_SIGN , 21 ; !
CONSTANT ASCII_DOUBLE_QUOTE_SIGN , 22 ; "
CONSTANT ASCII_NUMBER_SIGN , 23 ; #
CONSTANT ASCII_DOLLAR_SIGN , 24 ; $
CONSTANT ASCII_PERCENT_SIGN , 25 ; %
CONSTANT ASCII_AMPERSAND_SIGN , 26 ; &
CONSTANT ASCII_SINGLE_QUOTE_SIGN , 27 ; '
CONSTANT ASCII_OPN_PARENTHESIS_SIGN , 28 ; (
CONSTANT ASCII_CLS_PARENTHESIS_SIGN , 29 ; )
CONSTANT ASCII_ASTERISK_SIGN , 2A ; *
CONSTANT ASCII_PLUS_SIGN , 2B ; +
CONSTANT ASCII_COMMA_SIGN , 2C ; ,
CONSTANT ASCII_MINUS_SIGN , 2D ; -
CONSTANT ASCII_DOT_SIGN , 2E ; .
CONSTANT ASCII_SLASH_SIGN , 2F ; /
CONSTANT ASCII_0_DIGIT , 30 ; 0
CONSTANT ASCII_1_DIGIT , 31 ; 1
CONSTANT ASCII_2_DIGIT , 32 ; 2
CONSTANT ASCII_3_DIGIT , 33 ; 3
CONSTANT ASCII_4_DIGIT , 34 ; 4
CONSTANT ASCII_5_DIGIT , 35 ; 5
CONSTANT ASCII_6_DIGIT , 36 ; 6
CONSTANT ASCII_7_DIGIT , 37 ; 7
CONSTANT ASCII_8_DIGIT , 38 ; 8
CONSTANT ASCII_9_DIGIT , 39 ; 9
CONSTANT ASCII_COLON_SIGN , 3A ; :
CONSTANT ASCII_SEMICOLON_SIGN , 3B ; ;
CONSTANT ASCII_LESS_THAN_SIGN , 3C ; <
CONSTANT ASCII_EQUAL_SIGN , 3D ; =
CONSTANT ASCII_GREATER_THAN_SIGN , 3E ; >
CONSTANT ASCII_QUESTION_MARK_SIGN , 3F ; ?
CONSTANT ASCII_AT_SIGN , 40 ; @
CONSTANT ASCII_A_UC , 41 ; A
CONSTANT ASCII_B_UC , 42 ; B
CONSTANT ASCII_C_UC , 43 ; C
CONSTANT ASCII_D_UC , 44 ; D
CONSTANT ASCII_E_UC , 45 ; E
CONSTANT ASCII_F_UC , 46 ; F
CONSTANT ASCII_G_UC , 47 ; G
CONSTANT ASCII_H_UC , 48 ; H
CONSTANT ASCII_I_UC , 49 ; I
CONSTANT ASCII_J_UC , 4A ; J
CONSTANT ASCII_K_UC , 4B ; K
CONSTANT ASCII_L_UC , 4C ; L
CONSTANT ASCII_M_UC , 4D ; M
CONSTANT ASCII_N_UC , 4E ; N
CONSTANT ASCII_O_UC , 4F ; O
CONSTANT ASCII_P_UC , 50 ; P
CONSTANT ASCII_Q_UC , 51 ; Q
CONSTANT ASCII_R_UC , 52 ; R
CONSTANT ASCII_S_UC , 53 ; S
CONSTANT ASCII_T_UC , 54 ; T
CONSTANT ASCII_U_UC , 55 ; U
CONSTANT ASCII_V_UC , 56 ; V
CONSTANT ASCII_W_UC , 57 ; W
CONSTANT ASCII_X_UC , 58 ; X
CONSTANT ASCII_Y_UC , 59 ; Y
CONSTANT ASCII_Z_UC , 5A ; Z
CONSTANT ASCII_OPN_BRACKET_SIGN , 5B ; [
CONSTANT ASCII_BACKSLASH_SIGN , 5C ; \
CONSTANT ASCII_CLS_BRACKET_SIGN , 5D ; ]
CONSTANT ASCII_CARET_SIGN , 5E ; ^
CONSTANT ASCII_UNDERSCORE_SIGN , 5F ; _
CONSTANT ASCII_ACCENT_SIGN , 60 ; `
CONSTANT ASCII_A_LC , 61 ; a
CONSTANT ASCII_B_LC , 62 ; b
CONSTANT ASCII_C_LC , 63 ; c
CONSTANT ASCII_D_LC , 64 ; d
CONSTANT ASCII_E_LC , 65 ; e
CONSTANT ASCII_F_LC , 66 ; f
CONSTANT ASCII_G_LC , 67 ; g
CONSTANT ASCII_H_LC , 68 ; h
CONSTANT ASCII_I_LC , 69 ; i
CONSTANT ASCII_J_LC , 6A ; j
CONSTANT ASCII_K_LC , 6B ; k
CONSTANT ASCII_L_LC , 6C ; l
CONSTANT ASCII_M_LC , 6D ; m
CONSTANT ASCII_N_LC , 6E ; n
CONSTANT ASCII_O_LC , 6F ; o
CONSTANT ASCII_P_LC , 70 ; p
CONSTANT ASCII_Q_LC , 71 ; q
CONSTANT ASCII_R_LC , 72 ; r
CONSTANT ASCII_S_LC , 73 ; s
CONSTANT ASCII_T_LC , 74 ; t
CONSTANT ASCII_U_LC , 75 ; u
CONSTANT ASCII_V_LC , 76 ; v
CONSTANT ASCII_W_LC , 77 ; w
CONSTANT ASCII_X_LC , 78 ; x
CONSTANT ASCII_Y_LC , 79 ; y
CONSTANT ASCII_Z_LC , 7A ; z
CONSTANT ASCII_OPN_BRACE_SIGN , 7B ; {
CONSTANT ASCII_VERTICAL_BAR_SIGN , 7C ; |
CONSTANT ASCII_CLS_BRACE_SIGN , 7D ; }
CONSTANT ASCII_TILDE_SIGN , 7E ; ~
CONSTANT ASCII_DEL_CHAR , 7F ; DEL
/PBWBUART.VHD
0,0 → 1,274
--
-- Definition of a single port ROM for KCPSM3 program defined by pbwbuart.psm
--
-- Generated by KCPSM3 Assembler 07Feb2010-11:49:50.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity pbwbuart is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end pbwbuart;
--
architecture low_level_definition of pbwbuart is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "002D0D6F002D0D6C002D0D6C002D0D65002D0D48002D0D0A002D0D0D0025C000";
attribute INIT_01 of ram_1024_x_18 : label is "002D0D0D002D0D21002D0D64002D0D6C002D0D72002D0D6F002D0D57002D0D20";
attribute INIT_02 of ram_1024_x_18 : label is "003C1ED00F00A0000035003C0E000F03003C0E1A0F024022002D0031002D0D0A";
attribute INIT_03 of ram_1024_x_18 : label is "0042A0000042DEF040350031A000543A2E04003F0F01A0001DE0003F0F00A000";
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000008000A00050422E015EF0A0005EF0";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "4046000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "00000000000000000000000000003B48EEFB7232C2F0C3FCCCCCCCCCCCCCCCCF";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "C000000000000000000000000000000000000000000000000000000000000000";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"002D0D6F002D0D6C002D0D6C002D0D65002D0D48002D0D0A002D0D0D0025C000",
INIT_01 => X"002D0D0D002D0D21002D0D64002D0D6C002D0D72002D0D6F002D0D57002D0D20",
INIT_02 => X"003C1ED00F00A0000035003C0E000F03003C0E1A0F024022002D0031002D0D0A",
INIT_03 => X"0042A0000042DEF040350031A000543A2E04003F0F01A0001DE0003F0F00A000",
INIT_04 => X"0000000000000000000000000000000000008000A00050422E015EF0A0005EF0",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"4046000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000003B48EEFB7232C2F0C3FCCCCCCCCCCCCCCCCF",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE pbwbuart.vhd
--
------------------------------------------------------------------------------------
/PBWBUART.V
0,0 → 1,262
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: v1.30
// \ \ Application : KCPSM3
// / / Filename: pbwbuart.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//Command: kcpsm3 pbwbuart.psm
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
//Design Name: pbwbuart
//Generated 07Feb2010-11:49:50.
//Purpose:
// pbwbuart verilog program definition.
//
//Reference:
// PicoBlaze 8-bit Embedded Microcontroller User Guide
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module pbwbuart (address, instruction, clk);
input [9:0] address;
input clk;
output [17:0] instruction;
RAMB16_S18 ram_1024_x_18(
.DI (16'h0000),
.DIP (2'b00),
.EN (1'b1),
.WE (1'b0),
.SSR (1'b0),
.CLK (clk),
.ADDR (address),
.DO (instruction[15:0]),
.DOP (instruction[17:16]))
/*synthesis
init_00 = "002D0D6F002D0D6C002D0D6C002D0D65002D0D48002D0D0A002D0D0D0025C000"
init_01 = "002D0D0D002D0D21002D0D64002D0D6C002D0D72002D0D6F002D0D57002D0D20"
init_02 = "003C1ED00F00A0000035003C0E000F03003C0E1A0F024022002D0031002D0D0A"
init_03 = "0042A0000042DEF040350031A000543A2E04003F0F01A0001DE0003F0F00A000"
init_04 = "0000000000000000000000000000000000008000A00050422E015EF0A0005EF0"
init_05 = "0000000000000000000000000000000000000000000000000000000000000000"
init_06 = "0000000000000000000000000000000000000000000000000000000000000000"
init_07 = "0000000000000000000000000000000000000000000000000000000000000000"
init_08 = "0000000000000000000000000000000000000000000000000000000000000000"
init_09 = "0000000000000000000000000000000000000000000000000000000000000000"
init_0A = "0000000000000000000000000000000000000000000000000000000000000000"
init_0B = "0000000000000000000000000000000000000000000000000000000000000000"
init_0C = "0000000000000000000000000000000000000000000000000000000000000000"
init_0D = "0000000000000000000000000000000000000000000000000000000000000000"
init_0E = "0000000000000000000000000000000000000000000000000000000000000000"
init_0F = "0000000000000000000000000000000000000000000000000000000000000000"
init_10 = "0000000000000000000000000000000000000000000000000000000000000000"
init_11 = "0000000000000000000000000000000000000000000000000000000000000000"
init_12 = "0000000000000000000000000000000000000000000000000000000000000000"
init_13 = "0000000000000000000000000000000000000000000000000000000000000000"
init_14 = "0000000000000000000000000000000000000000000000000000000000000000"
init_15 = "0000000000000000000000000000000000000000000000000000000000000000"
init_16 = "0000000000000000000000000000000000000000000000000000000000000000"
init_17 = "0000000000000000000000000000000000000000000000000000000000000000"
init_18 = "0000000000000000000000000000000000000000000000000000000000000000"
init_19 = "0000000000000000000000000000000000000000000000000000000000000000"
init_1A = "0000000000000000000000000000000000000000000000000000000000000000"
init_1B = "0000000000000000000000000000000000000000000000000000000000000000"
init_1C = "0000000000000000000000000000000000000000000000000000000000000000"
init_1D = "0000000000000000000000000000000000000000000000000000000000000000"
init_1E = "0000000000000000000000000000000000000000000000000000000000000000"
init_1F = "0000000000000000000000000000000000000000000000000000000000000000"
init_20 = "0000000000000000000000000000000000000000000000000000000000000000"
init_21 = "0000000000000000000000000000000000000000000000000000000000000000"
init_22 = "0000000000000000000000000000000000000000000000000000000000000000"
init_23 = "0000000000000000000000000000000000000000000000000000000000000000"
init_24 = "0000000000000000000000000000000000000000000000000000000000000000"
init_25 = "0000000000000000000000000000000000000000000000000000000000000000"
init_26 = "0000000000000000000000000000000000000000000000000000000000000000"
init_27 = "0000000000000000000000000000000000000000000000000000000000000000"
init_28 = "0000000000000000000000000000000000000000000000000000000000000000"
init_29 = "0000000000000000000000000000000000000000000000000000000000000000"
init_2A = "0000000000000000000000000000000000000000000000000000000000000000"
init_2B = "0000000000000000000000000000000000000000000000000000000000000000"
init_2C = "0000000000000000000000000000000000000000000000000000000000000000"
init_2D = "0000000000000000000000000000000000000000000000000000000000000000"
init_2E = "0000000000000000000000000000000000000000000000000000000000000000"
init_2F = "0000000000000000000000000000000000000000000000000000000000000000"
init_30 = "0000000000000000000000000000000000000000000000000000000000000000"
init_31 = "0000000000000000000000000000000000000000000000000000000000000000"
init_32 = "0000000000000000000000000000000000000000000000000000000000000000"
init_33 = "0000000000000000000000000000000000000000000000000000000000000000"
init_34 = "0000000000000000000000000000000000000000000000000000000000000000"
init_35 = "0000000000000000000000000000000000000000000000000000000000000000"
init_36 = "0000000000000000000000000000000000000000000000000000000000000000"
init_37 = "0000000000000000000000000000000000000000000000000000000000000000"
init_38 = "0000000000000000000000000000000000000000000000000000000000000000"
init_39 = "0000000000000000000000000000000000000000000000000000000000000000"
init_3A = "0000000000000000000000000000000000000000000000000000000000000000"
init_3B = "0000000000000000000000000000000000000000000000000000000000000000"
init_3C = "0000000000000000000000000000000000000000000000000000000000000000"
init_3D = "0000000000000000000000000000000000000000000000000000000000000000"
init_3E = "0000000000000000000000000000000000000000000000000000000000000000"
init_3F = "4046000000000000000000000000000000000000000000000000000000000000"
initp_00 = "00000000000000000000000000003B48EEFB7232C2F0C3FCCCCCCCCCCCCCCCCF"
initp_01 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_02 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_03 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_04 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_05 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_06 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_07 = "C000000000000000000000000000000000000000000000000000000000000000" */;
// synthesis translate_off
// Attributes for Simulation
defparam ram_1024_x_18.INIT_00 = 256'h002D0D6F002D0D6C002D0D6C002D0D65002D0D48002D0D0A002D0D0D0025C000;
defparam ram_1024_x_18.INIT_01 = 256'h002D0D0D002D0D21002D0D64002D0D6C002D0D72002D0D6F002D0D57002D0D20;
defparam ram_1024_x_18.INIT_02 = 256'h003C1ED00F00A0000035003C0E000F03003C0E1A0F024022002D0031002D0D0A;
defparam ram_1024_x_18.INIT_03 = 256'h0042A0000042DEF040350031A000543A2E04003F0F01A0001DE0003F0F00A000;
defparam ram_1024_x_18.INIT_04 = 256'h0000000000000000000000000000000000008000A00050422E015EF0A0005EF0;
defparam ram_1024_x_18.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3F = 256'h4046000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_00 = 256'h00000000000000000000000000003B48EEFB7232C2F0C3FCCCCCCCCCCCCCCCCF;
defparam ram_1024_x_18.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_07 = 256'hC000000000000000000000000000000000000000000000000000000000000000;
// synthesis translate_on
// Attributes for XST (Synplicity attributes are in-line)
// synthesis attribute INIT_00 of ram_1024_x_18 is "002D0D6F002D0D6C002D0D6C002D0D65002D0D48002D0D0A002D0D0D0025C000"
// synthesis attribute INIT_01 of ram_1024_x_18 is "002D0D0D002D0D21002D0D64002D0D6C002D0D72002D0D6F002D0D57002D0D20"
// synthesis attribute INIT_02 of ram_1024_x_18 is "003C1ED00F00A0000035003C0E000F03003C0E1A0F024022002D0031002D0D0A"
// synthesis attribute INIT_03 of ram_1024_x_18 is "0042A0000042DEF040350031A000543A2E04003F0F01A0001DE0003F0F00A000"
// synthesis attribute INIT_04 of ram_1024_x_18 is "0000000000000000000000000000000000008000A00050422E015EF0A0005EF0"
// synthesis attribute INIT_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_07 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_08 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_09 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_10 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_11 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_12 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_13 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_14 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_15 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_16 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_17 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_18 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_19 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_20 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_21 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_22 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_23 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_24 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_25 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_26 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_27 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_28 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_29 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_30 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_31 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_32 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_33 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_34 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_35 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_36 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_37 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_38 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_39 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3F of ram_1024_x_18 is "4046000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_00 of ram_1024_x_18 is "00000000000000000000000000003B48EEFB7232C2F0C3FCCCCCCCCCCCCCCCCF"
// synthesis attribute INITP_01 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_07 of ram_1024_x_18 is "C000000000000000000000000000000000000000000000000000000000000000"
endmodule
// END OF FILE pbwbuart.v

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