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    /wb4pb/trunk/rtl
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Rev 10 → Rev 12

/picoblaze_wb_uart.v
0,0 → 1,147
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: picoblaze_wb_uart.v
// description: synthesizable PicoBlaze (TM) uart example using wishbone
// todo4user: add other modules as needed
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module picoblaze_wb_uart (
p_rst_n_i,
p_clk_i,
p_uart_rx_si_i,
p_uart_tx_so_o
);
 
input p_rst_n_i;
wire p_rst_n_i;
input p_clk_i;
wire p_clk_i;
input p_uart_rx_si_i;
wire p_uart_rx_si_i;
output p_uart_tx_so_o;
wire p_uart_tx_so_o;
 
reg rst;
wire clk;
wire wb_cyc;
wire wb_stb;
wire wb_we;
wire[7:0] wb_adr;
wire[7:0] wb_dat_m2s;
wire[7:0] wb_dat_s2m;
wire wb_ack;
wire pb_write_strobe;
wire pb_read_strobe;
wire[7:0] pb_port_id;
wire[7:0] pb_in_port;
wire[7:0] pb_out_port;
wire[17:0] instruction;
wire[9:0] address;
wire interrupt;
wire interrupt_ack;
// reset synchronisation
always@(clk)
rst <= ! p_rst_n_i;
assign clk = p_clk_i;
// module instances
///////////////////
kcpsm3 inst_kcpsm3 (
.address(address),
.instruction(instruction),
.port_id(pb_port_id),
.write_strobe(pb_write_strobe),
.out_port(pb_out_port),
.read_strobe(pb_read_strobe),
.in_port(pb_in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(rst),
.clk(clk)
);
 
pbwbuart inst_pbwbuart (
.address(address),
.instruction(instruction),
.clk(clk)
);
 
wbm_picoblaze inst_wbm_picoblaze (
.rst(rst),
.clk(clk),
.wbm_cyc_o(wb_cyc),
.wbm_stb_o(wb_stb),
.wbm_we_o(wb_we),
.wbm_adr_o(wb_adr),
.wbm_dat_m2s_o(wb_dat_m2s),
.wbm_dat_s2m_i(wb_dat_s2m),
.wbm_ack_i(wb_ack),
.pb_port_id_i(pb_port_id),
.pb_write_strobe_i(pb_write_strobe),
.pb_out_port_i(pb_out_port),
.pb_read_strobe_i(pb_read_strobe),
.pb_in_port_o(pb_in_port)
);
 
wbs_uart inst_wbs_uart (
.rst(rst),
.clk(clk),
.wbs_cyc_i(wb_cyc),
.wbs_stb_i(wb_stb),
.wbs_we_i(wb_we),
.wbs_adr_i(wb_adr),
.wbs_dat_m2s_i(wb_dat_m2s),
.wbs_dat_s2m_o(wb_dat_s2m),
.wbs_ack_o(wb_ack),
.uart_rx_si_i(p_uart_rx_si_i),
.uart_tx_so_o(p_uart_tx_so_o)
);
endmodule
/wbs_uart.vhd
0,0 → 1,246
--------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: wbs_uart.vhd
-- description: synthesizable wishbone slave uart sio module using Xilinx (R)
-- macros and adding some functionality like a configurable
-- baud rate and buffer level checking
-- todo4user: add other uart functionality as needed, i. e. interrupt logic or
-- modem control signals
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity wbs_uart is
port
(
rst : in std_logic;
clk : in std_logic;
wbs_cyc_i : in std_logic;
wbs_stb_i : in std_logic;
wbs_we_i : in std_logic;
wbs_adr_i : in std_logic_vector(7 downto 0);
wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
wbs_ack_o : out std_logic;
uart_rx_si_i : in std_logic;
uart_tx_so_o : out std_logic
);
end wbs_uart;
 
 
architecture rtl of wbs_uart is
 
signal wbs_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
signal wbs_ack : std_logic := '0';
signal uart_tx_so : std_logic := '0';
signal wb_reg_we : std_logic := '0';
constant ADDR_MSB : natural := 1;
constant UART_RXTX_ADDR : std_logic_vector(7 downto 0) := x"00";
constant UART_SR_ADDR : std_logic_vector(7 downto 0) := x"01";
constant UART_SR_RX_F_FLAG : natural := 0;
constant UART_SR_RX_HF_FLAG : natural := 1;
constant UART_SR_RX_DP_FLAG : natural := 2;
constant UART_SR_TX_F_FLAG : natural := 4;
constant UART_SR_TX_HF_FLAG : natural := 5;
constant UART_BAUD_LO_ADDR : std_logic_vector(7 downto 0) := x"02";
constant UART_BAUD_HI_ADDR : std_logic_vector(7 downto 0) := x"03";
signal baud_count : std_logic_vector(15 downto 0) := (others => '0');
signal baud_limit : std_logic_vector(15 downto 0) := (others => '0');
signal en_16_x_baud : std_logic := '0';
component uart_rx is
port
(
serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic
);
end component;
signal rx_read_buffer : std_logic := '0';
signal rx_buffer_full : std_logic := '0';
signal rx_buffer_half_full : std_logic := '0';
signal rx_buffer_data_present : std_logic := '0';
signal rx_data_out : std_logic_vector(7 downto 0) := (others => '0');
 
component uart_tx is
port
(
data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic
);
end component;
signal tx_write_buffer : std_logic := '0';
signal tx_buffer_full : std_logic := '0';
signal tx_buffer_half_full : std_logic := '0';
 
begin
 
wbs_dat_s2m_o <= wbs_dat_s2m;
wbs_ack_o <= wbs_ack;
uart_tx_so_o <= uart_tx_so;
-- internal register write enable signal
wb_reg_we <= wbs_cyc_i and wbs_stb_i and wbs_we_i;
process(clk)
begin
if clk'event and clk = '1' then
 
-- baud rate configuration:
-- baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
-- i. e. 9600 baud at 50 MHz system clock =>
-- baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
 
-- baud timer
if baud_count = baud_limit then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= std_logic_vector(unsigned(baud_count) + 1);
en_16_x_baud <= '0';
end if;
 
rx_read_buffer <= '0';
tx_write_buffer <= '0';
wbs_dat_s2m <= (others => '0');
-- registered wishbone slave handshake (default)
wbs_ack <= wbs_cyc_i and wbs_stb_i and (not wbs_ack);
case wbs_adr_i(ADDR_MSB downto 0) is
-- receive/transmit buffer access
when UART_RXTX_ADDR(ADDR_MSB downto 0) =>
if (wbs_cyc_i and wbs_stb_i) = '1' then
-- overwriting wishbone slave handshake for blocking transactions
-- to rx/tx fifos by using buffer status flags
if wbs_we_i = '1' then
tx_write_buffer <= (not tx_buffer_full) and (not wbs_ack);
wbs_ack <= (not tx_buffer_full) and (not wbs_ack);
else
rx_read_buffer <= rx_buffer_data_present and (not wbs_ack);
wbs_ack <= rx_buffer_data_present and (not wbs_ack);
end if;
end if;
wbs_dat_s2m <= rx_data_out;
-- status register access
when UART_SR_ADDR(ADDR_MSB downto 0) =>
wbs_dat_s2m(UART_SR_RX_F_FLAG) <= rx_buffer_full;
wbs_dat_s2m(UART_SR_RX_HF_FLAG) <= rx_buffer_half_full;
wbs_dat_s2m(UART_SR_RX_DP_FLAG) <= rx_buffer_data_present;
wbs_dat_s2m(UART_SR_TX_F_FLAG) <= tx_buffer_full;
wbs_dat_s2m(UART_SR_TX_HF_FLAG) <= tx_buffer_half_full;
-- baud rate register access / low byte
when UART_BAUD_LO_ADDR(ADDR_MSB downto 0) =>
if wb_reg_we = '1' then
baud_limit(7 downto 0) <= wbs_dat_m2s_i;
baud_count <= (others => '0');
end if;
wbs_dat_s2m <= baud_limit(7 downto 0);
-- baud rate register access / high byte
when UART_BAUD_HI_ADDR(ADDR_MSB downto 0) =>
if wb_reg_we = '1' then
baud_limit(15 downto 8) <= wbs_dat_m2s_i;
baud_count <= (others => '0');
end if;
wbs_dat_s2m <= baud_limit(15 downto 8);
when others => null;
end case;
if rst = '1' then
wbs_ack <= '0';
end if;
end if;
end process;
-- Xilinx (R) uart macro instances
----------------------------------
inst_uart_rx : uart_rx
port map
(
serial_in => uart_rx_si_i,
data_out => rx_data_out,
read_buffer => rx_read_buffer,
reset_buffer => rst,
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_buffer_data_present,
buffer_full => rx_buffer_full,
buffer_half_full => rx_buffer_half_full,
clk => clk
);
 
inst_uart_tx : uart_tx
port map
(
data_in => wbs_dat_m2s_i,
write_buffer => tx_write_buffer,
reset_buffer => rst,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx_so,
buffer_full => tx_buffer_full,
buffer_half_full => tx_buffer_half_full,
clk => clk
);
 
end rtl;
/wbs_uart.v
0,0 → 1,215
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: wbs_uart.v
// description: synthesizable wishbone slave uart sio module using Xilinx (R)
// macros and adding some functionality like a configurable
// baud rate and buffer level checking
// todo4user: add other uart functionality as needed, i. e. interrupt logic or
// modem control signals
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module wbs_uart (
rst,
clk,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
wbs_adr_i,
wbs_dat_m2s_i,
wbs_dat_s2m_o,
wbs_ack_o,
uart_rx_si_i,
uart_tx_so_o
);
 
input rst;
wire rst;
input clk;
wire clk;
input wbs_cyc_i;
wire wbs_cyc_i;
input wbs_stb_i;
wire wbs_stb_i;
input wbs_we_i;
wire wbs_we_i;
input[7:0] wbs_adr_i;
wire [7:0] wbs_adr_i;
input[7:0] wbs_dat_m2s_i;
wire [7:0] wbs_dat_m2s_i;
output[7:0] wbs_dat_s2m_o;
reg [7:0] wbs_dat_s2m_o;
output wbs_ack_o;
reg wbs_ack_o;
input uart_rx_si_i;
wire uart_rx_si_i;
output uart_tx_so_o;
wire uart_tx_so_o;
 
wire wb_reg_we;
 
parameter ADDR_MSB = 1;
parameter[7:0] UART_RXTX_ADDR = 8'h00;
parameter[7:0] UART_SR_ADDR = 8'h01;
parameter UART_SR_RX_F_FLAG = 0;
parameter UART_SR_RX_HF_FLAG = 1;
parameter UART_SR_RX_DP_FLAG = 2;
parameter UART_SR_TX_F_FLAG = 4;
parameter UART_SR_TX_HF_FLAG = 5;
parameter[7:0] UART_BAUD_LO_ADDR = 8'h02;
parameter[7:0] UART_BAUD_HI_ADDR = 8'h03;
reg[15:0] baud_count;
reg[15:0] baud_limit;
reg en_16_x_baud;
reg rx_read_buffer;
wire rx_buffer_full;
wire rx_buffer_half_full;
wire rx_buffer_data_present;
wire[7:0] rx_data_out;
reg tx_write_buffer;
wire tx_buffer_full;
wire tx_buffer_half_full;
// internal register write enable signal
assign wb_reg_we = wbs_cyc_i && wbs_stb_i && wbs_we_i;
always@(posedge clk) begin
// baud rate configuration:
// baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
// i. e. 9600 baud at 50 MHz system clock =>
// baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
 
// baud timer
if (baud_count == baud_limit) begin
baud_count <= 16'h0000;
en_16_x_baud <= 1'b1;
end else begin
baud_count <= baud_count + 1;
en_16_x_baud <= 1'b0;
end
rx_read_buffer <= 1'b0;
tx_write_buffer <= 1'b0;
wbs_dat_s2m_o <= 8'h00;
// registered wishbone slave handshake (default)
wbs_ack_o <= wbs_cyc_i && wbs_stb_i && (! wbs_ack_o);
case(wbs_adr_i[ADDR_MSB:0])
// receive/transmit buffer access
UART_RXTX_ADDR[ADDR_MSB:0]: begin
if (wbs_cyc_i && wbs_stb_i)
// overwriting wishbone slave handshake for blocking transactions
// to rx/tx fifos by using buffer status flags
if (wbs_we_i) begin
tx_write_buffer <= (! tx_buffer_full) && (! wbs_ack_o);
wbs_ack_o <= (! tx_buffer_full) && (! wbs_ack_o);
end else begin
rx_read_buffer <= rx_buffer_data_present && (! wbs_ack_o);
wbs_ack_o <= rx_buffer_data_present && (! wbs_ack_o);
end
wbs_dat_s2m_o <= rx_data_out;
end
// status register access
UART_SR_ADDR[ADDR_MSB:0]: begin
wbs_dat_s2m_o[UART_SR_RX_F_FLAG] <= rx_buffer_full;
wbs_dat_s2m_o[UART_SR_RX_HF_FLAG] <= rx_buffer_half_full;
wbs_dat_s2m_o[UART_SR_RX_DP_FLAG] <= rx_buffer_data_present;
wbs_dat_s2m_o[UART_SR_TX_F_FLAG] <= tx_buffer_full;
wbs_dat_s2m_o[UART_SR_TX_HF_FLAG] <= tx_buffer_half_full;
end
// baud rate register access / low byte
UART_BAUD_LO_ADDR[ADDR_MSB:0]: begin
if (wb_reg_we) begin
baud_limit[7:0] <= wbs_dat_m2s_i;
baud_count <= 16'h0000;
end
wbs_dat_s2m_o <= baud_limit[7:0];
end
// baud rate register access / high byte
UART_BAUD_HI_ADDR[ADDR_MSB:0]: begin
if (wb_reg_we) begin
baud_limit[15:8] <= wbs_dat_m2s_i;
baud_count <= 16'h0000;
end
wbs_dat_s2m_o <= baud_limit[15:8];
end
default: ;
endcase
if (rst) begin
wbs_ack_o <= 1'b0;
end
end
// Xilinx (R) uart macro instances
//////////////////////////////////
uart_rx inst_uart_rx (
.serial_in(uart_rx_si_i),
.data_out(rx_data_out),
.read_buffer(rx_read_buffer),
.reset_buffer(rst),
.en_16_x_baud(en_16_x_baud),
.buffer_data_present(rx_buffer_data_present),
.buffer_full(rx_buffer_full),
.buffer_half_full(rx_buffer_half_full),
.clk(clk)
);
uart_tx inst_uart_tx (
.data_in(wbs_dat_m2s_i),
.write_buffer(tx_write_buffer),
.reset_buffer(rst),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx_so_o),
.buffer_full(tx_buffer_full),
.buffer_half_full(tx_buffer_half_full),
.clk(clk)
);
 
endmodule
/picoblaze_wb_uart.vhd
0,0 → 1,226
--------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: picoblaze_wb_uart.vhd
-- description: synthesizable PicoBlaze (TM) uart example using wishbone
-- todo4user: add other modules as needed
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity picoblaze_wb_uart is
port
(
p_rst_n_i : in std_logic;
p_clk_i : in std_logic;
p_uart_rx_si_i : in std_logic;
p_uart_tx_so_o : out std_logic
);
end picoblaze_wb_uart;
 
 
architecture rtl of picoblaze_wb_uart is
 
component kcpsm3 is
port
(
address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic
);
end component;
 
component pbwbuart is
port
(
address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic
);
end component;
 
component wbm_picoblaze is
port
(
rst : in std_logic;
clk : in std_logic;
wbm_cyc_o : out std_logic;
wbm_stb_o : out std_logic;
wbm_we_o : out std_logic;
wbm_adr_o : out std_logic_vector(7 downto 0);
wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
wbm_ack_i : in std_logic;
pb_port_id_i : in std_logic_vector(7 downto 0);
pb_write_strobe_i : in std_logic;
pb_out_port_i : in std_logic_vector(7 downto 0);
pb_read_strobe_i : in std_logic;
pb_in_port_o : out std_logic_vector(7 downto 0)
);
end component;
 
component wbs_uart is
port
(
rst : in std_logic;
clk : in std_logic;
wbs_cyc_i : in std_logic;
wbs_stb_i : in std_logic;
wbs_we_i : in std_logic;
wbs_adr_i : in std_logic_vector(7 downto 0);
wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
wbs_ack_o : out std_logic;
uart_rx_si_i : in std_logic;
uart_tx_so_o : out std_logic
);
end component;
 
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal wb_cyc : std_logic := '0';
signal wb_stb : std_logic := '0';
signal wb_we : std_logic := '0';
signal wb_adr : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
signal wb_ack : std_logic := '0';
signal pb_write_strobe : std_logic := '0';
signal pb_read_strobe : std_logic := '0';
signal pb_port_id : std_logic_vector(7 downto 0) := (others => '0');
signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
signal pb_out_port : std_logic_vector(7 downto 0) := (others => '0');
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal address : std_logic_vector(9 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
signal interrupt_ack : std_logic := '0';
begin
 
-- reset synchronisation
process(clk)
begin
rst <= not p_rst_n_i;
end process;
clk <= p_clk_i;
-- module instances
-------------------
inst_kcpsm3 : kcpsm3
port map
(
address => address,
instruction => instruction,
port_id => pb_port_id,
write_strobe => pb_write_strobe,
out_port => pb_out_port,
read_strobe => pb_read_strobe,
in_port => pb_in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => rst,
clk => clk
);
 
inst_pbwbuart : pbwbuart
port map
(
address => address,
instruction => instruction,
clk => clk
);
 
inst_wbm_picoblaze : wbm_picoblaze
port map
(
rst => rst,
clk => clk,
wbm_cyc_o => wb_cyc,
wbm_stb_o => wb_stb,
wbm_we_o => wb_we,
wbm_adr_o => wb_adr,
wbm_dat_m2s_o => wb_dat_m2s,
wbm_dat_s2m_i => wb_dat_s2m,
wbm_ack_i => wb_ack,
pb_port_id_i => pb_port_id,
pb_write_strobe_i => pb_write_strobe,
pb_out_port_i => pb_out_port,
pb_read_strobe_i => pb_read_strobe,
pb_in_port_o => pb_in_port
);
 
inst_wbs_uart : wbs_uart
port map
(
rst => rst,
clk => clk,
wbs_cyc_i => wb_cyc,
wbs_stb_i => wb_stb,
wbs_we_i => wb_we,
wbs_adr_i => wb_adr,
wbs_dat_m2s_i => wb_dat_m2s,
wbs_dat_s2m_o => wb_dat_s2m,
wbs_ack_o => wb_ack,
uart_rx_si_i => p_uart_rx_si_i,
uart_tx_so_o => p_uart_tx_so_o
);
end rtl;

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