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/tags/ini_rel/asm/pbwbgpio.psm
0,0 → 1,146
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; This sourcecode is released under BSD license.
;; Please see http://www.opensource.org/licenses/bsd-license.php for details!
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
;; All rights reserved.
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright notice,
;; this list of conditions and the following disclaimer in the documentation
;; and/or other materials provided with the distribution.
;; * Neither the name of the author nor the names of his contributors may be
;; used to endorse or promote products derived from this software without
;; specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;; POSSIBILITY OF SUCH DAMAGE.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; filename: pbwbgpio.psm
;; description: gpio example, demonstrating access to wishbone peripherals
;; todo4user: modify main program and gpio_init code as needed
;; version: 0.0.0
;; changelog: - 0.0.0, initial release
;; - ...
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
; IMPORTANT NOTICE!
; be carefull, if using interrupts. wishbone cycles must be atomar, as any
; other processor local bus cycles are normally be. interrupting wishbone
; access may cause a crash of external wishbone master fsm, especially, if
; program flow through isr leads to another wishbone cycle!
 
 
NAMEREG sF , wb_addr
NAMEREG sE , wb_data ; also used as tmp-reg for status polling
 
CONSTANT WB_ACK_FLAG , 01
 
CONSTANT GPIO_IO_ADDR , 00
CONSTANT GPIO_OE_ADDR , 01
 
 
ADDRESS 000
 
; main entry point
DISABLE INTERRUPT
 
CALL gpio_init
 
; mirroring upper nibble gpio inputs
; to lower nibble gpio outputs
LOAD wb_addr , GPIO_IO_ADDR
mainloop:
CALL wb_rd
NAMEREG s0 , i
LOAD i , 04
for_i_in_4_downto_1_loop: ; bitshifting (wb_data>>4)
SR0 wb_data
SUB i , 01
JUMP NZ , for_i_in_4_downto_1_loop
CALL wb_wr
JUMP mainloop
 
gpio_init:
; setting all outputs low
LOAD wb_addr , GPIO_IO_ADDR
LOAD wb_data , 00
CALL wb_wr
; configuring lower gpio nibble as output
LOAD wb_addr , GPIO_OE_ADDR
LOAD wb_data , 0F
CALL wb_wr
RETURN
 
; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
; is a supporting subroutine, which should not be called directly
;
; transfer principle wishbone write:
; 1. OUTPUT cycle to set up wishbone address, data and control signals from
; PORT_ID, OUT_PORT and WRITE_STROBE
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
; => at least one OUTPUT and one INPUT cycle for a write
;
; transfer principle wishbone read:
; 1. INPUT cycle to set up wishbone address and control signals from PORT_ID
; and READ_STROBE
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
; 3. the very next INPUT cycle after acknowledgement contains valid wishbone
; data from IN_PORT
; => at least three INPUT cycles for a read
;
; calling examples:
;
; wishbone write code =>
;
; LOAD wb_addr , <user address> ; setting up address
; LOAD wb_data , <user data> ; setting up data
; CALL wb_wr ; starting wishbone write cycle
; <next user instruction> ; wishbone cycle finished
;
; wishbone read code =>
;
; LOAD wb_addr , <user address> ; setting up address
; CALL wb_rd ; starting wishbone read cycle
; <next user instruction> ; wishbone cycle finished, wb_data is updated now
 
; wishbone write access
wb_wr:
OUTPUT wb_data , (wb_addr)
CALL wb_wait_on_ack
RETURN
 
; wishbone read access
wb_rd:
CALL wb_wait_on_ack
INPUT wb_data , (wb_addr)
RETURN
 
; waiting on wishbone cycle to complete
wb_wait_on_ack:
INPUT wb_data , (wb_addr)
TEST wb_data , WB_ACK_FLAG
JUMP Z , wb_wait_on_ack
RETURN
 
; interrupt handling template, if needed
isr:
RETURNI DISABLE
ADDRESS 3FF
JUMP isr
/tags/ini_rel/asm/PBWBGPIO.VHD
0,0 → 1,274
--
-- Definition of a single port ROM for KCPSM3 program defined by pbwbgpio.psm
--
-- Generated by KCPSM3 Assembler 03Jan2010-20:03:33.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity pbwbgpio is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end pbwbgpio;
--
architecture low_level_definition of pbwbgpio is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "00110E0F0F0100110E000F00400300115405C0010E0E000400140F00000AC000";
attribute INIT_01 of ram_1024_x_18 : label is "00000000000000008000A00050172E015EF0A0005EF00017A0000017DEF0A000";
attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "401B000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000000ED23BAC30FD8CF";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "C000000000000000000000000000000000000000000000000000000000000000";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"00110E0F0F0100110E000F00400300115405C0010E0E000400140F00000AC000",
INIT_01 => X"00000000000000008000A00050172E015EF0A0005EF00017A0000017DEF0A000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"401B000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000ED23BAC30FD8CF",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE pbwbgpio.vhd
--
------------------------------------------------------------------------------------
/tags/ini_rel/asm/PBWBGPIO.V
0,0 → 1,262
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: v1.30
// \ \ Application : KCPSM3
// / / Filename: pbwbgpio.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//Command: kcpsm3 pbwbgpio.psm
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
//Design Name: pbwbgpio
//Generated 03Jan2010-20:03:33.
//Purpose:
// pbwbgpio verilog program definition.
//
//Reference:
// PicoBlaze 8-bit Embedded Microcontroller User Guide
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module pbwbgpio (address, instruction, clk);
input [9:0] address;
input clk;
output [17:0] instruction;
RAMB16_S18 ram_1024_x_18(
.DI (16'h0000),
.DIP (2'b00),
.EN (1'b1),
.WE (1'b0),
.SSR (1'b0),
.CLK (clk),
.ADDR (address),
.DO (instruction[15:0]),
.DOP (instruction[17:16]))
/*synthesis
init_00 = "00110E0F0F0100110E000F00400300115405C0010E0E000400140F00000AC000"
init_01 = "00000000000000008000A00050172E015EF0A0005EF00017A0000017DEF0A000"
init_02 = "0000000000000000000000000000000000000000000000000000000000000000"
init_03 = "0000000000000000000000000000000000000000000000000000000000000000"
init_04 = "0000000000000000000000000000000000000000000000000000000000000000"
init_05 = "0000000000000000000000000000000000000000000000000000000000000000"
init_06 = "0000000000000000000000000000000000000000000000000000000000000000"
init_07 = "0000000000000000000000000000000000000000000000000000000000000000"
init_08 = "0000000000000000000000000000000000000000000000000000000000000000"
init_09 = "0000000000000000000000000000000000000000000000000000000000000000"
init_0A = "0000000000000000000000000000000000000000000000000000000000000000"
init_0B = "0000000000000000000000000000000000000000000000000000000000000000"
init_0C = "0000000000000000000000000000000000000000000000000000000000000000"
init_0D = "0000000000000000000000000000000000000000000000000000000000000000"
init_0E = "0000000000000000000000000000000000000000000000000000000000000000"
init_0F = "0000000000000000000000000000000000000000000000000000000000000000"
init_10 = "0000000000000000000000000000000000000000000000000000000000000000"
init_11 = "0000000000000000000000000000000000000000000000000000000000000000"
init_12 = "0000000000000000000000000000000000000000000000000000000000000000"
init_13 = "0000000000000000000000000000000000000000000000000000000000000000"
init_14 = "0000000000000000000000000000000000000000000000000000000000000000"
init_15 = "0000000000000000000000000000000000000000000000000000000000000000"
init_16 = "0000000000000000000000000000000000000000000000000000000000000000"
init_17 = "0000000000000000000000000000000000000000000000000000000000000000"
init_18 = "0000000000000000000000000000000000000000000000000000000000000000"
init_19 = "0000000000000000000000000000000000000000000000000000000000000000"
init_1A = "0000000000000000000000000000000000000000000000000000000000000000"
init_1B = "0000000000000000000000000000000000000000000000000000000000000000"
init_1C = "0000000000000000000000000000000000000000000000000000000000000000"
init_1D = "0000000000000000000000000000000000000000000000000000000000000000"
init_1E = "0000000000000000000000000000000000000000000000000000000000000000"
init_1F = "0000000000000000000000000000000000000000000000000000000000000000"
init_20 = "0000000000000000000000000000000000000000000000000000000000000000"
init_21 = "0000000000000000000000000000000000000000000000000000000000000000"
init_22 = "0000000000000000000000000000000000000000000000000000000000000000"
init_23 = "0000000000000000000000000000000000000000000000000000000000000000"
init_24 = "0000000000000000000000000000000000000000000000000000000000000000"
init_25 = "0000000000000000000000000000000000000000000000000000000000000000"
init_26 = "0000000000000000000000000000000000000000000000000000000000000000"
init_27 = "0000000000000000000000000000000000000000000000000000000000000000"
init_28 = "0000000000000000000000000000000000000000000000000000000000000000"
init_29 = "0000000000000000000000000000000000000000000000000000000000000000"
init_2A = "0000000000000000000000000000000000000000000000000000000000000000"
init_2B = "0000000000000000000000000000000000000000000000000000000000000000"
init_2C = "0000000000000000000000000000000000000000000000000000000000000000"
init_2D = "0000000000000000000000000000000000000000000000000000000000000000"
init_2E = "0000000000000000000000000000000000000000000000000000000000000000"
init_2F = "0000000000000000000000000000000000000000000000000000000000000000"
init_30 = "0000000000000000000000000000000000000000000000000000000000000000"
init_31 = "0000000000000000000000000000000000000000000000000000000000000000"
init_32 = "0000000000000000000000000000000000000000000000000000000000000000"
init_33 = "0000000000000000000000000000000000000000000000000000000000000000"
init_34 = "0000000000000000000000000000000000000000000000000000000000000000"
init_35 = "0000000000000000000000000000000000000000000000000000000000000000"
init_36 = "0000000000000000000000000000000000000000000000000000000000000000"
init_37 = "0000000000000000000000000000000000000000000000000000000000000000"
init_38 = "0000000000000000000000000000000000000000000000000000000000000000"
init_39 = "0000000000000000000000000000000000000000000000000000000000000000"
init_3A = "0000000000000000000000000000000000000000000000000000000000000000"
init_3B = "0000000000000000000000000000000000000000000000000000000000000000"
init_3C = "0000000000000000000000000000000000000000000000000000000000000000"
init_3D = "0000000000000000000000000000000000000000000000000000000000000000"
init_3E = "0000000000000000000000000000000000000000000000000000000000000000"
init_3F = "401B000000000000000000000000000000000000000000000000000000000000"
initp_00 = "00000000000000000000000000000000000000000000000000ED23BAC30FD8CF"
initp_01 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_02 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_03 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_04 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_05 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_06 = "0000000000000000000000000000000000000000000000000000000000000000"
initp_07 = "C000000000000000000000000000000000000000000000000000000000000000" */;
// synthesis translate_off
// Attributes for Simulation
defparam ram_1024_x_18.INIT_00 = 256'h00110E0F0F0100110E000F00400300115405C0010E0E000400140F00000AC000;
defparam ram_1024_x_18.INIT_01 = 256'h00000000000000008000A00050172E015EF0A0005EF00017A0000017DEF0A000;
defparam ram_1024_x_18.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INIT_3F = 256'h401B000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_00 = 256'h00000000000000000000000000000000000000000000000000ED23BAC30FD8CF;
defparam ram_1024_x_18.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_1024_x_18.INITP_07 = 256'hC000000000000000000000000000000000000000000000000000000000000000;
// synthesis translate_on
// Attributes for XST (Synplicity attributes are in-line)
// synthesis attribute INIT_00 of ram_1024_x_18 is "00110E0F0F0100110E000F00400300115405C0010E0E000400140F00000AC000"
// synthesis attribute INIT_01 of ram_1024_x_18 is "00000000000000008000A00050172E015EF0A0005EF00017A0000017DEF0A000"
// synthesis attribute INIT_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_07 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_08 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_09 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_10 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_11 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_12 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_13 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_14 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_15 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_16 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_17 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_18 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_19 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_1F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_20 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_21 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_22 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_23 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_24 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_25 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_26 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_27 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_28 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_29 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_2F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_30 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_31 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_32 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_33 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_34 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_35 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_36 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_37 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_38 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_39 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_3F of ram_1024_x_18 is "401B000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_00 of ram_1024_x_18 is "00000000000000000000000000000000000000000000000000ED23BAC30FD8CF"
// synthesis attribute INITP_01 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INITP_07 of ram_1024_x_18 is "C000000000000000000000000000000000000000000000000000000000000000"
endmodule
// END OF FILE pbwbgpio.v
/tags/ini_rel/tools/userDefineLang.xml
0,0 → 1,77
<!------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: userDefineLang.xml
-- description: kcpsm3 assembler syntax highlighting for notepad++ programming
-- editor (http://notepad-plus.sourceforge.net)
-- todo4user: copy to notepad++ installation directory
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
------------------------------------------------------------------------------->
<NotepadPlus>
<UserLang name="KCPSM3" ext="psm">
<Settings>
<Global caseIgnored="no" />
<TreatAsSymbol comment="no" commentLine="yes" />
<Prefix words1="no" words2="no" words3="yes" words4="no" />
</Settings>
<KeywordLists>
<Keywords name="Delimiters">000000</Keywords>
<Keywords name="Folder+"></Keywords>
<Keywords name="Folder-"></Keywords>
<Keywords name="Operators"></Keywords>
<Keywords name="Comment">1 2 0;</Keywords>
<Keywords name="Words1">C NC Z NZ ADD ADDCY AND CALL COMPARE DISABLE ENABLE FETCH INPUT INTERRUPT JUMP LOAD OR OUTPUT RETURN RETURNI RL RR SL0 SL1 SLA SLX SR0 SR1 SRA SRX STORE SUB SUBCY TEST XOR</Keywords>
<Keywords name="Words2">ADDRESS NAMEREG CONSTANT</Keywords>
<Keywords name="Words3">s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 sA sB sC sD sE sF</Keywords>
<Keywords name="Words4"></Keywords>
</KeywordLists>
<Styles>
<WordsStyle name="DEFAULT" styleID="11" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="FOLDEROPEN" styleID="12" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="FOLDERCLOSE" styleID="13" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="KEYWORD1" styleID="5" fgColor="0000FF" bgColor="FFFFFF" fontName="" fontStyle="1" />
<WordsStyle name="KEYWORD2" styleID="6" fgColor="00FF00" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="KEYWORD3" styleID="7" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="1" />
<WordsStyle name="KEYWORD4" styleID="8" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="COMMENT" styleID="1" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="COMMENT LINE" styleID="2" fgColor="808080" bgColor="FFFFFF" fontName="" fontStyle="2" />
<WordsStyle name="NUMBER" styleID="4" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="OPERATOR" styleID="10" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="DELIMINER1" styleID="14" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="DELIMINER2" styleID="15" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="DELIMINER3" styleID="16" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
</Styles>
</UserLang>
</NotepadPlus>
/tags/ini_rel/rtl/wbm_picoblaze.v
0,0 → 1,166
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: wbm_picoblaze.v
// description: synthesizable wishbone master adapter for PicoBlaze (TM),
// working together with "wb_wr" and "wb_rd" assembler subroutines
// todo4user: module should not be changed!
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module wbm_picoblaze (
rst,
clk,
wbm_cyc_o,
wbm_stb_o,
wbm_we_o,
wbm_adr_o,
wbm_dat_m2s_o,
wbm_dat_s2m_i,
wbm_ack_i,
pb_port_id_i,
pb_write_strobe_i,
pb_out_port_i,
pb_read_strobe_i,
pb_in_port_o
);
 
input rst;
wire rst;
input clk;
wire clk;
output wbm_cyc_o;
reg wbm_cyc_o;
output wbm_stb_o;
reg wbm_stb_o;
output wbm_we_o;
reg wbm_we_o;
output[7:0] wbm_adr_o;
reg [7:0] wbm_adr_o;
output[7:0] wbm_dat_m2s_o;
reg [7:0] wbm_dat_m2s_o;
input[7:0] wbm_dat_s2m_i;
wire [7:0] wbm_dat_s2m_i;
input wbm_ack_i;
wire wbm_ack_i;
input[7:0] pb_port_id_i;
wire [7:0] pb_port_id_i;
input pb_write_strobe_i;
wire pb_write_strobe_i;
input[7:0] pb_out_port_i;
wire [7:0] pb_out_port_i;
input pb_read_strobe_i;
wire pb_read_strobe_i;
output[7:0] pb_in_port_o;
reg [7:0] pb_in_port_o;
reg[7:0] wb_buffer;
parameter[7:0] WB_ACK_FLAG = 8'h01;
 
parameter[1:0]
S_IDLE = 2'b00,
S_WAIT_ON_WB_ACK = 2'b01,
S_SOFTWARE_HANDSHAKE = 2'b10,
S_SOFTWARE_READ = 2'b11
;
reg[1:0] state;
always@(wbm_stb_o) wbm_cyc_o = wbm_stb_o;
 
always@(posedge clk) begin
case(state)
S_IDLE:
// setting up wishbone address, data and control signals from
// PicoBlaze (TM) signals
if (pb_write_strobe_i) begin
wbm_stb_o <= 1'b1;
wbm_we_o <= 1'b1;
wbm_adr_o <= pb_port_id_i;
wbm_dat_m2s_o <= pb_out_port_i;
state <= S_WAIT_ON_WB_ACK;
end else if (pb_read_strobe_i) begin
wbm_stb_o <= 1'b1;
wbm_we_o <= 1'b0;
wbm_adr_o <= pb_port_id_i;
state <= S_WAIT_ON_WB_ACK;
end
S_WAIT_ON_WB_ACK:
// waiting on slave peripheral to complete wishbone transfer cycle
if (wbm_ack_i) begin
wbm_stb_o <= 1'b0;
wb_buffer <= wbm_dat_s2m_i;
pb_in_port_o <= WB_ACK_FLAG;
state <= S_SOFTWARE_HANDSHAKE;
end
S_SOFTWARE_HANDSHAKE:
// software recognition of wishbone handshake
if (pb_read_strobe_i) begin
// transfer complete for a write access
if (wbm_we_o) begin
pb_in_port_o <= 8'h00;
state <= S_IDLE;
// presenting valid wishbone data to PicoBlaze (TM) port in read
// access
end else begin
pb_in_port_o <= wb_buffer;
state <= S_SOFTWARE_READ;
end
end
S_SOFTWARE_READ:
// transfer complete for a read access after software recognition of
// wishbone data
if (pb_read_strobe_i) begin
pb_in_port_o <= 8'h00;
state <= S_IDLE;
end
default: ;
endcase
if (rst) begin
wbm_stb_o <= 1'b0;
pb_in_port_o <= 8'h00;
state <= S_IDLE;
end
end
 
endmodule
/tags/ini_rel/rtl/picoblaze_wb_gpio.v
0,0 → 1,168
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: picoblaze_wb_gpio.v
// description: synthesizable PicoBlaze (TM) general purpose i/o example using
// wishbone
// todo4user: add other modules as needed
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module picoblaze_wb_gpio (
p_rst_i,
p_clk_i,
p_gpio_io
);
 
input p_rst_i;
wire p_rst_i;
input p_clk_i;
wire p_clk_i;
inout[7:0] p_gpio_io;
wire [7:0] p_gpio_io;
 
reg rst;
wire clk;
wire wb_cyc;
wire wb_stb;
wire wb_we;
wire[7:0] wb_adr;
wire[7:0] wb_dat_m2s;
wire[7:0] wb_dat_s2m;
wire wb_ack;
wire pb_write_strobe;
wire pb_read_strobe;
wire[7:0] pb_port_id;
wire[7:0] pb_in_port;
wire[7:0] pb_out_port;
wire[17:0] instruction;
wire[9:0] address;
wire interrupt;
wire interrupt_ack;
wire[7:0] gpio_in;
wire[7:0] gpio_out;
wire[7:0] gpio_oe;
reg [7:0] gpio;
parameter IS_INPUT = 1'b0;
parameter IS_OUTPUT = ! IS_INPUT;
integer i;
// reset synchronisation
always@(clk) begin
rst <= p_rst_i;
end
assign clk = p_clk_i;
// module instances
///////////////////
kcpsm3 inst_kcpsm3 (
.address(address),
.instruction(instruction),
.port_id(pb_port_id),
.write_strobe(pb_write_strobe),
.out_port(pb_out_port),
.read_strobe(pb_read_strobe),
.in_port(pb_in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(rst),
.clk(clk)
);
 
pbwbgpio inst_pbwbgpio (
.address(address),
.instruction(instruction),
.clk(clk)
);
 
wbm_picoblaze inst_wbm_picoblaze (
.rst(rst),
.clk(clk),
.wbm_cyc_o(wb_cyc),
.wbm_stb_o(wb_stb),
.wbm_we_o(wb_we),
.wbm_adr_o(wb_adr),
.wbm_dat_m2s_o(wb_dat_m2s),
.wbm_dat_s2m_i(wb_dat_s2m),
.wbm_ack_i(wb_ack),
.pb_port_id_i(pb_port_id),
.pb_write_strobe_i(pb_write_strobe),
.pb_out_port_i(pb_out_port),
.pb_read_strobe_i(pb_read_strobe),
.pb_in_port_o(pb_in_port)
);
 
wbs_gpio inst_wbs_gpio (
.rst(rst),
.clk(clk),
.wbs_cyc_i(wb_cyc),
.wbs_stb_i(wb_stb),
.wbs_we_i(wb_we),
.wbs_adr_i(wb_adr),
.wbs_dat_m2s_i(wb_dat_m2s),
.wbs_dat_s2m_o(wb_dat_s2m),
.wbs_ack_o(wb_ack),
.gpio_in_i(gpio_in),
.gpio_out_o(gpio_out),
.gpio_oe_o(gpio_oe)
);
// i/o buffer generation
assign gpio_in = p_gpio_io;
always@(gpio_oe or gpio_out) begin
for (i = 0; i <= 7; i = i + 1) begin
if (gpio_oe[i] == IS_OUTPUT)
gpio[i] = gpio_out[i];
else
gpio[i] = 1'bZ;
end
end
assign p_gpio_io = gpio;
endmodule
/tags/ini_rel/rtl/wbs_gpio.vhd
0,0 → 1,132
--------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: wbs_gpio.vhd
-- description: synthesizable wishbone slave general purpose i/o module
-- todo4user: add more i/o ports as needed
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity wbs_gpio is
port
(
rst : in std_logic;
clk : in std_logic;
wbs_cyc_i : in std_logic;
wbs_stb_i : in std_logic;
wbs_we_i : in std_logic;
wbs_adr_i : in std_logic_vector(7 downto 0);
wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
wbs_ack_o : out std_logic;
gpio_in_i : in std_logic_vector(7 downto 0);
gpio_out_o : out std_logic_vector(7 downto 0);
gpio_oe_o : out std_logic_vector(7 downto 0)
);
end wbs_gpio;
 
 
architecture rtl of wbs_gpio is
 
signal wbs_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
signal wbs_ack : std_logic := '0';
signal gpio_out : std_logic_vector(7 downto 0) := (others => '0');
signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0');
signal wb_reg_we : std_logic := '0';
signal gpio_in : std_logic_vector(7 downto 0) := (others => '0');
constant IS_INPUT : std_logic := '0';
constant IS_OUTPUT : std_logic := not IS_INPUT;
constant ADDR_MSB : natural := 0;
constant GPIO_IO_ADDR : std_logic_vector(7 downto 0) := x"00";
constant GPIO_OE_ADDR : std_logic_vector(7 downto 0) := x"01";
begin
 
wbs_dat_s2m_o <= wbs_dat_s2m;
wbs_ack_o <= wbs_ack;
gpio_out_o <= gpio_out;
gpio_oe_o <= gpio_oe;
-- internal register write enable signal
wb_reg_we <= wbs_cyc_i and wbs_stb_i and wbs_we_i;
process(clk)
begin
if clk'event and clk = '1' then
gpio_in <= gpio_in_i;
wbs_dat_s2m <= (others => '0');
-- registered wishbone slave handshake
wbs_ack <= wbs_cyc_i and wbs_stb_i and (not wbs_ack);
case wbs_adr_i(ADDR_MSB downto 0) is
-- i/o register access
when GPIO_IO_ADDR(ADDR_MSB downto 0) =>
if wb_reg_we = '1' then
gpio_out <= wbs_dat_m2s_i;
end if;
wbs_dat_s2m <= gpio_in;
-- output enable register access
when GPIO_OE_ADDR(ADDR_MSB downto 0) =>
if wb_reg_we = '1' then
gpio_oe <= wbs_dat_m2s_i;
end if;
wbs_dat_s2m <= gpio_oe;
when others => null;
end case;
if rst = '1' then
wbs_ack <= '0';
gpio_oe <= (others => IS_INPUT);
end if;
end if;
end process;
 
end rtl;
/tags/ini_rel/rtl/wbm_picoblaze.vhd
0,0 → 1,167
--------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: wbm_picoblaze.vhd
-- description: synthesizable wishbone master adapter for PicoBlaze (TM),
-- working together with "wb_wr" and "wb_rd" assembler subroutines
-- todo4user: module should not be changed!
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity wbm_picoblaze is
port
(
rst : in std_logic;
clk : in std_logic;
wbm_cyc_o : out std_logic;
wbm_stb_o : out std_logic;
wbm_we_o : out std_logic;
wbm_adr_o : out std_logic_vector(7 downto 0);
wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
wbm_ack_i : in std_logic;
pb_port_id_i : in std_logic_vector(7 downto 0);
pb_write_strobe_i : in std_logic;
pb_out_port_i : in std_logic_vector(7 downto 0);
pb_read_strobe_i : in std_logic;
pb_in_port_o : out std_logic_vector(7 downto 0)
);
end wbm_picoblaze;
 
 
architecture rtl of wbm_picoblaze is
 
signal wbm_cyc : std_logic := '0';
signal wbm_stb : std_logic := '0';
signal wbm_we : std_logic := '0';
signal wbm_adr : std_logic_vector(7 downto 0) := (others => '0');
signal wbm_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
signal wb_buffer : std_logic_vector(7 downto 0) := (others => '0');
constant WB_ACK_FLAG : std_logic_vector(7 downto 0) := x"01";
type t_states is
(
S_IDLE,
S_WAIT_ON_WB_ACK,
S_SOFTWARE_HANDSHAKE,
S_SOFTWARE_READ
);
signal state : t_states := S_IDLE;
 
begin
 
wbm_cyc_o <= wbm_cyc;
wbm_stb_o <= wbm_stb;
wbm_we_o <= wbm_we;
wbm_adr_o <= wbm_adr;
wbm_dat_m2s_o <= wbm_dat_m2s;
pb_in_port_o <= pb_in_port;
wbm_cyc <= wbm_stb;
process(clk)
begin
if clk'event and clk = '1' then
case state is
when S_IDLE =>
-- setting up wishbone address, data and control signals from
-- PicoBlaze (TM) signals
if pb_write_strobe_i = '1' then
wbm_stb <= '1';
wbm_we <= '1';
wbm_adr <= pb_port_id_i;
wbm_dat_m2s <= pb_out_port_i;
state <= S_WAIT_ON_WB_ACK;
elsif pb_read_strobe_i = '1' then
wbm_stb <= '1';
wbm_we <= '0';
wbm_adr <= pb_port_id_i;
state <= S_WAIT_ON_WB_ACK;
end if;
when S_WAIT_ON_WB_ACK =>
-- waiting on slave peripheral to complete wishbone transfer cycle
if wbm_ack_i = '1' then
wbm_stb <= '0';
wb_buffer <= wbm_dat_s2m_i;
pb_in_port <= WB_ACK_FLAG;
state <= S_SOFTWARE_HANDSHAKE;
end if;
when S_SOFTWARE_HANDSHAKE =>
-- software recognition of wishbone handshake
if pb_read_strobe_i = '1' then
-- transfer complete for a write access
if wbm_we = '1' then
pb_in_port <= (others => '0');
state <= S_IDLE;
-- presenting valid wishbone data to PicoBlaze (TM) port in read
-- access
else
pb_in_port <= wb_buffer;
state <= S_SOFTWARE_READ;
end if;
end if;
when S_SOFTWARE_READ =>
-- transfer complete for a read access after software recognition of
-- wishbone data
if pb_read_strobe_i = '1' then
pb_in_port <= (others => '0');
state <= S_IDLE;
end if;
when others => null;
end case;
if rst = '1' then
wbm_stb <= '0';
pb_in_port <= (others => '0');
state <= S_IDLE;
end if;
end if;
end process;
 
end rtl;
/tags/ini_rel/rtl/wbs_gpio.v
0,0 → 1,132
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: wbs_gpio.v
// description: synthesizable wishbone slave general purpose i/o module
// todo4user: add more i/o ports as needed
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module wbs_gpio (
rst,
clk,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
wbs_adr_i,
wbs_dat_m2s_i,
wbs_dat_s2m_o,
wbs_ack_o,
gpio_in_i,
gpio_out_o,
gpio_oe_o
);
 
input rst;
wire rst;
input clk;
wire clk;
input wbs_cyc_i;
wire wbs_cyc_i;
input wbs_stb_i;
wire wbs_stb_i;
input wbs_we_i;
wire wbs_we_i;
input[7:0] wbs_adr_i;
wire [7:0] wbs_adr_i;
input[7:0] wbs_dat_m2s_i;
wire [7:0] wbs_dat_m2s_i;
output[7:0] wbs_dat_s2m_o;
reg [7:0] wbs_dat_s2m_o;
output wbs_ack_o;
reg wbs_ack_o;
input[7:0] gpio_in_i;
wire [7:0] gpio_in_i;
output[7:0] gpio_out_o;
reg [7:0] gpio_out_o;
output[7:0] gpio_oe_o;
reg [7:0] gpio_oe_o;
 
wire wb_reg_we;
reg[7:0] gpio_in;
parameter IS_INPUT = 1'b0;
parameter IS_OUTPUT = ! IS_INPUT;
 
parameter ADDR_MSB = 0;
parameter[7:0] GPIO_IO_ADDR = 8'h00;
parameter[7:0] GPIO_OE_ADDR = 8'h01;
// internal register write enable signal
assign wb_reg_we = wbs_cyc_i && wbs_stb_i && wbs_we_i;
always@(posedge clk) begin
gpio_in <= gpio_in_i;
wbs_dat_s2m_o <= 8'h00;
// registered wishbone slave handshake
wbs_ack_o <= wbs_cyc_i && wbs_stb_i && (! wbs_ack_o);
case(wbs_adr_i[ADDR_MSB:0])
// i/o register access
GPIO_IO_ADDR[ADDR_MSB:0]: begin
if (wb_reg_we)
gpio_out_o <= wbs_dat_m2s_i;
wbs_dat_s2m_o <= gpio_in;
end
// output enable register access
GPIO_OE_ADDR[ADDR_MSB:0]: begin
if (wb_reg_we)
gpio_oe_o <= wbs_dat_m2s_i;
wbs_dat_s2m_o <= gpio_oe_o;
end
default: ;
endcase
if (rst) begin
wbs_ack_o <= 1'b0;
gpio_oe_o <= {8{IS_INPUT}};
end
end
 
endmodule
/tags/ini_rel/rtl/picoblaze_wb_gpio.vhd
0,0 → 1,248
--------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: picoblaze_wb_gpio.vhd
-- description: synthesizable PicoBlaze (TM) general purpose i/o example using
-- wishbone
-- todo4user: add other modules as needed
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity picoblaze_wb_gpio is
port
(
p_rst_i : in std_logic;
p_clk_i : in std_logic;
p_gpio_io : inout std_logic_vector(7 downto 0)
);
end picoblaze_wb_gpio;
 
 
architecture rtl of picoblaze_wb_gpio is
 
component kcpsm3 is
port
(
address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic
);
end component;
 
component pbwbgpio is
port
(
address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic
);
end component;
 
component wbm_picoblaze is
port
(
rst : in std_logic;
clk : in std_logic;
wbm_cyc_o : out std_logic;
wbm_stb_o : out std_logic;
wbm_we_o : out std_logic;
wbm_adr_o : out std_logic_vector(7 downto 0);
wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
wbm_ack_i : in std_logic;
pb_port_id_i : in std_logic_vector(7 downto 0);
pb_write_strobe_i : in std_logic;
pb_out_port_i : in std_logic_vector(7 downto 0);
pb_read_strobe_i : in std_logic;
pb_in_port_o : out std_logic_vector(7 downto 0)
);
end component;
 
component wbs_gpio is
port
(
rst : in std_logic;
clk : in std_logic;
wbs_cyc_i : in std_logic;
wbs_stb_i : in std_logic;
wbs_we_i : in std_logic;
wbs_adr_i : in std_logic_vector(7 downto 0);
wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
wbs_ack_o : out std_logic;
gpio_in_i : in std_logic_vector(7 downto 0);
gpio_out_o : out std_logic_vector(7 downto 0);
gpio_oe_o : out std_logic_vector(7 downto 0)
);
end component;
 
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal wb_cyc : std_logic := '0';
signal wb_stb : std_logic := '0';
signal wb_we : std_logic := '0';
signal wb_adr : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
signal wb_ack : std_logic := '0';
signal pb_write_strobe : std_logic := '0';
signal pb_read_strobe : std_logic := '0';
signal pb_port_id : std_logic_vector(7 downto 0) := (others => '0');
signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
signal pb_out_port : std_logic_vector(7 downto 0) := (others => '0');
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal address : std_logic_vector(9 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
signal interrupt_ack : std_logic := '0';
signal gpio_in : std_logic_vector(7 downto 0) := (others => '0');
signal gpio_out : std_logic_vector(7 downto 0) := (others => '0');
signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0');
constant IS_INPUT : std_logic := '0';
constant IS_OUTPUT : std_logic := not IS_INPUT;
begin
 
-- reset synchronisation
process(clk)
begin
rst <= p_rst_i;
end process;
clk <= p_clk_i;
-- module instances
-------------------
inst_kcpsm3 : kcpsm3
port map
(
address => address,
instruction => instruction,
port_id => pb_port_id,
write_strobe => pb_write_strobe,
out_port => pb_out_port,
read_strobe => pb_read_strobe,
in_port => pb_in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => rst,
clk => clk
);
 
inst_pbwbgpio : pbwbgpio
port map
(
address => address,
instruction => instruction,
clk => clk
);
 
inst_wbm_picoblaze : wbm_picoblaze
port map
(
rst => rst,
clk => clk,
wbm_cyc_o => wb_cyc,
wbm_stb_o => wb_stb,
wbm_we_o => wb_we,
wbm_adr_o => wb_adr,
wbm_dat_m2s_o => wb_dat_m2s,
wbm_dat_s2m_i => wb_dat_s2m,
wbm_ack_i => wb_ack,
pb_port_id_i => pb_port_id,
pb_write_strobe_i => pb_write_strobe,
pb_out_port_i => pb_out_port,
pb_read_strobe_i => pb_read_strobe,
pb_in_port_o => pb_in_port
);
 
inst_wbs_gpio : wbs_gpio
port map
(
rst => rst,
clk => clk,
wbs_cyc_i => wb_cyc,
wbs_stb_i => wb_stb,
wbs_we_i => wb_we,
wbs_adr_i => wb_adr,
wbs_dat_m2s_i => wb_dat_m2s,
wbs_dat_s2m_o => wb_dat_s2m,
wbs_ack_o => wb_ack,
gpio_in_i => gpio_in,
gpio_out_o => gpio_out,
gpio_oe_o => gpio_oe
);
-- i/o buffer generation
gpio_in <= p_gpio_io;
process(gpio_oe, gpio_out)
begin
for i in 0 to 7 loop
if gpio_oe(i) = IS_OUTPUT then
p_gpio_io(i) <= gpio_out(i);
else
p_gpio_io(i) <= 'Z';
end if;
end loop;
end process;
end rtl;
/tags/ini_rel/sim/do/picoblaze_wb_gpio_tb.do
0,0 → 1,153
################################################################################
## This sourcecode is released under BSD license.
## Please see http://www.opensource.org/licenses/bsd-license.php for details!
################################################################################
##
## Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
## All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice,
## this list of conditions and the following disclaimer.
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and/or other materials provided with the distribution.
## * Neither the name of the author nor the names of his contributors may be
## used to endorse or promote products derived from this software without
## specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
################################################################################
## filename: picoblaze_wb_gpio_tb.do
## description: ModelSim (R) do-macro / tcl-script for picoblaze_wb_gpio_tb hdl
## testbench
## todo4user: modify working directory and hdl variables
## version: 0.0.0
## changelog: - 0.0.0, initial release
## - ...
################################################################################
 
# IMPORTANT NOTICE!
# Verilog (R) simulation flow requires Xilinx (R) ISE (R) to be installed.
 
# user settings: preferred hdl and working directory
set wd "e:/home_users/ste.fis/projects/wb4pb/sim"
set isVHDL no
 
# working directory cannot be changed while simulation is running
if {![string equal -nocase [pwd] $wd]} {
quit -sim
cd $wd
}
 
# creating library work, if not existing
if {[glob -nocomplain -types d "work"] == {}} {
vlib work
}
 
# compiling hdl modules and starting simulator
if {$isVHDL} {
 
vcom -check_synthesis "../rtl/picoblaze_wb_gpio.vhd"
vcom -check_synthesis "../rtl/wbm_picoblaze.vhd"
vcom -check_synthesis "../rtl/wbs_gpio.vhd"
vcom "../rtl/kcpsm3.vhd"
vcom "../asm/pbwbgpio.vhd"
vcom "../sim/hdl/picoblaze_wb_gpio_tb.vhd"
vsim picoblaze_wb_gpio_tb behavioral
} else {
 
vlog "../rtl/picoblaze_wb_gpio.v"
vlog "../rtl/wbm_picoblaze.v"
vlog "../rtl/wbs_gpio.v"
vlog "../rtl/kcpsm3.v"
vlog "../asm/pbwbgpio.v"
vlog "../sim/hdl/picoblaze_wb_gpio_tb.v"
vlog "$env(XILINX)/verilog/src/glbl.v"
vsim picoblaze_wb_gpio_tb glbl
}
 
# configuring wave window
view -undock -x 0 -y 0 -width 1024 -height 640 wave
 
# adding signals of interest
 
proc add_wave_sys_sig? {on_off_n} {
if {$on_off_n} {
add wave -divider "SYSTEM SIGNALS"
add wave sim:/dut/rst
add wave sim:/dut/clk
}
}
 
proc add_wave_wb_sig? {on_off_n} {
if {$on_off_n} {
add wave -divider "WISHBONE SIGNALS"
#add wave sim:/dut/wb_cyc
add wave sim:/dut/wb_stb
add wave sim:/dut/wb_we
add wave -radix hex sim:/dut/wb_adr
add wave -radix hex sim:/dut/wb_dat_m2s
add wave -radix hex sim:/dut/wb_dat_s2m
add wave sim:/dut/wb_ack
}
}
 
proc add_wave_pbport_sig? {on_off_n} {
if {$on_off_n} {
add wave -divider "PICOBLAZE PORT SIGNALS"
add wave -radix hex sim:/dut/pb_port_id
add wave sim:/dut/pb_write_strobe
add wave -radix hex sim:/dut/pb_out_port
add wave sim:/dut/pb_read_strobe
add wave -radix hex sim:/dut/pb_in_port
}
}
 
proc add_wave_pbimem_sig? {on_off_n} {
if {$on_off_n} {
add wave -divider "PICOBLAZE INSTRUCTION MEMORY SIGNALS"
add wave -radix hex sim:/dut/address
add wave -radix hex sim:/dut/instruction
}
}
 
proc add_wave_gpio_sig? {on_off_n} {
if {$on_off_n} {
add wave -divider "GPIO SIGNALS"
add wave -radix hex sim:/dut/gpio_in
add wave -radix hex sim:/dut/gpio_out
add wave -radix hex sim:/dut/gpio_oe
add wave -radix hex sim:/dut/p_gpio_io
}
}
 
# selecting active signal groups
add_wave_sys_sig? yes
add_wave_wb_sig? yes
add_wave_pbport_sig? yes
add_wave_pbimem_sig? no
add_wave_gpio_sig? yes
 
# setting simulation runtime
run 10 us
 
# zooming to time area of interest
wave zoomfull
/tags/ini_rel/sim/hdl/picoblaze_wb_gpio_tb.vhd
0,0 → 1,94
--------------------------------------------------------------------------------
-- This sourcecode is released under BSD license.
-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
--------------------------------------------------------------------------------
--
-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the author nor the names of his contributors may be
-- used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- filename: picoblaze_wb_gpio_tb.vhd
-- description: testbench for picoblaze_wb_gpio example
-- todo4user: modify stimulus as needed
-- version: 0.0.0
-- changelog: - 0.0.0, initial release
-- - ...
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity picoblaze_wb_gpio_tb is
end picoblaze_wb_gpio_tb;
 
 
architecture behavioral of picoblaze_wb_gpio_tb is
 
component picoblaze_wb_gpio is
port
(
p_rst_i : in std_logic;
p_clk_i : in std_logic;
p_gpio_io : inout std_logic_vector(7 downto 0)
);
end component;
 
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal gpio : std_logic_vector(7 downto 0) := (others => 'Z');
constant PERIOD : time := 20 ns;
 
signal test_data_in : std_logic_vector(7 downto 4) := (others => '0');
begin
 
rst <= '0' after PERIOD*2;
clk <= not clk after PERIOD/2;
process
begin
wait for 2500 ns;
test_data_in <= std_logic_vector(unsigned(test_data_in) + 1);
end process;
gpio(7 downto 4) <= test_data_in;
dut : picoblaze_wb_gpio
port map
(
p_rst_i => rst,
p_clk_i => clk,
p_gpio_io => gpio
);
end behavioral;
/tags/ini_rel/sim/hdl/picoblaze_wb_gpio_tb.v
0,0 → 1,77
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: picoblaze_wb_gpio_tb.v
// description: testbench for picoblaze_wb_gpio example
// todo4user: modify stimulus as needed
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
`uselib lib = unisims_ver
 
`timescale 1 ns / 1 ps
 
 
module picoblaze_wb_gpio_tb;
 
reg rst;
reg clk;
wire[7:0] gpio;
parameter PERIOD = 20;
 
reg[7:4] test_data_in;
initial begin
test_data_in = 4'h0;
clk = 1'b1;
rst = 1'b1;
#(PERIOD*2) rst = 1'b0;
end
always #(PERIOD/2) clk = ! clk;
always #2500 test_data_in = test_data_in + 1;
assign gpio[7:4] = test_data_in;
 
picoblaze_wb_gpio dut (
.p_rst_i(rst),
.p_clk_i(clk),
.p_gpio_io(gpio)
);
endmodule

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