URL
https://opencores.org/ocsvn/wb_async_mem_bridge/wb_async_mem_bridge/trunk
Subversion Repositories wb_async_mem_bridge
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/wb_async_mem_bridge/trunk/src
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Rev 5 → Rev 6
/sync.v
1,26 → 1,26
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module sync ( |
input async_sig, |
output sync_out, |
|
input clk |
); |
|
reg [1:2] resync; |
|
always @(posedge clk) |
begin |
// update history shifter. |
resync <= {async_sig , resync[1]}; |
end |
|
assign sync_out = resync[2]; |
|
endmodule |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module sync ( |
input async_sig, |
output sync_out, |
|
input clk |
); |
|
reg [1:2] resync; |
|
always @(posedge clk) |
begin |
// update history shifter. |
resync <= {async_sig , resync[1]}; |
end |
|
assign sync_out = resync[2]; |
|
endmodule |
|
/wb_async_mem_bridge.v
1,161 → 1,161
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module |
wb_async_mem_bridge |
#( |
parameter DW = 32, |
parameter AW = 32 |
) |
( |
input [(DW-1):0] wb_data_i, |
output [(DW-1):0] wb_data_o, |
output [(AW-1):0] wb_addr_o, |
output [3:0] wb_sel_o, |
output wb_we_o, |
output wb_cyc_o, |
output wb_stb_o, |
input wb_ack_i, |
input wb_err_i, |
input wb_rty_i, |
|
inout [(DW-1):0] mem_d, |
input [(AW-1):0] mem_a, |
input mem_oe_n, |
input [3:0] mem_bls_n, |
input mem_we_n, |
input mem_cs_n, |
|
input wb_clk_i, |
input wb_rst_i |
); |
|
|
// -------------------------------------------------------------------- |
// sync data & bls |
wire [(DW-1):0] sync_mem_d; |
wire [(AW-1):0] sync_mem_a; |
wire [3:0] sync_mem_bls_n; |
|
genvar i; |
|
generate |
for( i = 0; i < DW; i = i + 1 ) |
begin: sync_data_loop |
sync i_sync( .async_sig(mem_d[i]), .sync_out(sync_mem_d[i]), .clk(wb_clk_i) ); |
end |
endgenerate |
|
generate |
for( i = 0; i < AW; i = i + 1 ) |
begin: sync_addr_loop |
sync i_sync( .async_sig(mem_a[i]), .sync_out(sync_mem_a[i]), .clk(wb_clk_i) ); |
end |
endgenerate |
|
generate |
for( i = 0; i < 4; i = i + 1 ) |
begin: sync_bls_loop |
sync i_sync( .async_sig(mem_bls_n[i]), .sync_out(sync_mem_bls_n[i]), .clk(wb_clk_i) ); |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// sync mem_cs_n & mem_oe_n & mem_we_n |
wire sync_mem_oe_n, sync_mem_oe_n_rise, sync_mem_oe_n_fall; |
wire sync_mem_cs_n; |
wire sync_mem_we_n, sync_mem_we_n_rise, sync_mem_we_n_fall; |
|
sync_edge_detect |
i_sync_mem_oe_n( |
.async_sig(mem_oe_n), |
.sync_out(sync_mem_oe_n), |
.clk(wb_clk_i), |
.rise(sync_mem_oe_n_rise), |
.fall(sync_mem_oe_n_fall) |
); |
|
sync |
i_sync_mem_cs_n( |
.async_sig(mem_cs_n), |
.sync_out(sync_mem_cs_n), |
.clk(wb_clk_i) |
); |
|
sync_edge_detect |
i_sync_mem_we_n( |
.async_sig(mem_we_n), |
.sync_out(sync_mem_we_n), |
.clk(wb_clk_i), |
.rise(sync_mem_we_n_rise), |
.fall(sync_mem_we_n_fall) |
); |
|
|
// -------------------------------------------------------------------- |
// state machine |
wb_async_mem_sm #( .DW(DW), .AW(AW) ) |
i_wb_async_mem_sm |
( |
.wb_data_i(wb_data_i), |
// .wb_data_o(wb_data_o), |
.wb_addr_i(wb_addr_o), |
// .wb_sel_o(wb_sel_o), |
.wb_we_o(wb_we_o), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
|
.mem_d(sync_mem_d), |
.mem_a(sync_mem_a), |
.mem_oe_n(sync_mem_oe_n), |
.mem_bls_n(sync_mem_bls_n), |
.mem_we_n(sync_mem_we_n), |
.mem_cs_n(sync_mem_cs_n), |
|
.mem_we_n_fall(sync_mem_we_n_fall), |
.mem_oe_n_fall(sync_mem_oe_n_fall), |
|
.wb_clk_i(wb_clk_i), |
.wb_rst_i(wb_rst_i) |
); |
|
|
|
// -------------------------------------------------------------------- |
// wb_data_i flop |
reg [(DW-1):0] wb_data_i_r; |
|
always @(posedge wb_clk_i) |
if(wb_ack_i) |
wb_data_i_r <= wb_data_i; |
|
|
// -------------------------------------------------------------------- |
// wb_data_o flop |
reg [(DW-1):0] wb_data_o_r; |
|
always @(posedge wb_clk_i) |
if(~sync_mem_we_n) |
wb_data_o_r <= sync_mem_d; |
|
|
// -------------------------------------------------------------------- |
// outputs |
|
assign mem_d = (~sync_mem_oe_n & ~sync_mem_cs_n ) ? wb_data_i_r : 'bz; |
|
assign wb_addr_o = sync_mem_a; |
assign wb_data_o = wb_data_o_r; |
assign wb_sel_o = ~sync_mem_bls_n; |
|
|
endmodule |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module |
wb_async_mem_bridge |
#( |
parameter DW = 32, |
parameter AW = 32 |
) |
( |
input [(DW-1):0] wb_data_i, |
output [(DW-1):0] wb_data_o, |
output [(AW-1):0] wb_addr_o, |
output [3:0] wb_sel_o, |
output wb_we_o, |
output wb_cyc_o, |
output wb_stb_o, |
input wb_ack_i, |
input wb_err_i, |
input wb_rty_i, |
|
inout [(DW-1):0] mem_d, |
input [(AW-1):0] mem_a, |
input mem_oe_n, |
input [3:0] mem_bls_n, |
input mem_we_n, |
input mem_cs_n, |
|
input wb_clk_i, |
input wb_rst_i |
); |
|
|
// -------------------------------------------------------------------- |
// sync data & bls |
wire [(DW-1):0] sync_mem_d; |
wire [(AW-1):0] sync_mem_a; |
wire [3:0] sync_mem_bls_n; |
|
genvar i; |
|
generate |
for( i = 0; i < DW; i = i + 1 ) |
begin: sync_data_loop |
sync i_sync( .async_sig(mem_d[i]), .sync_out(sync_mem_d[i]), .clk(wb_clk_i) ); |
end |
endgenerate |
|
generate |
for( i = 0; i < AW; i = i + 1 ) |
begin: sync_addr_loop |
sync i_sync( .async_sig(mem_a[i]), .sync_out(sync_mem_a[i]), .clk(wb_clk_i) ); |
end |
endgenerate |
|
generate |
for( i = 0; i < 4; i = i + 1 ) |
begin: sync_bls_loop |
sync i_sync( .async_sig(mem_bls_n[i]), .sync_out(sync_mem_bls_n[i]), .clk(wb_clk_i) ); |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// sync mem_cs_n & mem_oe_n & mem_we_n |
wire sync_mem_oe_n, sync_mem_oe_n_rise, sync_mem_oe_n_fall; |
wire sync_mem_cs_n; |
wire sync_mem_we_n, sync_mem_we_n_rise, sync_mem_we_n_fall; |
|
sync_edge_detect |
i_sync_mem_oe_n( |
.async_sig(mem_oe_n), |
.sync_out(sync_mem_oe_n), |
.clk(wb_clk_i), |
.rise(sync_mem_oe_n_rise), |
.fall(sync_mem_oe_n_fall) |
); |
|
sync |
i_sync_mem_cs_n( |
.async_sig(mem_cs_n), |
.sync_out(sync_mem_cs_n), |
.clk(wb_clk_i) |
); |
|
sync_edge_detect |
i_sync_mem_we_n( |
.async_sig(mem_we_n), |
.sync_out(sync_mem_we_n), |
.clk(wb_clk_i), |
.rise(sync_mem_we_n_rise), |
.fall(sync_mem_we_n_fall) |
); |
|
|
// -------------------------------------------------------------------- |
// state machine |
wb_async_mem_sm #( .DW(DW), .AW(AW) ) |
i_wb_async_mem_sm |
( |
.wb_data_i(wb_data_i), |
// .wb_data_o(wb_data_o), |
.wb_addr_i(wb_addr_o), |
// .wb_sel_o(wb_sel_o), |
.wb_we_o(wb_we_o), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
|
.mem_d(sync_mem_d), |
.mem_a(sync_mem_a), |
.mem_oe_n(sync_mem_oe_n), |
.mem_bls_n(sync_mem_bls_n), |
.mem_we_n(sync_mem_we_n), |
.mem_cs_n(sync_mem_cs_n), |
|
.mem_we_n_fall(sync_mem_we_n_fall), |
.mem_oe_n_fall(sync_mem_oe_n_fall), |
|
.wb_clk_i(wb_clk_i), |
.wb_rst_i(wb_rst_i) |
); |
|
|
|
// -------------------------------------------------------------------- |
// wb_data_i flop |
reg [(DW-1):0] wb_data_i_r; |
|
always @(posedge wb_clk_i) |
if(wb_ack_i) |
wb_data_i_r <= wb_data_i; |
|
|
// -------------------------------------------------------------------- |
// wb_data_o flop |
reg [(DW-1):0] wb_data_o_r; |
|
always @(posedge wb_clk_i) |
if(~sync_mem_we_n) |
wb_data_o_r <= sync_mem_d; |
|
|
// -------------------------------------------------------------------- |
// outputs |
|
assign mem_d = (~sync_mem_oe_n & ~sync_mem_cs_n ) ? wb_data_i_r : 'bz; |
|
assign wb_addr_o = sync_mem_a; |
assign wb_data_o = wb_data_o_r; |
assign wb_sel_o = ~sync_mem_bls_n; |
|
|
endmodule |
|
/test_harness.v
1,96 → 1,96
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module |
test_harness( |
inout [35:0] gpio_0, |
inout [35:0] gpio_1, |
|
input sys_clk_i, |
input sys_rst_i |
); |
|
|
// -------------------------------------------------------------------- |
// wb_async_mem_bridge |
wire [31:0] wb_data_i; |
wire [31:0] wb_data_o; |
wire [31:0] wb_addr_o; |
wire [3:0] wb_sel_o; |
wire wb_we_o; |
wire wb_cyc_o; |
wire wb_stb_o; |
wire wb_ack_i; |
wire wb_err_i; |
wire wb_rty_i; |
|
wb_async_mem_bridge i_wb_async_mem_bridge( |
.wb_data_i(wb_data_i), |
.wb_data_o(wb_data_o), |
.wb_addr_o(wb_addr_o), |
.wb_sel_o(wb_sel_o), |
.wb_we_o(wb_we_o), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
|
.mem_d( gpio_1[31:0] ), |
.mem_a( {8'h00, gpio_0[23:0]} ), |
.mem_oe_n( gpio_0[30] ), |
.mem_bls_n( { gpio_0[26], gpio_0[27], gpio_0[28], gpio_0[29] } ), |
.mem_we_n( gpio_0[25] ), |
.mem_cs_n( gpio_0[24] ), |
|
.wb_clk_i(sys_clk_i), |
.wb_rst_i(sys_rst_i) |
); |
|
|
|
// -------------------------------------------------------------------- |
// soc_ram |
soc_ram |
i_soc_ram_0( |
.data(wb_data_o[7:0]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[0]), |
.clk(sys_clk_i), |
.q(wb_data_i[7:0]) |
); |
|
soc_ram |
i_soc_ram_1( |
.data(wb_data_o[15:8]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[1]), |
.clk(sys_clk_i), |
.q(wb_data_i[15:8]) |
); |
|
soc_ram |
i_soc_ram_2( |
.data(wb_data_o[23:16]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[2]), |
.clk(sys_clk_i), |
.q(wb_data_i[23:16]) |
); |
|
soc_ram |
i_soc_ram_3( |
.data(wb_data_o[31:24]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[3]), |
.clk(sys_clk_i), |
.q(wb_data_i[31:24]) |
); |
|
|
endmodule |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module |
test_harness( |
inout [35:0] gpio_0, |
inout [35:0] gpio_1, |
|
input sys_clk_i, |
input sys_rst_i |
); |
|
|
// -------------------------------------------------------------------- |
// wb_async_mem_bridge |
wire [31:0] wb_data_i; |
wire [31:0] wb_data_o; |
wire [31:0] wb_addr_o; |
wire [3:0] wb_sel_o; |
wire wb_we_o; |
wire wb_cyc_o; |
wire wb_stb_o; |
wire wb_ack_i; |
wire wb_err_i; |
wire wb_rty_i; |
|
wb_async_mem_bridge i_wb_async_mem_bridge( |
.wb_data_i(wb_data_i), |
.wb_data_o(wb_data_o), |
.wb_addr_o(wb_addr_o), |
.wb_sel_o(wb_sel_o), |
.wb_we_o(wb_we_o), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
|
.mem_d( gpio_1[31:0] ), |
.mem_a( {8'h00, gpio_0[23:0]} ), |
.mem_oe_n( gpio_0[30] ), |
.mem_bls_n( { gpio_0[26], gpio_0[27], gpio_0[28], gpio_0[29] } ), |
.mem_we_n( gpio_0[25] ), |
.mem_cs_n( gpio_0[24] ), |
|
.wb_clk_i(sys_clk_i), |
.wb_rst_i(sys_rst_i) |
); |
|
|
|
// -------------------------------------------------------------------- |
// soc_ram |
soc_ram |
i_soc_ram_0( |
.data(wb_data_o[7:0]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[0]), |
.clk(sys_clk_i), |
.q(wb_data_i[7:0]) |
); |
|
soc_ram |
i_soc_ram_1( |
.data(wb_data_o[15:8]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[1]), |
.clk(sys_clk_i), |
.q(wb_data_i[15:8]) |
); |
|
soc_ram |
i_soc_ram_2( |
.data(wb_data_o[23:16]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[2]), |
.clk(sys_clk_i), |
.q(wb_data_i[23:16]) |
); |
|
soc_ram |
i_soc_ram_3( |
.data(wb_data_o[31:24]), |
.addr(wb_addr_o[7:2]), |
.we(wb_we_o & wb_stb_o & wb_sel_o[3]), |
.clk(sys_clk_i), |
.q(wb_data_i[31:24]) |
); |
|
|
endmodule |
|
/top.v
1,166 → 1,166
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module top( |
//////////////////////// Clock Input //////////////////////// |
input [1:0] clock_24, // 24 MHz |
input [1:0] clock_27, // 27 MHz |
input clock_50, // 50 MHz |
input ext_clock, // External Clock |
//////////////////////// Push Button //////////////////////// |
input [3:0] key, // Pushbutton[3:0] |
//////////////////////// DPDT Switch //////////////////////// |
input [9:0] sw, // Toggle Switch[9:0] |
//////////////////////// 7-SEG Dispaly //////////////////////// |
output [6:0] hex0, // Seven Segment Digit 0 |
output [6:0] hex1, // Seven Segment Digit 1 |
output [6:0] hex2, // Seven Segment Digit 2 |
output [6:0] hex3, // Seven Segment Digit 3 |
//////////////////////////// LED //////////////////////////// |
output [7:0] ledg, // LED Green[7:0] |
output [9:0] ledr, // LED Red[9:0] |
//////////////////////////// UART //////////////////////////// |
output uart_txd, // UART Transmitter |
input uart_rxd, // UART Receiver |
/////////////////////// SDRAM Interface //////////////////////// |
inout [15:0] dram_dq, // SDRAM Data bus 16 Bits |
output [11:0] dram_addr, // SDRAM Address bus 12 Bits |
output dram_ldqm, // SDRAM Low-byte Data Mask |
output dram_udqm, // SDRAM High-byte Data Mask |
output dram_we_n, // SDRAM Write Enable |
output dram_cas_n, // SDRAM Column Address Strobe |
output dram_ras_n, // SDRAM Row Address Strobe |
output dram_cs_n, // SDRAM Chip Select |
output dram_ba_0, // SDRAM Bank Address 0 |
output dram_ba_1, // SDRAM Bank Address 0 |
output dram_clk, // SDRAM Clock |
output dram_cke, // SDRAM Clock Enable |
//////////////////////// Flash Interface //////////////////////// |
inout [7:0] fl_dq, // FLASH Data bus 8 Bits |
output [21:0] fl_addr, // FLASH Address bus 22 Bits |
output fl_we_n, // FLASH Write Enable |
output fl_rst_n, // FLASH Reset |
output fl_oe_n, // FLASH Output Enable |
output fl_ce_n, // FLASH Chip Enable |
//////////////////////// SRAM Interface //////////////////////// |
inout [15:0] sram_dq, // SRAM Data bus 16 Bits |
output [17:0] sram_addr, // SRAM Address bus 18 Bits |
output sram_ub_n, // SRAM High-byte Data Mask |
output sram_lb_n, // SRAM Low-byte Data Mask |
output sram_we_n, // SRAM Write Enable |
output sram_ce_n, // SRAM Chip Enable |
output sram_oe_n, // SRAM Output Enable |
//////////////////// SD Card Interface //////////////////////// |
inout sd_dat, // SD Card Data |
inout sd_dat3, // SD Card Data 3 |
inout sd_cmd, // SD Card Command Signal |
output sd_clk, // SD Card Clock |
//////////////////////// I2C //////////////////////////////// |
inout i2c_sdat, // I2C Data |
output i2c_sclk, // I2C Clock |
//////////////////////// PS2 //////////////////////////////// |
input ps2_dat, // PS2 Data |
input ps2_clk, // PS2 Clock |
//////////////////// USB JTAG link //////////////////////////// |
input tdi, // CPLD -> FPGA (data in) |
input tck, // CPLD -> FPGA (clk) |
input tcs, // CPLD -> FPGA (CS) |
output tdo, // FPGA -> CPLD (data out) |
//////////////////////// VGA //////////////////////////// |
output vga_hs, // VGA H_SYNC |
output vga_vs, // VGA V_SYNC |
output [3:0] vga_r, // VGA Red[3:0] |
output [3:0] vga_g, // VGA Green[3:0] |
output [3:0] vga_b, // VGA Blue[3:0] |
//////////////////// Audio CODEC //////////////////////////// |
inout aud_adclrck, // Audio CODEC ADC LR Clock |
input aud_adcdat, // Audio CODEC ADC Data |
inout aud_daclrck, // Audio CODEC DAC LR Clock |
output aud_dacdat, // Audio CODEC DAC Data |
inout aud_bclk, // Audio CODEC Bit-Stream Clock |
output aud_xck, // Audio CODEC Chip Clock |
//////////////////////// GPIO //////////////////////////////// |
inout [35:0] gpio_0, // GPIO Connection 0 |
inout [35:0] gpio_1 // GPIO Connection 1 |
); |
|
|
//--------------------------------------------------- |
// system wires |
wire reset_switch; |
wire sysclk = clock_24[0]; |
|
|
//--------------------------------------------------- |
// sync reset |
sync |
i_sync_reset( |
.async_sig(~key[0]), |
.sync_out(reset_switch), |
.clk(sysclk) |
); |
|
|
//--------------------------------------------------- |
// FLED |
reg [24:0] counter; |
wire [7:0] fled; |
|
always @(posedge sysclk or posedge reset_switch) |
if(reset_switch) |
counter <= 25'b0; |
else |
counter <= counter + 1; |
|
assign fled[0] = sw[0]; |
assign fled[1] = sw[1]; |
assign fled[2] = sw[2]; |
assign fled[3] = sw[3]; |
assign fled[4] = sw[4]; |
assign fled[5] = sw[5]; |
assign fled[6] = sw[6]; |
assign fled[7] = counter[24]; |
|
|
//--------------------------------------------------- |
// test_harness |
test_harness i_test_harness( |
.gpio_0(gpio_0), |
.gpio_1(gpio_1), |
|
.sys_clk_i(sysclk), |
.sys_rst_i(reset_switch) |
); |
|
|
//--------------------------------------------------- |
// outputs |
|
// Turn off all display |
assign hex0 = 7'h7f; |
assign hex1 = 7'h7f; |
assign hex2 = 7'h7f; |
assign hex3 = 7'h7f; |
// assign ledg = 8'hff; |
assign ledg = fled; |
assign ledr = 10'h000; |
|
// All inout port turn to tri-state |
assign dram_dq = 16'hzzzz; |
assign fl_dq = 8'hzz; |
assign sram_dq = 16'hzzzz; |
assign sd_dat = 1'bz; |
assign i2c_sdat = 1'bz; |
assign aud_adclrck = 1'bz; |
assign aud_daclrck = 1'bz; |
assign aud_bclk = 1'bz; |
assign gpio_0 = 36'hzzzzzzzzz; |
assign gpio_1 = 36'hzzzzzzzzz; |
|
|
endmodule |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module top( |
//////////////////////// Clock Input //////////////////////// |
input [1:0] clock_24, // 24 MHz |
input [1:0] clock_27, // 27 MHz |
input clock_50, // 50 MHz |
input ext_clock, // External Clock |
//////////////////////// Push Button //////////////////////// |
input [3:0] key, // Pushbutton[3:0] |
//////////////////////// DPDT Switch //////////////////////// |
input [9:0] sw, // Toggle Switch[9:0] |
//////////////////////// 7-SEG Dispaly //////////////////////// |
output [6:0] hex0, // Seven Segment Digit 0 |
output [6:0] hex1, // Seven Segment Digit 1 |
output [6:0] hex2, // Seven Segment Digit 2 |
output [6:0] hex3, // Seven Segment Digit 3 |
//////////////////////////// LED //////////////////////////// |
output [7:0] ledg, // LED Green[7:0] |
output [9:0] ledr, // LED Red[9:0] |
//////////////////////////// UART //////////////////////////// |
output uart_txd, // UART Transmitter |
input uart_rxd, // UART Receiver |
/////////////////////// SDRAM Interface //////////////////////// |
inout [15:0] dram_dq, // SDRAM Data bus 16 Bits |
output [11:0] dram_addr, // SDRAM Address bus 12 Bits |
output dram_ldqm, // SDRAM Low-byte Data Mask |
output dram_udqm, // SDRAM High-byte Data Mask |
output dram_we_n, // SDRAM Write Enable |
output dram_cas_n, // SDRAM Column Address Strobe |
output dram_ras_n, // SDRAM Row Address Strobe |
output dram_cs_n, // SDRAM Chip Select |
output dram_ba_0, // SDRAM Bank Address 0 |
output dram_ba_1, // SDRAM Bank Address 0 |
output dram_clk, // SDRAM Clock |
output dram_cke, // SDRAM Clock Enable |
//////////////////////// Flash Interface //////////////////////// |
inout [7:0] fl_dq, // FLASH Data bus 8 Bits |
output [21:0] fl_addr, // FLASH Address bus 22 Bits |
output fl_we_n, // FLASH Write Enable |
output fl_rst_n, // FLASH Reset |
output fl_oe_n, // FLASH Output Enable |
output fl_ce_n, // FLASH Chip Enable |
//////////////////////// SRAM Interface //////////////////////// |
inout [15:0] sram_dq, // SRAM Data bus 16 Bits |
output [17:0] sram_addr, // SRAM Address bus 18 Bits |
output sram_ub_n, // SRAM High-byte Data Mask |
output sram_lb_n, // SRAM Low-byte Data Mask |
output sram_we_n, // SRAM Write Enable |
output sram_ce_n, // SRAM Chip Enable |
output sram_oe_n, // SRAM Output Enable |
//////////////////// SD Card Interface //////////////////////// |
inout sd_dat, // SD Card Data |
inout sd_dat3, // SD Card Data 3 |
inout sd_cmd, // SD Card Command Signal |
output sd_clk, // SD Card Clock |
//////////////////////// I2C //////////////////////////////// |
inout i2c_sdat, // I2C Data |
output i2c_sclk, // I2C Clock |
//////////////////////// PS2 //////////////////////////////// |
input ps2_dat, // PS2 Data |
input ps2_clk, // PS2 Clock |
//////////////////// USB JTAG link //////////////////////////// |
input tdi, // CPLD -> FPGA (data in) |
input tck, // CPLD -> FPGA (clk) |
input tcs, // CPLD -> FPGA (CS) |
output tdo, // FPGA -> CPLD (data out) |
//////////////////////// VGA //////////////////////////// |
output vga_hs, // VGA H_SYNC |
output vga_vs, // VGA V_SYNC |
output [3:0] vga_r, // VGA Red[3:0] |
output [3:0] vga_g, // VGA Green[3:0] |
output [3:0] vga_b, // VGA Blue[3:0] |
//////////////////// Audio CODEC //////////////////////////// |
inout aud_adclrck, // Audio CODEC ADC LR Clock |
input aud_adcdat, // Audio CODEC ADC Data |
inout aud_daclrck, // Audio CODEC DAC LR Clock |
output aud_dacdat, // Audio CODEC DAC Data |
inout aud_bclk, // Audio CODEC Bit-Stream Clock |
output aud_xck, // Audio CODEC Chip Clock |
//////////////////////// GPIO //////////////////////////////// |
inout [35:0] gpio_0, // GPIO Connection 0 |
inout [35:0] gpio_1 // GPIO Connection 1 |
); |
|
|
//--------------------------------------------------- |
// system wires |
wire reset_switch; |
wire sysclk = clock_24[0]; |
|
|
//--------------------------------------------------- |
// sync reset |
sync |
i_sync_reset( |
.async_sig(~key[0]), |
.sync_out(reset_switch), |
.clk(sysclk) |
); |
|
|
//--------------------------------------------------- |
// FLED |
reg [24:0] counter; |
wire [7:0] fled; |
|
always @(posedge sysclk or posedge reset_switch) |
if(reset_switch) |
counter <= 25'b0; |
else |
counter <= counter + 1; |
|
assign fled[0] = sw[0]; |
assign fled[1] = sw[1]; |
assign fled[2] = sw[2]; |
assign fled[3] = sw[3]; |
assign fled[4] = sw[4]; |
assign fled[5] = sw[5]; |
assign fled[6] = sw[6]; |
assign fled[7] = counter[24]; |
|
|
//--------------------------------------------------- |
// test_harness |
test_harness i_test_harness( |
.gpio_0(gpio_0), |
.gpio_1(gpio_1), |
|
.sys_clk_i(sysclk), |
.sys_rst_i(reset_switch) |
); |
|
|
//--------------------------------------------------- |
// outputs |
|
// Turn off all display |
assign hex0 = 7'h7f; |
assign hex1 = 7'h7f; |
assign hex2 = 7'h7f; |
assign hex3 = 7'h7f; |
// assign ledg = 8'hff; |
assign ledg = fled; |
assign ledr = 10'h000; |
|
// All inout port turn to tri-state |
assign dram_dq = 16'hzzzz; |
assign fl_dq = 8'hzz; |
assign sram_dq = 16'hzzzz; |
assign sd_dat = 1'bz; |
assign i2c_sdat = 1'bz; |
assign aud_adclrck = 1'bz; |
assign aud_daclrck = 1'bz; |
assign aud_bclk = 1'bz; |
assign gpio_0 = 36'hzzzzzzzzz; |
assign gpio_1 = 36'hzzzzzzzzz; |
|
|
endmodule |
|
/wb_async_mem_sm.v
1,131 → 1,131
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module |
wb_async_mem_sm |
#( |
parameter DW = 32, |
parameter AW = 32 |
) |
( |
input [(DW-1):0] wb_data_i, |
input [(AW-1):0] wb_addr_i, |
output wb_we_o, |
output wb_cyc_o, |
output wb_stb_o, |
input wb_ack_i, |
input wb_err_i, |
input wb_rty_i, |
|
input [(DW-1):0] mem_d, |
input [(AW-1):0] mem_a, |
input mem_oe_n, |
input [3:0] mem_bls_n, |
input mem_we_n, |
input mem_cs_n, |
|
input mem_we_n_fall, |
input mem_oe_n_fall, |
|
output [5:0] dbg_state, |
|
input wb_clk_i, |
input wb_rst_i |
); |
|
|
// -------------------------------------------------------------------- |
// wires |
wire address_change; |
|
|
// -------------------------------------------------------------------- |
// state machine |
|
localparam STATE_IDLE = 6'b000001; |
localparam STATE_WE = 6'b000010; |
localparam STATE_OE = 6'b000100; |
localparam STATE_DONE = 6'b001000; |
localparam STATE_ERROR = 6'b010000; |
localparam STATE_GLITCH = 6'b100000; |
|
reg [5:0] state; |
reg [5:0] next_state; |
|
always @(posedge wb_clk_i or posedge wb_rst_i) |
if(wb_rst_i) |
state <= STATE_IDLE; |
else |
state <= next_state; |
|
always @(*) |
case( state ) |
STATE_IDLE: if( (mem_oe_n & mem_we_n) | mem_cs_n ) |
next_state = STATE_IDLE; |
else |
if( ~mem_oe_n & ~mem_we_n ) |
next_state = STATE_ERROR; |
else |
if( ~mem_we_n ) |
next_state = STATE_WE; |
else |
next_state = STATE_OE; |
|
STATE_WE: if( mem_we_n | mem_cs_n ) |
next_state = STATE_ERROR; |
else |
if( wb_ack_i ) |
next_state = STATE_DONE; |
else |
next_state = STATE_WE; |
|
STATE_OE: if( mem_oe_n | mem_cs_n | address_change ) |
next_state = STATE_ERROR; |
else |
if( wb_ack_i ) |
next_state = STATE_DONE; |
else |
next_state = STATE_OE; |
|
STATE_DONE: if( mem_cs_n ) |
next_state = STATE_IDLE; |
else |
if( mem_we_n_fall ) |
next_state = STATE_WE; |
else if( mem_oe_n_fall ) |
next_state = STATE_OE; |
else |
next_state = STATE_DONE; |
|
STATE_ERROR: next_state = STATE_IDLE; |
|
STATE_GLITCH: next_state = STATE_IDLE; |
|
default: next_state = STATE_GLITCH; |
endcase |
|
|
// -------------------------------------------------------------------- |
// wb_addr_i flop |
reg [(AW-1):0] wb_addr_i_r; |
assign address_change = (wb_addr_i != wb_addr_i_r); |
|
always @(posedge wb_clk_i) |
if( (state != STATE_DONE) | (state != STATE_OE) ) |
wb_addr_i_r <= wb_addr_i; |
|
|
// -------------------------------------------------------------------- |
// outputs |
assign wb_cyc_o = (state == STATE_WE) | (state == STATE_OE); |
assign wb_stb_o = (state == STATE_WE) | (state == STATE_OE); |
assign wb_we_o = (state == STATE_WE); |
|
assign dbg_state = state; |
|
endmodule |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module |
wb_async_mem_sm |
#( |
parameter DW = 32, |
parameter AW = 32 |
) |
( |
input [(DW-1):0] wb_data_i, |
input [(AW-1):0] wb_addr_i, |
output wb_we_o, |
output wb_cyc_o, |
output wb_stb_o, |
input wb_ack_i, |
input wb_err_i, |
input wb_rty_i, |
|
input [(DW-1):0] mem_d, |
input [(AW-1):0] mem_a, |
input mem_oe_n, |
input [3:0] mem_bls_n, |
input mem_we_n, |
input mem_cs_n, |
|
input mem_we_n_fall, |
input mem_oe_n_fall, |
|
output [5:0] dbg_state, |
|
input wb_clk_i, |
input wb_rst_i |
); |
|
|
// -------------------------------------------------------------------- |
// wires |
wire address_change; |
|
|
// -------------------------------------------------------------------- |
// state machine |
|
localparam STATE_IDLE = 6'b000001; |
localparam STATE_WE = 6'b000010; |
localparam STATE_OE = 6'b000100; |
localparam STATE_DONE = 6'b001000; |
localparam STATE_ERROR = 6'b010000; |
localparam STATE_GLITCH = 6'b100000; |
|
reg [5:0] state; |
reg [5:0] next_state; |
|
always @(posedge wb_clk_i or posedge wb_rst_i) |
if(wb_rst_i) |
state <= STATE_IDLE; |
else |
state <= next_state; |
|
always @(*) |
case( state ) |
STATE_IDLE: if( (mem_oe_n & mem_we_n) | mem_cs_n ) |
next_state = STATE_IDLE; |
else |
if( ~mem_oe_n & ~mem_we_n ) |
next_state = STATE_ERROR; |
else |
if( ~mem_we_n ) |
next_state = STATE_WE; |
else |
next_state = STATE_OE; |
|
STATE_WE: if( mem_we_n | mem_cs_n ) |
next_state = STATE_ERROR; |
else |
if( wb_ack_i ) |
next_state = STATE_DONE; |
else |
next_state = STATE_WE; |
|
STATE_OE: if( mem_oe_n | mem_cs_n | address_change ) |
next_state = STATE_ERROR; |
else |
if( wb_ack_i ) |
next_state = STATE_DONE; |
else |
next_state = STATE_OE; |
|
STATE_DONE: if( mem_cs_n ) |
next_state = STATE_IDLE; |
else |
if( mem_we_n_fall ) |
next_state = STATE_WE; |
else if( mem_oe_n_fall ) |
next_state = STATE_OE; |
else |
next_state = STATE_DONE; |
|
STATE_ERROR: next_state = STATE_IDLE; |
|
STATE_GLITCH: next_state = STATE_IDLE; |
|
default: next_state = STATE_GLITCH; |
endcase |
|
|
// -------------------------------------------------------------------- |
// wb_addr_i flop |
reg [(AW-1):0] wb_addr_i_r; |
assign address_change = (wb_addr_i != wb_addr_i_r); |
|
always @(posedge wb_clk_i) |
if( (state != STATE_DONE) | (state != STATE_OE) ) |
wb_addr_i_r <= wb_addr_i; |
|
|
// -------------------------------------------------------------------- |
// outputs |
assign wb_cyc_o = (state == STATE_WE) | (state == STATE_OE); |
assign wb_stb_o = (state == STATE_WE) | (state == STATE_OE); |
assign wb_we_o = (state == STATE_WE); |
|
assign dbg_state = state; |
|
endmodule |
|
/soc_ram.v
1,41 → 1,41
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module soc_ram( data, addr, we, clk, q ); |
|
parameter DATA_WIDTH = 8; |
parameter ADDR_WIDTH = 6; |
parameter MEM_INIT = 0; |
|
input [(DATA_WIDTH-1):0] data; |
input [(ADDR_WIDTH-1):0] addr; |
input we; |
input clk; |
output [(DATA_WIDTH-1):0] q; |
|
// Declare the RAM variable |
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; |
reg [ADDR_WIDTH-1:0] addr_reg; |
|
|
always @ (posedge clk) |
begin |
// Write |
if (we) ram[addr] <= data; |
addr_reg <= addr; |
end |
|
// Read returns NEW data at addr if we == 1'b1. This is the |
// natural behavior of TriMatrix memory blocks in Single Port |
// mode |
assign q = ram[addr_reg]; |
|
// generate |
// if( MEM_INIT != 0 ) |
// initial |
// $readmemh( MEM_INIT, ram ); |
// endgenerate |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module soc_ram( data, addr, we, clk, q ); |
|
parameter DATA_WIDTH = 8; |
parameter ADDR_WIDTH = 6; |
parameter MEM_INIT = 0; |
|
input [(DATA_WIDTH-1):0] data; |
input [(ADDR_WIDTH-1):0] addr; |
input we; |
input clk; |
output [(DATA_WIDTH-1):0] q; |
|
// Declare the RAM variable |
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; |
reg [ADDR_WIDTH-1:0] addr_reg; |
|
|
always @ (posedge clk) |
begin |
// Write |
if (we) ram[addr] <= data; |
addr_reg <= addr; |
end |
|
// Read returns NEW data at addr if we == 1'b1. This is the |
// natural behavior of TriMatrix memory blocks in Single Port |
// mode |
assign q = ram[addr_reg]; |
|
// generate |
// if( MEM_INIT != 0 ) |
// initial |
// $readmemh( MEM_INIT, ram ); |
// endgenerate |
|
endmodule |
/sync_edge_detect.v
1,32 → 1,32
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module sync_edge_detect ( |
input async_sig, |
output sync_out, |
|
input clk, |
|
output reg rise, |
output reg fall |
); |
|
reg [1:3] resync; |
|
always @(posedge clk) |
begin |
// detect rising and falling edges. |
rise <= ~resync[3] & resync[2]; |
fall <= ~resync[2] & resync[3]; |
// update history shifter. |
resync <= {async_sig , resync[1:2]}; |
end |
|
assign sync_out = resync[2]; |
|
endmodule |
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`include "timescale.v" |
|
|
module sync_edge_detect ( |
input async_sig, |
output sync_out, |
|
input clk, |
|
output reg rise, |
output reg fall |
); |
|
reg [1:3] resync; |
|
always @(posedge clk) |
begin |
// detect rising and falling edges. |
rise <= ~resync[3] & resync[2]; |
fall <= ~resync[2] & resync[3]; |
// update history shifter. |
resync <= {async_sig , resync[1:2]}; |
end |
|
assign sync_out = resync[2]; |
|
endmodule |
|