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URL https://opencores.org/ocsvn/wb_fifo/wb_fifo/trunk

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Rev 3 → Rev 4

/model/vhdl/fifo.vhdl
52,6 → 52,9
signal memory:t_memory;
signal ptr:natural range 0 to memoryDepth-1;
/* FIFO control signalling. */
signal fifoCtrl:t_fifo;
/*
writeRequest and readRequest are inputs. This indicate that a block is requesting to write to or
read from the FIFO.
133,26 → 136,26
if falling_edge(clk) then
i_writeRequest <= fifoInterface.writeRequest;
i_readRequest <= fifoInterface.readRequest;
i_full <= fifoInterface.full;
i_empty <= fifoInterface.empty;
i_full <= fifoCtrl.full;
i_empty <= fifoCtrl.empty;
end if;
end process;
fifoInterface.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoInterface.pctFilled'length);
fifoCtrl.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoCtrl.pctFilled'length);
process(clk) is begin
if rising_edge(clk) then
fifoInterface.nearFull<=true when fifoInterface.pctFilled>=d"75" and fifoInterface.pctFilled<d"100" else false;
fifoInterface.full<=true when fifoInterface.pctFilled=d"100" else false;
fifoInterface.nearEmpty<=true when fifoInterface.pctFilled<=d"25" and fifoInterface.pctFilled>d"0" else false;
fifoInterface.empty<=true when fifoInterface.pctFilled=d"0" else false;
fifoCtrl.nearFull<=true when fifoCtrl.pctFilled>=d"75" and fifoCtrl.pctFilled<d"100" else false;
fifoCtrl.full<=true when fifoCtrl.pctFilled=d"100" else false;
fifoCtrl.nearEmpty<=true when fifoCtrl.pctFilled<=d"25" and fifoCtrl.pctFilled>d"0" else false;
fifoCtrl.empty<=true when fifoCtrl.pctFilled=d"0" else false;
end if;
end process;
process(clk) is begin
if falling_edge(clk) then
fifoInterface.overflow<=fifoInterface.full and write;
fifoInterface.underflow<=fifoInterface.empty and read;
fifoCtrl.overflow<=fifoCtrl.full and write;
fifoCtrl.underflow<=fifoCtrl.empty and read;
end if;
end process;
end architecture rtl;
/model/vhdl/packages/pkg-fifo-tlm.vhdl
50,14 → 50,11
type t_fifoTransactor is record
writeRequest,readRequest:t_bfm;
writeResponse,readResponse:t_bfm;
pctFilled:unsigned(7 downto 0);
nearFull,full:boolean;
nearEmpty,empty:boolean;
overflow,underflow:boolean;
end record t_fifoTransactor;
/* Use separate FIFO structure when request and response are
made into separate structures (for different directions).
/* Use separate record for FIFO signalling.
This will make it easier when we need to split up the request and response
structures into separate records (for different directions).
*/
type t_fifo is record
pctFilled:unsigned(7 downto 0);

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