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URL https://opencores.org/ocsvn/wb_fifo/wb_fifo/trunk

Subversion Repositories wb_fifo

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  • This comparison shows the changes necessary to convert path 
    /wb_fifo/trunk
    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/model/vhdl/fifo.vhdl
79,12 → 79,30
signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
signal i_full,i_empty:boolean;
signal write,read:boolean;
signal writeRequested, readRequested: boolean;
begin
/* Registers and pipelines. */
/* TODO recheck pipelining. */
process(clk) is begin
if falling_edge(clk) then
/* TODO add buffers for pipelined request signals,
i.e., add a flip-flop and a buffer.
*/
i_writeRequest <= fifoInterface.writeRequest after 1 ps;
i_readRequest <= fifoInterface.readRequest after 1 ps;
i_full <= fifoCtrl.full;
i_empty <= fifoCtrl.empty;
end if;
end process;
/* Synchronous FIFO. */
controller: process(reset,clk) is begin
if reset then
fifoInterface.readResponse.message<=(others=>'Z');
fifoInterface.readResponse.trigger<=false;
elsif falling_edge(clk) then
--if reset then
-- fifoInterface.readResponse.message<=(others=>'Z');
-- fifoInterface.readResponse.trigger<=false;
if falling_edge(clk) then
/* Default assignments. */
fifoInterface.readResponse.trigger<=false;
fifoInterface.writeResponse.trigger<=false;
93,7 → 111,8
Safety control: allow writing only when FIFO is not full.
*/
--if i_pctFilled<d"100" and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
if not i_full and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
--if not i_full and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then -- TODO change to write
if not i_full and write then
fifoInterface.writeResponse.trigger<=true;
memory(ptr)<=fifoInterface.writeRequest.message;
end if;
101,16 → 120,34
/* Read request.
Safety control: allow reading only when FIFO is not empty.
*/
if not i_empty and (fifoInterface.readRequest.trigger xor i_readRequest.trigger) then
--if not i_empty and (fifoInterface.readRequest.trigger xor i_readRequest.trigger) then -- TODO change to read
if not i_empty and read then
fifoInterface.readResponse.trigger<=true;
fifoInterface.readResponse.message<=memory(ptr);
end if;
/* Synchronous reset. */
if reset then
fifoInterface.readResponse.message<=(others=>'Z');
fifoInterface.readResponse.trigger<=false;
end if;
end if;
end process controller;
write<=fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
read<=fifoInterface.readRequest.trigger xor i_readRequest.trigger;
write <= fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
read <= fifoInterface.readRequest.trigger xor i_readRequest.trigger;
/* Request indicator. Derived from fifoInterface.writeRequest.trigger
and fifoInterface.readRequest.trigger.
Asserts when there are incoming requests.
*/
process(clk) is begin
if falling_edge(clk) then
writeRequested <= fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
readRequested <= fifoInterface.readRequest.trigger xor i_readRequest.trigger;
end if;
end process;
addrPointer: process(reset,clk) is begin
if reset then ptr<=0;
elsif falling_edge(clk) then
128,17 → 165,6
end if;
end process addrPointer;
/* Registers and pipelines. */
/* TODO recheck pipelining. */
process(clk) is begin
if falling_edge(clk) then
i_writeRequest <= fifoInterface.writeRequest;
i_readRequest <= fifoInterface.readRequest;
i_full <= fifoCtrl.full;
i_empty <= fifoCtrl.empty;
end if;
end process;
fifoCtrl.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoCtrl.pctFilled'length);
process(clk) is begin
/model/vhdl/packages/pkg-tlm.vhdl
59,13 → 59,13
end record t_bfm;
procedure write(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout if tool doesn't support reading from out ports.
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
);
procedure read(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout if tool doesn't support reading from out ports.
address:in t_addr -- used only for non-stream interfaces.
);
end package tlm;
72,7 → 72,7
 
package body tlm is
procedure write(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout if tool doesn't support reading from out ports.
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
) is begin
82,7 → 82,7
end procedure write;
procedure read(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout if tool doesn't support reading from out ports.
address:in t_addr -- used only for non-stream interfaces.
) is begin
request.address<=address;
/model/vhdl/packages/pkg-fifo-tlm.vhdl
38,7 → 38,6
--use std.textio.all;
library tauhop; --use tauhop.transactor.all;
 
/* Record I/O data structures for AXI interface transactor (block interface). */
package fifoTLM is
generic(
package i_transactor is new tauhop.tlm generic map(<>)
/model/vhdl/packages/pkg-resolved.vhdl
0,0 → 1,106
/* Tauhop resolution package
Description
Defines common resolution functions.
To Do:
Author(s):
- Daniel C.K. Kho, daniel.kho@tauhop.com
Copyright (C) 2012-2014 Authors and Tauhop Solutions.
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.
This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
package resolved is
generic(type t);
/* unresolved vector of generic type. */
type t_vector is array(natural range <>) of t;
type unsigned32_vector is array (natural range <>) of unsigned(31 downto 0);
type signed32_vector is array (natural range <>) of signed(31 downto 0);
type integer_vector is array(natural range <>) of integer;
function resolve(s:t_vector) return t;
function resolve(s:unsigned32_vector) return unsigned;
function resolve(s:integer_vector) return integer;
function to_int(u_unsigned: unresolved_unsigned) return integer;
end package resolved;
 
package body resolved is
function resolve(s: t_vector) return t is
variable result: t;
begin
for i in s'range loop
for j in s(i)'range loop
if is_LH01(s(i)(j)) then
if is_LH01(result(j)) then
report "Multiple driving signals detected." severity warning;
end if;
result(j) := s(i)(j);
end if;
end loop;
end loop;
end function resolve;
function resolve(s: unsigned32_vector) return unsigned is
variable result: unsigned(31 downto 0);
begin
for i in s'range loop
if s(i) /= 0 then
if result /= 0 then
report "Multiple driving signals on unsigned32" severity warning;
end if;
result := s(i);
end if;
end loop;
return result;
end function resolve;
function resolve(s:integer_vector) return integer is
variable result:integer:=0;
begin
for i in s'range loop
if s(i) /= 0 then
if result /= 0 then
report "Multiple driving signals on integer" severity warning;
end if;
result := s(i);
end if;
end loop;
return result;
end function resolve;
function to_int(u_unsigned: unresolved_unsigned) return integer is
variable result: natural:=0;
begin
for i in u_unsigned'range loop
result := result+result;
if u_unsigned(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function to_int;
end package body resolved;

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