OpenCores
URL https://opencores.org/ocsvn/wb_fifo/wb_fifo/trunk

Subversion Repositories wb_fifo

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /wb_fifo
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/trunk/model/vhdl/fifo.vhdl
0,0 → 1,115
/*
This file is part of the Memories project:
http://opencores.org/project,wb_fifo
Description
FIFO memory model.
To Do:
Author(s):
- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
Copyright (C) 2012-2013 Authors and OPENCORES.ORG.
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.
This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
library tauhop;
--package fifoTypes is new tauhop.types generic map(t_data=>unsigned(31 downto 0));
use tauhop.fifoTransactor.all;
 
--library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
--library tauhop; use tauhop.fifoTypes.all;
entity fifo is
generic(memoryDepth:positive);
port(clk,reset:in std_ulogic;
fifoInterface:inout t_fifoTransactor
);
end entity fifo;
 
architecture rtl of fifo is
type t_memory is array(memoryDepth-1 downto 0) of i_transactor.t_msg;
signal memory:t_memory;
signal ptr:natural range 0 to memoryDepth-1;
signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
signal write,read:boolean;
begin
controller: process(reset,clk) is begin
if reset then fifoInterface.readResponse.message<=(others=>'Z');
elsif falling_edge(clk) then
if fifoInterface.writeRequest.trigger xor i_writeRequest.trigger then
memory(ptr)<=fifoInterface.writeRequest.message;
end if;
if fifoInterface.readRequest.trigger xor i_readRequest.trigger then
fifoInterface.readResponse.message<=memory(ptr);
end if;
end if;
end process controller;
write<=fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
read<=fifoInterface.readRequest.trigger xor i_readRequest.trigger;
addrPointer: process(reset,clk) is begin
if reset then ptr<=0;
elsif falling_edge(clk) then
/* Increment or decrement the address pointer only when write or read is HIGH;
do nothing when both are HIGH or when both are LOW.
*/
if write xor read then
if write then
if ptr<memoryDepth-1 then ptr<=ptr+1; end if;
end if;
if read then
if ptr>0 then ptr<=ptr-1; end if;
end if;
end if;
end if;
end process addrPointer;
/* Registers and pipelines. */
process(clk) is begin
i_writeRequest<=fifoInterface.writeRequest;
i_readRequest<=fifoInterface.readRequest;
end process;
fifoInterface.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoInterface.pctFilled'length);
process(clk) is begin
if rising_edge(clk) then
fifoInterface.nearFull<=true when fifoInterface.pctFilled>=d"75" and fifoInterface.pctFilled<d"100" else false;
fifoInterface.full<=true when fifoInterface.pctFilled=d"100" else false;
fifoInterface.nearEmpty<=true when fifoInterface.pctFilled<=d"25" and fifoInterface.pctFilled>d"0" else false;
fifoInterface.empty<=true when fifoInterface.pctFilled=d"0" else false;
end if;
end process;
process(clk) is begin
if falling_edge(clk) then
fifoInterface.overflow<=fifoInterface.full and write;
fifoInterface.underflow<=fifoInterface.empty and read;
end if;
end process;
end architecture rtl;
/trunk/model/vhdl/packages/pkg-tlm.vhdl
0,0 → 1,92
/*
This file is part of the AXI4 Transactor and Bus Functional Model
(axi4_tlm_bfm) project:
http://www.opencores.org/project,axi4_tlm_bfm
 
Description
This implements a generic interface for transactors, and has a set
of reusable procedures to read and write from / to a bus. This
interface can be used in many different bus protocols, by means of
instantiating this package. An example implementation for the AXI4
protocol can be found at
pkg-axi-tlm.vhdl
under the axi4_tlm_bfm project.
To Do:
Author(s):
- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
Copyright (C) 2012-2013 Authors and OPENCORES.ORG
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.
This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml.
*/
/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
--use std.textio.all;
 
package tlm is
generic(type t_addr; type t_msg; type t_cnt);
-- /* TODO remove once generic packages are supported. */
-- subtype t_addr is unsigned(31 downto 0);
-- subtype t_msg is signed(63 downto 0);
/* BFM control interface. */
type t_bfm is record
address:t_addr;
message:t_msg;
trigger:boolean;
end record t_bfm;
procedure write(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
);
procedure read(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr -- used only for non-stream interfaces.
);
end package tlm;
 
package body tlm is
procedure write(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
) is begin
request.address<=address;
request.message<=data;
request.trigger<=not request.trigger;
end procedure write;
procedure read(
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr -- used only for non-stream interfaces.
) is begin
request.address<=address;
request.trigger<=not request.trigger;
--report "request.address: " & to_hstring(request.address);
end procedure read;
end package body tlm;
trunk/model/vhdl/packages/pkg-tlm.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/model/vhdl/packages/pkg-fifo-tlm.vhdl =================================================================== --- trunk/model/vhdl/packages/pkg-fifo-tlm.vhdl (nonexistent) +++ trunk/model/vhdl/packages/pkg-fifo-tlm.vhdl (revision 2) @@ -0,0 +1,90 @@ +/* + This file is part of the Memories project: + http://www.opencores.org/project,wb_fifo + + Description + Implementation of FIFO transactor data structures and high-level API. + + To Do: + + Author(s): + - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com + + Copyright (C) 2012-2013 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any + later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml. +*/ +/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */ +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; +--use std.textio.all; +library tauhop; --use tauhop.transactor.all; + +/* Record I/O data structures for AXI interface transactor (block interface). */ +package fifoTLM is + generic( + package i_transactor is new tauhop.tlm generic map(<>) + ); + /* Makes i_transactor.t_addr, i_transactor.t_msg, and i_transactor.t_cnt visible. */ + use i_transactor.all; + + /* FIFO Transactor block interface. */ + type t_fifoTransactor is record + writeRequest,readRequest:t_bfm; + writeResponse,readResponse:t_bfm; + pctFilled:unsigned(7 downto 0); + nearFull,full:boolean; + nearEmpty,empty:boolean; + overflow,underflow:boolean; + end record t_fifoTransactor; +end package fifoTLM; + +package body fifoTLM is +end package body fifoTLM; + + +/* FIFO Transactor API. + * Generally, transactors are high-level bus interface models that perform + * read/write transactions to/from the bus. These models are not concerned + * with the low-level implementation of the bus protocol. However, the + * TLM models encapsulate the lower-level models known as the BFM. + * fifoTLM uses generic package tauhop.tlm, hence inherits basic TLM types and + * procedures generally used in any messaging system (i.e. address and message + * information, and bus read/write methods). It also extends the tauhop.tlm + * package with application-specific types, such as record structures specific + * to the AXI protocol. + * fifoTransactor instantiates the fifoTLM, and assigns specific types to the + * transactor model. + */ +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; +library tauhop; +package transactor is new tauhop.tlm generic map( + t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces. + t_msg=>unsigned(63 downto 0), + t_cnt=>unsigned(127 downto 0) +); + +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; +library tauhop; use tauhop.transactor.all; +package fifoTransactor is new tauhop.fifoTLM generic map( + --t_data=>unsigned(31 downto 0), + i_transactor=>tauhop.transactor +);
trunk/model/vhdl/packages/pkg-fifo-tlm.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/workspaces/questa/waves.do =================================================================== --- trunk/workspaces/questa/waves.do (nonexistent) +++ trunk/workspaces/questa/waves.do (revision 2) @@ -0,0 +1,28 @@ +configure wave -signalnamewidth 1 + +add wave -position end sim:/testbench/clk +add wave -position end sim:/testbench/reset +add wave -position end sim:/testbench/fifoInterface.writeRequest +add wave -position end sim:/testbench/fifoInterface.readRequest +add wave -position end sim:/testbench/memoryDepth +add wave -position end -hexadecimal -expand sim:/testbench/fifoInterface.writeRequest +#add wave -position end -hexadecimal -expand sim:/testbench/duv/i_writeRequest +add wave -position end -hexadecimal sim:/testbench/fifoInterface.writeResponse +add wave -position end -hexadecimal sim:/testbench/fifoInterface.readRequest +add wave -position end -hexadecimal sim:/testbench/fifoInterface.readResponse +add wave -position end -hexadecimal sim:/testbench/duv/ptr +add wave -position end -decimal sim:/testbench/duv/fifoInterface.pctFilled +add wave -position end sim:/testbench/duv/write +add wave -position end sim:/testbench/duv/read +add wave -position end sim:/testbench/duv/fifoInterface.nearFull +add wave -position end sim:/testbench/duv/fifoInterface.full +add wave -position end sim:/testbench/duv/fifoInterface.nearEmpty +add wave -position end sim:/testbench/duv/fifoInterface.empty +add wave -position end sim:/testbench/duv/fifoInterface.overflow +add wave -position end sim:/testbench/duv/fifoInterface.underflow +add wave -position end -hexadecimal sim:/testbench/duv/memory + +run 80 ns; + +wave zoomfull +#.wave.tree zoomfull # with some versions of ModelSim
trunk/workspaces/questa/waves.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/workspaces/questa/simulate.sh =================================================================== --- trunk/workspaces/questa/simulate.sh (nonexistent) +++ trunk/workspaces/questa/simulate.sh (revision 2) @@ -0,0 +1,65 @@ +#!/bin/bash +# +# Example bash script for Mentor Graphics QuestaSim/ModelSim simulation. +# +# Author(s): +# - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com +# +# Copyright (C) 2012-2013 Authors and OPENCORES.ORG +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# This notice and disclaimer must be retained as part of this text at all times. +# +# @dependencies: +# @designer: Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] +# @history: @see Mercurial log for full list of changes. +# +# @Description: +# + +#read -p "press Enter to run full simulation now, or Ctrl-C to exit: "; +echo $(date "+[%Y-%m-%d %H:%M:%S]: Removing previously-generated files and folders..."); +rm -rf modelsim.ini ./simulate.log ./work ./altera ./osvvm ./tauhop; + +echo $(date "+[%Y-%m-%d %H:%M:%S]: Remove successful."); +echo $(date "+[%Y-%m-%d %H:%M:%S]: Compiling project..."); +vlib work; vmap work work; +vlib tauhop; vmap tauhop tauhop; +vlib osvvm; vmap osvvm osvvm; + +vcom -2008 -work osvvm ../../model/vhdl/packages/os-vvm/SortListPkg_int.vhd \ + ../../model/vhdl/packages/os-vvm/RandomBasePkg.vhd \ + ../../model/vhdl/packages/os-vvm/RandomPkg.vhd \ + ../../model/vhdl/packages/os-vvm/CoveragePkg.vhd \ + | tee -ai ./simulate.log; + +#vcom -2008 -work tauhop ../../pkg-types.vhdl \ +vcom -2008 -work tauhop ../../model/vhdl/packages/pkg-tlm.vhdl \ + ../../model/vhdl/packages/pkg-fifo-tlm.vhdl \ + ../../model/vhdl/fifo.vhdl \ + | tee -ai ./simulate.log; + +vcom -2008 -work work ../../tester/tb.vhdl \ + | tee -ai ./simulate.log; + +errorStr=`grep "\*\* Error: " ./simulate.log` +if [ `echo ${#errorStr}` -gt 0 ] +then echo "Errors exist. Refer simulate.log for more details. Exiting."; exit; +else + vsim -t ps -do ./waves.do -voptargs="+acc" "work.testbench(simulation)"; + #vsim -t ps -voptargs="+acc" "tauhop.fifo(rtl)"; + #vsim -t ps -voptargs="+acc" "work.testbench(simulation)"; + echo $(date "+[%Y-%m-%d %H:%M:%S]: simulation loaded."); +fi
trunk/workspaces/questa/simulate.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tester/tb.vhdl =================================================================== --- trunk/tester/tb.vhdl (nonexistent) +++ trunk/tester/tb.vhdl (revision 2) @@ -0,0 +1,114 @@ +/* + This file is part of the Memories project: + http://www.opencores.org/project,wb_fifo + + Description + Testbench for generic FIFO project. + + To Do: + + Author(s): + - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com + + Copyright (C) 2012-2013 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any + later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml. +*/ +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; +--library tauhop; use tauhop.fifoTypes.all; +library tauhop; use tauhop.fifoTransactor.all; +library osvvm; use osvvm.RandomPkg.all; +entity testbench is end entity testbench; + +architecture simulation of testbench is + constant period:time:=10 ps; + constant memoryDepth:positive:=16; + signal reset,clk:std_ulogic:='0'; + --signal write,read:boolean; + --signal d,q:t_data; + + /* BFM signalling. */ + --signal readRequest,writeRequest:i_transactor.t_bfm; + signal fifoInterface:t_fifoTransactor; +begin + --duv: entity tauhop.fifo(rtl) generic map(memoryDepth=>memoryDepth) port map(clk=>clk, reset=>reset, write=>write, read=>read, d=>d, q=>q); + duv: entity tauhop.fifo(rtl) generic map(memoryDepth=>memoryDepth) port map(clk=>clk, reset=>reset, fifoInterface=>fifoInterface); + + clk<=not clk after period/2; + + process is begin + reset<='1'; +-- fifoInterface.write<=false; + wait for 30 ps; + + reset<='0'; + wait until falling_edge(clk); + +-- fifoInterface.write<=true; + wait for memoryDepth*period; + +-- fifoInterface.write<=false; + wait; + end process; + + /* Read operation. */ +/* process is begin + fifoInterface.read<=false; + wait for 50 ps; + fifoInterface.read<=true; + wait; + end process; +*/ + /* Write operation. */ + process(reset,clk) is + /* Local procedures to map BFM signals with the package procedure. */ + --procedure read(address:in i_transactor.t_addr) is begin + procedure read is begin + i_transactor.read(request=>fifoInterface.readRequest, address=>(others=>'-')); + end procedure read; + + procedure write(data:in i_transactor.t_msg) is begin + i_transactor.write(request=>fifoInterface.writeRequest, address=>(others=>'-'), data=>data); + end procedure write; + + variable rv:RandomPType; + variable cnt:unsigned(7 downto 0); + begin + if reset then + rv.InitSeed(rv'instance_name); + cnt:=(others=>'0'); + elsif rising_edge(clk) then + /* if fifoInterface.write then + --fifoInterface.d<=rv.RandUnsigned(fifoInterface.d'length); + else fifoInterface.d<=(others=>'Z'); + end if; + */ + + if cnt
trunk/tester/tb.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.