URL
https://opencores.org/ocsvn/wb_size_bridge/wb_size_bridge/trunk
Subversion Repositories wb_size_bridge
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/wb_size_bridge/trunk/tb/test/debug
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/tb_dut.v
1,152 → 1,175
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`timescale 1ns/10ps |
|
|
module tb_dut( |
input tb_clk, |
input tb_rst |
); |
|
|
wire wb_hi_clk = tb_clk; |
wire wb_hi_rst = tb_rst; |
|
wire [31:0] wb_hi_dat_i, wb_hi_dat_o; |
wire [31:0] wb_hi_adr_o; |
wire wb_hi_cyc_o, wb_hi_stb_o; |
wire wb_hi_we_o; |
wire [ 3:0] wb_hi_sel_o; |
wire wb_hi_ack_i, wb_hi_err_i, wb_hi_rty_i; |
|
wire wb_lo_clk_o; |
wire wb_lo_rst_o; |
|
wire [15:0] wb_lo_dat_i, wb_lo_dat_o; |
wire [31:0] wb_lo_adr_o; |
wire wb_lo_cyc_o, wb_lo_stb_o; |
wire wb_lo_we_o; |
wire [1:0] wb_lo_sel_o; |
wire wb_lo_ack_i, wb_lo_err_i, wb_lo_rty_i; |
wire lo_byte_if_i; |
|
|
// -------------------------------------------------------------------- |
// wb_hi_master_model |
wb_master_model wbm( |
.clk(wb_hi_clk), |
.rst(wb_hi_rst), |
.adr(wb_hi_adr_o), |
.din(wb_hi_dat_i), |
.dout(wb_hi_dat_o), |
.cyc(wb_hi_cyc_o), |
.stb(wb_hi_stb_o), |
.we(wb_hi_we_o), |
.sel(wb_hi_sel_o), |
.ack(wb_hi_ack_i), |
.err(wb_hi_err_i), |
.rty(wb_hi_rty_i) |
); |
|
|
// -------------------------------------------------------------------- |
// wb_hi_size_bridge |
wb_size_bridge i_wb_size_bridge( |
.wb_hi_clk_i(wb_hi_clk), |
.wb_hi_rst_i(wb_hi_rst), |
.wb_hi_dat_o(wb_hi_dat_i), |
.wb_hi_dat_i(wb_hi_dat_o), |
.wb_hi_adr_i(wb_hi_adr_o), |
.wb_hi_cyc_i(wb_hi_cyc_o), |
.wb_hi_we_i(wb_hi_we_o), |
.wb_hi_stb_i(wb_hi_stb_o), |
.wb_hi_sel_i(wb_hi_sel_o), |
.wb_hi_ack_o(wb_hi_ack_i), |
.wb_hi_err_o(wb_hi_err_i), |
.wb_hi_rty_o(wb_hi_rty_i), |
|
.wb_lo_clk_o(wb_lo_clk_o), |
.wb_lo_rst_o(wb_lo_rst_o), |
.wb_lo_dat_o(wb_lo_dat_o), |
.wb_lo_dat_i(wb_lo_dat_i), |
.wb_lo_adr_o(wb_lo_adr_o), |
.wb_lo_cyc_o(wb_lo_cyc_o), |
.wb_lo_we_o(wb_lo_we_o), |
.wb_lo_stb_o(wb_lo_stb_o), |
.wb_lo_sel_o(wb_lo_sel_o), |
.wb_lo_ack_i(wb_lo_ack_i), |
.wb_lo_err_i(wb_lo_err_i), |
.wb_lo_rty_i(wb_lo_rty_i), |
.lo_byte_if_i(lo_byte_if_i) |
); |
|
|
// -------------------------------------------------------------------- |
// wb_slave_model |
|
wire slave_08_bit_hit = (wb_lo_adr_o[31:24] == 8'h60) & wb_lo_cyc_o; |
|
wire [15:0] slave_08_bit_dat_o; |
wire [15:0] slave_16_bit_dat_o; |
|
assign wb_lo_dat_i[15:0] = slave_08_bit_hit ? slave_08_bit_dat_o : slave_16_bit_dat_o; |
|
wire slave_08_bit_ack_o; |
wire slave_08_bit_err_o; |
wire slave_08_bit_rty_o; |
|
wire slave_16_bit_ack_o; |
wire slave_16_bit_err_o; |
wire slave_16_bit_rty_o; |
|
assign wb_lo_ack_i = slave_08_bit_hit ? slave_08_bit_ack_o : slave_16_bit_ack_o; |
assign wb_lo_err_i = slave_08_bit_hit ? slave_08_bit_err_o : slave_16_bit_err_o; |
assign wb_lo_rty_i = slave_08_bit_hit ? slave_08_bit_rty_o : slave_16_bit_rty_o; |
|
wire slave_08_bit_cyc_i = wb_lo_cyc_o & slave_08_bit_hit; |
wire slave_08_bit_stb_i = wb_lo_stb_o & slave_08_bit_hit; |
|
wire slave_16_bit_cyc_i = wb_lo_cyc_o & ~slave_08_bit_hit; |
wire slave_16_bit_stb_i = wb_lo_stb_o & ~slave_08_bit_hit; |
|
assign lo_byte_if_i = slave_08_bit_hit; |
|
wb_slave_model #(.DWIDTH(8), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_08_bit.txt") ) |
wb_slave_08_bit( |
.clk_i(wb_lo_clk_o), |
.rst_i(wb_lo_rst_o), |
.dat_o(slave_08_bit_dat_o[7:0]), |
.dat_i(wb_lo_dat_o[7:0]), |
.adr_i(wb_lo_adr_o[4:0]), |
.cyc_i(slave_08_bit_cyc_i), |
.stb_i(slave_08_bit_stb_i), |
.we_i(wb_lo_we_o), |
.sel_i(wb_lo_sel_o[0]), |
.ack_o(slave_08_bit_ack_o), |
.err_o(slave_08_bit_err_o), |
.rty_o(slave_08_bit_rty_o) |
); |
|
|
wb_slave_model #(.DWIDTH(16), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_16_bit.txt") ) |
wb_slave_16_bit( |
.clk_i(wb_lo_clk_o), |
.rst_i(wb_lo_rst_o), |
.dat_o(slave_16_bit_dat_o), |
.dat_i(wb_lo_dat_o[15:0]), |
.adr_i(wb_lo_adr_o[4:0]), |
.cyc_i(slave_16_bit_cyc_i), |
.stb_i(slave_16_bit_stb_i), |
.we_i(wb_lo_we_o), |
.sel_i(wb_lo_sel_o), |
.ack_o(slave_16_bit_ack_o), |
.err_o(slave_16_bit_err_o), |
.rty_o(slave_16_bit_rty_o) |
); |
|
|
endmodule |
|
|
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ns/10ps |
|
|
module tb_dut( |
input tb_clk, |
input tb_rst |
); |
|
|
wire wb_hi_clk = tb_clk; |
wire wb_hi_rst = tb_rst; |
|
wire [31:0] wb_hi_dat_i, wb_hi_dat_o; |
wire [31:0] wb_hi_adr_o; |
wire wb_hi_cyc_o, wb_hi_stb_o; |
wire wb_hi_we_o; |
wire [ 3:0] wb_hi_sel_o; |
wire wb_hi_ack_i, wb_hi_err_i, wb_hi_rty_i; |
|
wire wb_lo_clk_o; |
wire wb_lo_rst_o; |
|
wire [15:0] wb_lo_dat_i, wb_lo_dat_o; |
wire [31:0] wb_lo_adr_o; |
wire wb_lo_cyc_o, wb_lo_stb_o; |
wire wb_lo_we_o; |
wire [1:0] wb_lo_sel_o; |
wire wb_lo_ack_i, wb_lo_err_i, wb_lo_rty_i; |
wire lo_byte_if_i; |
|
|
// -------------------------------------------------------------------- |
// wb_hi_master_model |
wb_master_model wbm( |
.clk(wb_hi_clk), |
.rst(wb_hi_rst), |
.adr(wb_hi_adr_o), |
.din(wb_hi_dat_i), |
.dout(wb_hi_dat_o), |
.cyc(wb_hi_cyc_o), |
.stb(wb_hi_stb_o), |
.we(wb_hi_we_o), |
.sel(wb_hi_sel_o), |
.ack(wb_hi_ack_i), |
.err(wb_hi_err_i), |
.rty(wb_hi_rty_i) |
); |
|
|
// -------------------------------------------------------------------- |
// wb_hi_size_bridge |
wb_size_bridge i_wb_size_bridge( |
.wb_hi_clk_i(wb_hi_clk), |
.wb_hi_rst_i(wb_hi_rst), |
.wb_hi_dat_o(wb_hi_dat_i), |
.wb_hi_dat_i(wb_hi_dat_o), |
.wb_hi_adr_i(wb_hi_adr_o), |
.wb_hi_cyc_i(wb_hi_cyc_o), |
.wb_hi_we_i(wb_hi_we_o), |
.wb_hi_stb_i(wb_hi_stb_o), |
.wb_hi_sel_i(wb_hi_sel_o), |
.wb_hi_ack_o(wb_hi_ack_i), |
.wb_hi_err_o(wb_hi_err_i), |
.wb_hi_rty_o(wb_hi_rty_i), |
|
.wb_lo_clk_o(wb_lo_clk_o), |
.wb_lo_rst_o(wb_lo_rst_o), |
.wb_lo_dat_o(wb_lo_dat_o), |
.wb_lo_dat_i(wb_lo_dat_i), |
.wb_lo_adr_o(wb_lo_adr_o), |
.wb_lo_cyc_o(wb_lo_cyc_o), |
.wb_lo_we_o(wb_lo_we_o), |
.wb_lo_stb_o(wb_lo_stb_o), |
.wb_lo_sel_o(wb_lo_sel_o), |
.wb_lo_ack_i(wb_lo_ack_i), |
.wb_lo_err_i(wb_lo_err_i), |
.wb_lo_rty_i(wb_lo_rty_i), |
.lo_byte_if_i(lo_byte_if_i) |
); |
|
|
// -------------------------------------------------------------------- |
// wb_slave_model |
|
wire slave_08_bit_hit = (wb_lo_adr_o[31:24] == 8'h60) & wb_lo_cyc_o; |
|
wire [15:0] slave_08_bit_dat_o; |
wire [15:0] slave_16_bit_dat_o; |
|
assign wb_lo_dat_i[15:0] = slave_08_bit_hit ? slave_08_bit_dat_o : slave_16_bit_dat_o; |
|
wire slave_08_bit_ack_o; |
wire slave_08_bit_err_o; |
wire slave_08_bit_rty_o; |
|
wire slave_16_bit_ack_o; |
wire slave_16_bit_err_o; |
wire slave_16_bit_rty_o; |
|
assign wb_lo_ack_i = slave_08_bit_hit ? slave_08_bit_ack_o : slave_16_bit_ack_o; |
assign wb_lo_err_i = slave_08_bit_hit ? slave_08_bit_err_o : slave_16_bit_err_o; |
assign wb_lo_rty_i = slave_08_bit_hit ? slave_08_bit_rty_o : slave_16_bit_rty_o; |
|
wire slave_08_bit_cyc_i = wb_lo_cyc_o & slave_08_bit_hit; |
wire slave_08_bit_stb_i = wb_lo_stb_o & slave_08_bit_hit; |
|
wire slave_16_bit_cyc_i = wb_lo_cyc_o & ~slave_08_bit_hit; |
wire slave_16_bit_stb_i = wb_lo_stb_o & ~slave_08_bit_hit; |
|
assign lo_byte_if_i = slave_08_bit_hit; |
|
wb_slave_model #(.DWIDTH(8), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_08_bit.txt") ) |
wb_slave_08_bit( |
.clk_i(wb_lo_clk_o), |
.rst_i(wb_lo_rst_o), |
.dat_o(slave_08_bit_dat_o[7:0]), |
.dat_i(wb_lo_dat_o[7:0]), |
.adr_i(wb_lo_adr_o[4:0]), |
.cyc_i(slave_08_bit_cyc_i), |
.stb_i(slave_08_bit_stb_i), |
.we_i(wb_lo_we_o), |
.sel_i(wb_lo_sel_o[0]), |
.ack_o(slave_08_bit_ack_o), |
.err_o(slave_08_bit_err_o), |
.rty_o(slave_08_bit_rty_o) |
); |
|
|
wb_slave_model #(.DWIDTH(16), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_16_bit.txt") ) |
wb_slave_16_bit( |
.clk_i(wb_lo_clk_o), |
.rst_i(wb_lo_rst_o), |
.dat_o(slave_16_bit_dat_o), |
.dat_i(wb_lo_dat_o[15:0]), |
.adr_i(wb_lo_adr_o[4:0]), |
.cyc_i(slave_16_bit_cyc_i), |
.stb_i(slave_16_bit_stb_i), |
.we_i(wb_lo_we_o), |
.sel_i(wb_lo_sel_o), |
.ack_o(slave_16_bit_ack_o), |
.err_o(slave_16_bit_err_o), |
.rty_o(slave_16_bit_rty_o) |
); |
|
|
endmodule |
|
|
/tb_top.v
1,132 → 1,155
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`timescale 1ns/10ps |
|
|
module tb_top(); |
|
parameter CLK_PERIOD = 10; |
|
reg tb_clk, tb_rst; |
|
initial |
begin |
tb_clk <= 1'b1; |
tb_rst <= 1'b1; |
|
#(CLK_PERIOD); #(CLK_PERIOD/3); |
tb_rst = 1'b0; |
|
end |
|
always |
#(CLK_PERIOD/2) tb_clk = ~tb_clk; |
|
// -------------------------------------------------------------------- |
// tb_dut |
tb_dut dut( tb_clk, tb_rst ); |
|
|
// -------------------------------------------------------------------- |
// insert test below |
|
initial |
begin |
|
wait( ~tb_rst ); |
|
repeat(2) @(posedge tb_clk); |
|
// 8 bit if |
$display("\n^^^- testing 8 bit interface\n"); |
|
dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988); |
dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc); |
|
dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef); |
dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f); |
|
dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f); |
|
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx); |
|
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx); |
|
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx); |
|
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx); |
|
// 16 bit if |
$display("\n^^^- testing 16 bit interface\n"); |
|
dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988); |
dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc); |
|
dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef); |
dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f); |
|
dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f); |
|
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx); |
|
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx); |
|
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx); |
|
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx); |
|
// do illegal byte boundary access |
$display("\n^^^- testing illegal byte boundary access\n"); |
dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx); |
|
repeat(2) @(posedge tb_clk); |
|
$display("\n^^^---------------------------------\n"); |
$display("^^^- Testbench done. %t.\n", $time); |
|
$stop(); |
|
end |
|
endmodule |
|
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ns/10ps |
|
|
module tb_top(); |
|
parameter CLK_PERIOD = 10; |
|
reg tb_clk, tb_rst; |
|
initial |
begin |
tb_clk <= 1'b1; |
tb_rst <= 1'b1; |
|
#(CLK_PERIOD); #(CLK_PERIOD/3); |
tb_rst = 1'b0; |
|
end |
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always |
#(CLK_PERIOD/2) tb_clk = ~tb_clk; |
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// -------------------------------------------------------------------- |
// tb_dut |
tb_dut dut( tb_clk, tb_rst ); |
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// -------------------------------------------------------------------- |
// insert test below |
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initial |
begin |
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wait( ~tb_rst ); |
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repeat(2) @(posedge tb_clk); |
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// 8 bit if |
$display("\n^^^- testing 8 bit interface\n"); |
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dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988); |
dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc); |
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dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef); |
dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f); |
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dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f); |
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dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx); |
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dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx); |
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx); |
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx); |
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// 16 bit if |
$display("\n^^^- testing 16 bit interface\n"); |
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dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988); |
dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc); |
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dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef); |
dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f); |
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dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d); |
dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e); |
dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f); |
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx); |
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx); |
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dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx); |
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dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx); |
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx); |
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// do illegal byte boundary access |
$display("\n^^^- testing illegal byte boundary access\n"); |
dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx); |
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repeat(2) @(posedge tb_clk); |
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$display("\n^^^---------------------------------\n"); |
$display("^^^- Testbench done. %t.\n", $time); |
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$stop(); |
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end |
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endmodule |
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