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URL https://opencores.org/ocsvn/wb_size_bridge/wb_size_bridge/trunk

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Rev 4 → Rev 5

/test/debug/tb_dut.v
1,175 → 1,152
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ns/10ps
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
 
 
wire wb_hi_clk = tb_clk;
wire wb_hi_rst = tb_rst;
 
wire [31:0] wb_hi_dat_i, wb_hi_dat_o;
wire [31:0] wb_hi_adr_o;
wire wb_hi_cyc_o, wb_hi_stb_o;
wire wb_hi_we_o;
wire [ 3:0] wb_hi_sel_o;
wire wb_hi_ack_i, wb_hi_err_i, wb_hi_rty_i;
 
wire wb_lo_clk_o;
wire wb_lo_rst_o;
 
wire [15:0] wb_lo_dat_i, wb_lo_dat_o;
wire [31:0] wb_lo_adr_o;
wire wb_lo_cyc_o, wb_lo_stb_o;
wire wb_lo_we_o;
wire [1:0] wb_lo_sel_o;
wire wb_lo_ack_i, wb_lo_err_i, wb_lo_rty_i;
wire lo_byte_if_i;
 
 
// --------------------------------------------------------------------
// wb_hi_master_model
wb_master_model wbm(
.clk(wb_hi_clk),
.rst(wb_hi_rst),
.adr(wb_hi_adr_o),
.din(wb_hi_dat_i),
.dout(wb_hi_dat_o),
.cyc(wb_hi_cyc_o),
.stb(wb_hi_stb_o),
.we(wb_hi_we_o),
.sel(wb_hi_sel_o),
.ack(wb_hi_ack_i),
.err(wb_hi_err_i),
.rty(wb_hi_rty_i)
);
 
 
// --------------------------------------------------------------------
// wb_hi_size_bridge
wb_size_bridge i_wb_size_bridge(
.wb_hi_clk_i(wb_hi_clk),
.wb_hi_rst_i(wb_hi_rst),
.wb_hi_dat_o(wb_hi_dat_i),
.wb_hi_dat_i(wb_hi_dat_o),
.wb_hi_adr_i(wb_hi_adr_o),
.wb_hi_cyc_i(wb_hi_cyc_o),
.wb_hi_we_i(wb_hi_we_o),
.wb_hi_stb_i(wb_hi_stb_o),
.wb_hi_sel_i(wb_hi_sel_o),
.wb_hi_ack_o(wb_hi_ack_i),
.wb_hi_err_o(wb_hi_err_i),
.wb_hi_rty_o(wb_hi_rty_i),
.wb_lo_clk_o(wb_lo_clk_o),
.wb_lo_rst_o(wb_lo_rst_o),
.wb_lo_dat_o(wb_lo_dat_o),
.wb_lo_dat_i(wb_lo_dat_i),
.wb_lo_adr_o(wb_lo_adr_o),
.wb_lo_cyc_o(wb_lo_cyc_o),
.wb_lo_we_o(wb_lo_we_o),
.wb_lo_stb_o(wb_lo_stb_o),
.wb_lo_sel_o(wb_lo_sel_o),
.wb_lo_ack_i(wb_lo_ack_i),
.wb_lo_err_i(wb_lo_err_i),
.wb_lo_rty_i(wb_lo_rty_i),
.lo_byte_if_i(lo_byte_if_i)
);
// --------------------------------------------------------------------
// wb_slave_model
wire slave_08_bit_hit = (wb_lo_adr_o[31:24] == 8'h60) & wb_lo_cyc_o;
wire [15:0] slave_08_bit_dat_o;
wire [15:0] slave_16_bit_dat_o;
assign wb_lo_dat_i[15:0] = slave_08_bit_hit ? slave_08_bit_dat_o : slave_16_bit_dat_o;
wire slave_08_bit_ack_o;
wire slave_08_bit_err_o;
wire slave_08_bit_rty_o;
wire slave_16_bit_ack_o;
wire slave_16_bit_err_o;
wire slave_16_bit_rty_o;
assign wb_lo_ack_i = slave_08_bit_hit ? slave_08_bit_ack_o : slave_16_bit_ack_o;
assign wb_lo_err_i = slave_08_bit_hit ? slave_08_bit_err_o : slave_16_bit_err_o;
assign wb_lo_rty_i = slave_08_bit_hit ? slave_08_bit_rty_o : slave_16_bit_rty_o;
wire slave_08_bit_cyc_i = wb_lo_cyc_o & slave_08_bit_hit;
wire slave_08_bit_stb_i = wb_lo_stb_o & slave_08_bit_hit;
wire slave_16_bit_cyc_i = wb_lo_cyc_o & ~slave_08_bit_hit;
wire slave_16_bit_stb_i = wb_lo_stb_o & ~slave_08_bit_hit;
assign lo_byte_if_i = slave_08_bit_hit;
wb_slave_model #(.DWIDTH(8), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_08_bit.txt") )
wb_slave_08_bit(
.clk_i(wb_lo_clk_o),
.rst_i(wb_lo_rst_o),
.dat_o(slave_08_bit_dat_o[7:0]),
.dat_i(wb_lo_dat_o[7:0]),
.adr_i(wb_lo_adr_o[4:0]),
.cyc_i(slave_08_bit_cyc_i),
.stb_i(slave_08_bit_stb_i),
.we_i(wb_lo_we_o),
.sel_i(wb_lo_sel_o[0]),
.ack_o(slave_08_bit_ack_o),
.err_o(slave_08_bit_err_o),
.rty_o(slave_08_bit_rty_o)
);
wb_slave_model #(.DWIDTH(16), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_16_bit.txt") )
wb_slave_16_bit(
.clk_i(wb_lo_clk_o),
.rst_i(wb_lo_rst_o),
.dat_o(slave_16_bit_dat_o),
.dat_i(wb_lo_dat_o[15:0]),
.adr_i(wb_lo_adr_o[4:0]),
.cyc_i(slave_16_bit_cyc_i),
.stb_i(slave_16_bit_stb_i),
.we_i(wb_lo_we_o),
.sel_i(wb_lo_sel_o),
.ack_o(slave_16_bit_ack_o),
.err_o(slave_16_bit_err_o),
.rty_o(slave_16_bit_rty_o)
);
 
endmodule
 
 
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
 
 
wire wb_hi_clk = tb_clk;
wire wb_hi_rst = tb_rst;
 
wire [31:0] wb_hi_dat_i, wb_hi_dat_o;
wire [31:0] wb_hi_adr_o;
wire wb_hi_cyc_o, wb_hi_stb_o;
wire wb_hi_we_o;
wire [ 3:0] wb_hi_sel_o;
wire wb_hi_ack_i, wb_hi_err_i, wb_hi_rty_i;
 
wire wb_lo_clk_o;
wire wb_lo_rst_o;
 
wire [15:0] wb_lo_dat_i, wb_lo_dat_o;
wire [31:0] wb_lo_adr_o;
wire wb_lo_cyc_o, wb_lo_stb_o;
wire wb_lo_we_o;
wire [1:0] wb_lo_sel_o;
wire wb_lo_ack_i, wb_lo_err_i, wb_lo_rty_i;
wire lo_byte_if_i;
 
 
// --------------------------------------------------------------------
// wb_hi_master_model
wb_master_model wbm(
.clk(wb_hi_clk),
.rst(wb_hi_rst),
.adr(wb_hi_adr_o),
.din(wb_hi_dat_i),
.dout(wb_hi_dat_o),
.cyc(wb_hi_cyc_o),
.stb(wb_hi_stb_o),
.we(wb_hi_we_o),
.sel(wb_hi_sel_o),
.ack(wb_hi_ack_i),
.err(wb_hi_err_i),
.rty(wb_hi_rty_i)
);
 
 
// --------------------------------------------------------------------
// wb_hi_size_bridge
wb_size_bridge i_wb_size_bridge(
.wb_hi_clk_i(wb_hi_clk),
.wb_hi_rst_i(wb_hi_rst),
.wb_hi_dat_o(wb_hi_dat_i),
.wb_hi_dat_i(wb_hi_dat_o),
.wb_hi_adr_i(wb_hi_adr_o),
.wb_hi_cyc_i(wb_hi_cyc_o),
.wb_hi_we_i(wb_hi_we_o),
.wb_hi_stb_i(wb_hi_stb_o),
.wb_hi_sel_i(wb_hi_sel_o),
.wb_hi_ack_o(wb_hi_ack_i),
.wb_hi_err_o(wb_hi_err_i),
.wb_hi_rty_o(wb_hi_rty_i),
.wb_lo_clk_o(wb_lo_clk_o),
.wb_lo_rst_o(wb_lo_rst_o),
.wb_lo_dat_o(wb_lo_dat_o),
.wb_lo_dat_i(wb_lo_dat_i),
.wb_lo_adr_o(wb_lo_adr_o),
.wb_lo_cyc_o(wb_lo_cyc_o),
.wb_lo_we_o(wb_lo_we_o),
.wb_lo_stb_o(wb_lo_stb_o),
.wb_lo_sel_o(wb_lo_sel_o),
.wb_lo_ack_i(wb_lo_ack_i),
.wb_lo_err_i(wb_lo_err_i),
.wb_lo_rty_i(wb_lo_rty_i),
.lo_byte_if_i(lo_byte_if_i)
);
// --------------------------------------------------------------------
// wb_slave_model
wire slave_08_bit_hit = (wb_lo_adr_o[31:24] == 8'h60) & wb_lo_cyc_o;
wire [15:0] slave_08_bit_dat_o;
wire [15:0] slave_16_bit_dat_o;
assign wb_lo_dat_i[15:0] = slave_08_bit_hit ? slave_08_bit_dat_o : slave_16_bit_dat_o;
wire slave_08_bit_ack_o;
wire slave_08_bit_err_o;
wire slave_08_bit_rty_o;
wire slave_16_bit_ack_o;
wire slave_16_bit_err_o;
wire slave_16_bit_rty_o;
assign wb_lo_ack_i = slave_08_bit_hit ? slave_08_bit_ack_o : slave_16_bit_ack_o;
assign wb_lo_err_i = slave_08_bit_hit ? slave_08_bit_err_o : slave_16_bit_err_o;
assign wb_lo_rty_i = slave_08_bit_hit ? slave_08_bit_rty_o : slave_16_bit_rty_o;
wire slave_08_bit_cyc_i = wb_lo_cyc_o & slave_08_bit_hit;
wire slave_08_bit_stb_i = wb_lo_stb_o & slave_08_bit_hit;
wire slave_16_bit_cyc_i = wb_lo_cyc_o & ~slave_08_bit_hit;
wire slave_16_bit_stb_i = wb_lo_stb_o & ~slave_08_bit_hit;
assign lo_byte_if_i = slave_08_bit_hit;
wb_slave_model #(.DWIDTH(8), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_08_bit.txt") )
wb_slave_08_bit(
.clk_i(wb_lo_clk_o),
.rst_i(wb_lo_rst_o),
.dat_o(slave_08_bit_dat_o[7:0]),
.dat_i(wb_lo_dat_o[7:0]),
.adr_i(wb_lo_adr_o[4:0]),
.cyc_i(slave_08_bit_cyc_i),
.stb_i(slave_08_bit_stb_i),
.we_i(wb_lo_we_o),
.sel_i(wb_lo_sel_o[0]),
.ack_o(slave_08_bit_ack_o),
.err_o(slave_08_bit_err_o),
.rty_o(slave_08_bit_rty_o)
);
wb_slave_model #(.DWIDTH(16), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_16_bit.txt") )
wb_slave_16_bit(
.clk_i(wb_lo_clk_o),
.rst_i(wb_lo_rst_o),
.dat_o(slave_16_bit_dat_o),
.dat_i(wb_lo_dat_o[15:0]),
.adr_i(wb_lo_adr_o[4:0]),
.cyc_i(slave_16_bit_cyc_i),
.stb_i(slave_16_bit_stb_i),
.we_i(wb_lo_we_o),
.sel_i(wb_lo_sel_o),
.ack_o(slave_16_bit_ack_o),
.err_o(slave_16_bit_err_o),
.rty_o(slave_16_bit_rty_o)
);
 
endmodule
 
 
/test/debug/tb_top.v
1,155 → 1,132
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ns/10ps
 
 
module tb_top();
 
parameter CLK_PERIOD = 10;
 
reg tb_clk, tb_rst;
 
initial
begin
tb_clk <= 1'b1;
tb_rst <= 1'b1;
#(CLK_PERIOD); #(CLK_PERIOD/3);
tb_rst = 1'b0;
end
 
always
#(CLK_PERIOD/2) tb_clk = ~tb_clk;
// --------------------------------------------------------------------
// tb_dut
tb_dut dut( tb_clk, tb_rst );
 
// --------------------------------------------------------------------
// insert test below
 
initial
begin
wait( ~tb_rst );
repeat(2) @(posedge tb_clk);
// 8 bit if
$display("\n^^^- testing 8 bit interface\n");
dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100);
dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544);
dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988);
dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc);
dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef);
dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef);
dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
// 16 bit if
$display("\n^^^- testing 16 bit interface\n");
dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100);
dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544);
dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988);
dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc);
dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef);
dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef);
dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
// do illegal byte boundary access
$display("\n^^^- testing illegal byte boundary access\n");
dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx);
repeat(2) @(posedge tb_clk);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
$stop();
end
endmodule
 
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_top();
 
parameter CLK_PERIOD = 10;
 
reg tb_clk, tb_rst;
 
initial
begin
tb_clk <= 1'b1;
tb_rst <= 1'b1;
#(CLK_PERIOD); #(CLK_PERIOD/3);
tb_rst = 1'b0;
end
 
always
#(CLK_PERIOD/2) tb_clk = ~tb_clk;
// --------------------------------------------------------------------
// tb_dut
tb_dut dut( tb_clk, tb_rst );
 
// --------------------------------------------------------------------
// insert test below
 
initial
begin
wait( ~tb_rst );
repeat(2) @(posedge tb_clk);
// 8 bit if
$display("\n^^^- testing 8 bit interface\n");
dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100);
dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544);
dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988);
dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc);
dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef);
dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef);
dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
// 16 bit if
$display("\n^^^- testing 16 bit interface\n");
dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100);
dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544);
dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988);
dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc);
dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef);
dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef);
dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
// do illegal byte boundary access
$display("\n^^^- testing illegal byte boundary access\n");
dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx);
repeat(2) @(posedge tb_clk);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
$stop();
end
endmodule
 
/models/wb_slave_model.v
1,146 → 1,123
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ns/10ps
 
 
module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i,
cyc_i, stb_i, we_i, sel_i,
ack_o, err_o, rty_o );
 
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter ACK_DELAY = 2;
parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
input clk_i;
input rst_i;
output [DWIDTH-1:0] dat_o;
input [DWIDTH-1:0] dat_i;
input [AWIDTH-1:0] adr_i;
input cyc_i;
input stb_i;
input we_i;
input [( (DWIDTH/8) - 1 ):0] sel_i;
output ack_o;
output err_o;
output rty_o;
// --------------------------------------------------------------------
// slave ram
reg [7:0] ram[2**AWIDTH-1:0];
initial
$readmemh( SLAVE_RAM_INIT, ram );
 
// --------------------------------------------------------------------
//
generate
case( DWIDTH )
8: begin
initial
$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[adr_i] <= dat_i[7:0];
assign dat_o = ram[adr_i];
end
16: begin
initial
$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
end
32: begin
initial
begin
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
$display( "###- wb_slave_model(): Not yet supported " );
$stop();
end
end
default: begin
localparam SLAVE_SIZE = -1;
initial
begin
$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
$stop();
end
end
endcase
endgenerate
 
// --------------------------------------------------------------------
// ack delay
reg ack_delayed;
initial
ack_delayed = 1'b0;
always @(posedge clk_i or cyc_i or stb_i)
begin
if(cyc_i & stb_i)
begin
ack_delayed = 1'b0;
repeat(ACK_DELAY) @(posedge clk_i);
if(cyc_i & stb_i)
ack_delayed = 1'b1;
else
ack_delayed = 1'b0;
end
else
ack_delayed = 1'b0;
end
// --------------------------------------------------------------------
// assign outputs
assign ack_o = ack_delayed;
assign err_o = 1'b0;
assign rty_o = 1'b0;
 
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i,
cyc_i, stb_i, we_i, sel_i,
ack_o, err_o, rty_o );
 
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter ACK_DELAY = 2;
parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
input clk_i;
input rst_i;
output [DWIDTH-1:0] dat_o;
input [DWIDTH-1:0] dat_i;
input [AWIDTH-1:0] adr_i;
input cyc_i;
input stb_i;
input we_i;
input [( (DWIDTH/8) - 1 ):0] sel_i;
output ack_o;
output err_o;
output rty_o;
// --------------------------------------------------------------------
// slave ram
reg [7:0] ram[2**AWIDTH-1:0];
initial
$readmemh( SLAVE_RAM_INIT, ram );
 
// --------------------------------------------------------------------
//
generate
case( DWIDTH )
8: begin
initial
$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[adr_i] <= dat_i[7:0];
assign dat_o = ram[adr_i];
end
16: begin
initial
$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
end
32: begin
initial
begin
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
$display( "###- wb_slave_model(): Not yet supported " );
$stop();
end
end
default: begin
localparam SLAVE_SIZE = -1;
initial
begin
$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
$stop();
end
end
endcase
endgenerate
 
// --------------------------------------------------------------------
// ack delay
reg ack_delayed;
initial
ack_delayed = 1'b0;
always @(posedge clk_i or cyc_i or stb_i)
begin
if(cyc_i & stb_i)
begin
ack_delayed = 1'b0;
repeat(ACK_DELAY) @(posedge clk_i);
if(cyc_i & stb_i)
ack_delayed = 1'b1;
else
ack_delayed = 1'b0;
end
else
ack_delayed = 1'b0;
end
// --------------------------------------------------------------------
// assign outputs
assign ack_o = ack_delayed;
assign err_o = 1'b0;
assign rty_o = 1'b0;
 
endmodule
/models/wb_master_model.v
1,498 → 1,498
///////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 Wishbone Master model ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
//// ////
///////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
///////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/10ps
 
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
//
// parameters
//
parameter dwidth = 32;
parameter awidth = 32;
parameter log_level = 3;
 
//
// inputs & outputs
//
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dwidth/8 -1:0] sel;
input ack, err, rty;
 
//
// variables
//
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg cyc, stb;
reg we;
reg [dwidth/8 -1:0] sel;
 
reg [dwidth -1:0] q;
 
integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
 
 
//
// module body
//
 
// check ack, err and rty assertion
always@(ack or err or rty)
begin
case ({ack, err, rty})
// ok-states
// 3'b000: // none asserted
// 3'b001: // only rty asserted
// 3'b010: // only err asserted
// 3'b100: // only ack asserted
 
// fault-states
3'b011: // oops, err and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
end
3'b101: // oops, ack and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
end
3'b110: // oops, ack and err
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
end
3'b111: // oops, ack, err and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
end
endcase
if (err_wb_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
$stop;
end
end
 
// initial settings
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
err_tot_cnt = 0;
err_cur_cnt = 0;
err_wb_cnt = 0;
err_watchdog = 3;
 
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
 
////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
if( log_level > 2 )
$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = d;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
task wb_write_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
 
if( log_level > 2 )
$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = d;
stb = 1'b1;
we = 1'b1;
sel = s;
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = {dwidth{1'bx}};
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
if( log_level > 2 )
$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
end
endtask
 
task wb_read_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = {dwidth{1'bx}};
stb = 1'b1;
we = 1'b0;
sel = s;
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
if( log_level > 2 )
$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
end
endtask
 
////////////////////////////
//
// Wishbone compare cycle
// read data from location and compare with expected data
//
 
task wb_cmp;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read (delay, stb_delay, a, q);
 
if (d_exp !== q)
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
end
 
if (err_tot_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
$stop;
end
end
endtask
 
 
task wb_cmp_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read_sel (delay, stb_delay, s, a, q);
 
if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
end
 
if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
end
 
if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
end
 
if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
end
 
if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
end
 
if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
end
 
if( (d_exp !== q) & s == 4'b1111 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
end
case( s )
4'b0001: ;
4'b0010: ;
4'b0100: ;
4'b1000: ;
4'b0011: ;
4'b1100: ;
4'b1111: ;
default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
endcase
 
if (err_tot_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
$stop;
end
end
endtask
 
 
////////////////////////////
//
// Error counter handlers
//
task set_cur_err_cnt;
input value;
begin
err_cur_cnt = value;
end
endtask
 
task show_cur_err_cnt;
$display("\nCurrent errors detected: %d\n", err_cur_cnt);
endtask
 
task show_tot_err_cnt;
$display("\nTotal errors detected: %d\n", err_tot_cnt);
endtask
always @(posedge clk)
if( err & (cyc == 1'b1) & (stb == 1'b1) )
$display( "!!!- WB Bus Error at time %t. ", $time );
 
endmodule
 
///////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 Wishbone Master model ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
//// ////
///////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
///////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/10ps
 
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
//
// parameters
//
parameter dwidth = 32;
parameter awidth = 32;
parameter log_level = 3;
 
//
// inputs & outputs
//
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dwidth/8 -1:0] sel;
input ack, err, rty;
 
//
// variables
//
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg cyc, stb;
reg we;
reg [dwidth/8 -1:0] sel;
 
reg [dwidth -1:0] q;
 
integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
 
 
//
// module body
//
 
// check ack, err and rty assertion
always@(ack or err or rty)
begin
case ({ack, err, rty})
// ok-states
// 3'b000: // none asserted
// 3'b001: // only rty asserted
// 3'b010: // only err asserted
// 3'b100: // only ack asserted
 
// fault-states
3'b011: // oops, err and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
end
3'b101: // oops, ack and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
end
3'b110: // oops, ack and err
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
end
3'b111: // oops, ack, err and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
end
endcase
if (err_wb_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
$stop;
end
end
 
// initial settings
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
err_tot_cnt = 0;
err_cur_cnt = 0;
err_wb_cnt = 0;
err_watchdog = 3;
 
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
 
////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
if( log_level > 2 )
$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = d;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
task wb_write_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
 
if( log_level > 2 )
$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = d;
stb = 1'b1;
we = 1'b1;
sel = s;
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = {dwidth{1'bx}};
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
if( log_level > 2 )
$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
end
endtask
 
task wb_read_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = {dwidth{1'bx}};
stb = 1'b1;
we = 1'b0;
sel = s;
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
if( log_level > 2 )
$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
end
endtask
 
////////////////////////////
//
// Wishbone compare cycle
// read data from location and compare with expected data
//
 
task wb_cmp;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read (delay, stb_delay, a, q);
 
if (d_exp !== q)
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
end
 
if (err_tot_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
$stop;
end
end
endtask
 
 
task wb_cmp_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read_sel (delay, stb_delay, s, a, q);
 
if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
end
 
if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
end
 
if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
end
 
if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
end
 
if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
end
 
if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
end
 
if( (d_exp !== q) & s == 4'b1111 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
end
case( s )
4'b0001: ;
4'b0010: ;
4'b0100: ;
4'b1000: ;
4'b0011: ;
4'b1100: ;
4'b1111: ;
default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
endcase
 
if (err_tot_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
$stop;
end
end
endtask
 
 
////////////////////////////
//
// Error counter handlers
//
task set_cur_err_cnt;
input value;
begin
err_cur_cnt = value;
end
endtask
 
task show_cur_err_cnt;
$display("\nCurrent errors detected: %d\n", err_cur_cnt);
endtask
 
task show_tot_err_cnt;
$display("\nTotal errors detected: %d\n", err_tot_cnt);
endtask
always @(posedge clk)
if( err & (cyc == 1'b1) & (stb == 1'b1) )
$display( "!!!- WB Bus Error at time %t. ", $time );
 
endmodule
 

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