Subversion Repositories wb_tk
Compare Revisions
- This comparison shows the changes necessary to convert path
/wb_tk/web_uploads
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
WisboneTK
+WishboneTK output register
+Description
+WishboneTK output register is a parametrized output register with read-back support. It is 100% Wishbone compatible +with the WishboneTK extensions. The bus-width and the output width can be configured separately. +Output width can be larger than the bus size. In that case address signals should be used access various parts of the +however the bus width is required to be bigger than the output width. + +Wishbone datasheet
+Description | Specification | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
General Description | Output register with readback support. | ||||||||||||||||||||||
Supported cycles | Slave read/write Slave block read/write Slave rmw | ||||||||||||||||||||||
Data port size | variable | ||||||||||||||||||||||
Data port granularity | 8 bits | ||||||||||||||||||||||
Data port maximum operand size | same as bus size | ||||||||||||||||||||||
Data transfer ordering | n/a | ||||||||||||||||||||||
Data transfer sequencing | n/a | ||||||||||||||||||||||
Supported signal list and cross reference to equivalent Wishbone signals |
+
|
Parameter description
+Parameter name | Description |
---|---|
width | Number of bits in the output register |
bus_width | Size of the data-bus |
offset | Bit-offset from where the output bits start within the data |
Signal description
+Signal name | Description |
---|---|
CLK_I | Wishbone clock signal |
RST_I | Wishbone reset signal |
CYC_I | Wishbone cycle signal. High value frames blocks of access |
STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
ACK_OI | WhisboneTK acknowledge chain input signal |
SEL_I(bus_width/8-1..0) | Wishbone byte-selection signals |
ADR_I(addr_width*-1..0) | Wishbone address bus signals |
DAT_I(bus_width-1..0) | Wishbone data bus input (to slave direction) signals |
DAT_O(bus_width-1..0) | Wishbone data bus output (to master direction) signals |
DAT_OI(bus_width-1..0) | WhisboneTK data bus chain input signal |
RST_VAL(width-1..0) | Value written to the register upon reset |
Q(width-1..0) | Output value of the register |
+* addr_with: size2bits((width+offset+bus_width-1)/bus_width)-1. + +
Author & Maintainer
++Andras Tantos + Index: wb_async_slave.shtml =================================================================== --- wb_async_slave.shtml (nonexistent) +++ wb_async_slave.shtml (revision 9) @@ -0,0 +1,75 @@ + + + +
WisboneTK
+Asyncronous slave interface
+Description
+Asyncronous (SRAM-like) slave interface is a simple parametrized bus converter. It acts as a slave device +for a Wishbone bus master device and converts cycles on the wishbone bus to asyncronous access cycles, very similar to SRAM +access cycles. That type of bus interface is very common between slow to middle speed peripherial chips available on the +market. With this core it is possible to use those peripherials from a Wishbone master device. It is also possible to drive +high-speed SRAM devices and use them as off-core memory. The core is 100% Wishbone compatible +with the WishboneTK extensions. The address and data bus-width can be configured through compile-time +parameters. The speed of the external device can be set using input signals. A deactivation cycle is inserted after each access to +the core thus the maximum access speed is half of the speed of the Whisbone bus. Becouse deactivation cycle is completed after the +finish of the access cycle if the next access on the Whisbone bus is to another device zero wait-state operation can be achieved. + +Wishbone datasheet
+Description | Specification | ||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
General Description | Asyncronous (SRAM-like) slave interface | ||||||||||||||||||||
Supported cycles | Slave read/write Slave block read/write Slave rmw | ||||||||||||||||||||
Data port size | variable | ||||||||||||||||||||
Data port granularity | 8-bit | ||||||||||||||||||||
Data port maximum operand size | same as data port size | ||||||||||||||||||||
Data transfer ordering | n/a | ||||||||||||||||||||
Data transfer sequencing | n/a | ||||||||||||||||||||
Supported signal list and cross reference to equivalent Wishbone signals |
+
|
Parameter description
+Parameter name | Description |
---|---|
width | Data bus width |
addr_width | Address bus width |
Signal description
+Signal name | Description |
---|---|
WAIT_STATE(3..0) | Number of wait-states to generate. 0 means 1 access and one deactivation cycle, no wait-states. |
CLK_I | Wishbone clock signal |
RST_I | Wishbone reset signal |
STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
ACK_OI | WhisboneTK acknowledge chain input signal |
ADR_I(addr_width-1..0) | Wishbone address bus signals |
DAT_I(width-1..0) | Wishbone data bus input (to slave direction) signals |
DAT_O(width-1..0) | Wishbone data bus output (to master direction) signals |
DAT_OI(width-1..0) | WhisboneTK data bus chain input signal |
SEL_I(addr_width/8-1..0) | Wishbone byte-selection signals |
Aysncronous interfce signals | |
A_DATA(width-1..0) | Bidirectional data bus signals |
A_ADDR(addr_width-1..0) | Address bus output signals |
A_RDN | Active low read signal |
A_WRN | Active low write signal |
A_CEN | Active low chip-select signal |
A_BYEN(addr_width/8-1..0) | Active-low byte-enable signals |
Author & Maintainer
++Andras Tantos + Index: wb_arbiter.shtml =================================================================== --- wb_arbiter.shtml (nonexistent) +++ wb_arbiter.shtml (revision 9) @@ -0,0 +1,91 @@ + + + +
WisboneTK
+WishboneTK two-way arbiter
+Description
+WishboneTK two-way arbiter connectrs two master devices to a set of shared slave devies. From the master devices point +of view the shared peripherials will look like a single slave inserted into their local slave's chain. From the shared slaves point of +view the arbiter will act as a master device on behalf of the two real masters. The core is 100% Wishbone compatible +with the WishboneTK extensions. Address select and data buses should be multiplexed to the +common interface externaly but handshake signals are handled by the core. Multiplexer control signals are also provided. The core +is asyncronous to support zero-wait-state operation on the shared bus. Thus the CLK_I signal, required for most Wishbone devies +is not used. + +Wishbone datasheet
+Description | Specification | ||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
General Description | Two-way arbiter. | ||||||||||||||||||||||||||||||||||||||||||||||
Supported cycles | Slave read/write Slave block read/write Slave rmw + Master read/write Master block read/write Master rmw | ||||||||||||||||||||||||||||||||||||||||||||||
Data port size | n/a | ||||||||||||||||||||||||||||||||||||||||||||||
Data port granularity | n/a | ||||||||||||||||||||||||||||||||||||||||||||||
Data port maximum operand size | n/a | ||||||||||||||||||||||||||||||||||||||||||||||
Data transfer ordering | n/a | ||||||||||||||||||||||||||||||||||||||||||||||
Data transfer sequencing | n/a | ||||||||||||||||||||||||||||||||||||||||||||||
Supported signal list and cross reference to equivalent Wishbone signals |
+
|
Signal description
+Signal name | Description |
---|---|
Signals to connect to master A | |
A_RST_I | Wishbone reset signal |
A_CYC_I | Wishbone cycle signal. High value frames blocks of access |
A_STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
A_WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
A_ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
A_ACK_OI | WhisboneTK acknowledge chain input signal |
A_RTY_O | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
A_RTY_OI | WhisboneTK retry chain input signal |
A_ERR_O | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
A_ERR_OI | WhisboneTK error chain input signal |
Signals to connect to master B | |
B_RST_I | Wishbone reset signal |
B_CYC_I | Wishbone cycle signal. High value frames blocks of access |
B_STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
B_WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
B_ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
B_ACK_OI | WhisboneTK acknowledge chain input signal |
B_RTY_O | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
B_RTY_OI | WhisboneTK retry chain input signal |
B_ERR_O | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
B_ERR_OI | WhisboneTK error chain input signal |
Signals to connect to shared slaves | |
S_CYC_O | Wishbone cycle signal. High value frames blocks of access |
S_STB_O | Wishbone strobe signal. High value indicates cycle to this particular device |
S_WE_O | Wishbone write enable signal. High indicates data flowing from master to slave |
S_ACK_I | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
S_RTY_I | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
S_ERR_I | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
Author & Maintainer
++Andras Tantos + Index: wb_async_master.shtml =================================================================== --- wb_async_master.shtml (nonexistent) +++ wb_async_master.shtml (revision 9) @@ -0,0 +1,74 @@ + + + +
WisboneTK
+Asyncronous master interface
+Description
+Asyncronous master interface is a simple parametrized bus converter. It acts as a slave device +for an asyncron CPU-like master device and converts cycles to wishbone compatible bus access cycles. That +type of bus interface is very common between slow to middle speed CPUs and MCUs available on the +market. With this core it is possible to use those Wishbone peripherials from those device. The core is 100% Wishbone compatible +with the WishboneTK extensions. The address and data bus-width can be configured +through compile-time parameters. The speed of the asyncronous bus is controled by the wait signal. + +Wishbone datasheet
+Description | Specification | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
General Description | Asyncronous master interface | ||||||||||||||||||||||||||
Supported cycles | Master read/write Master block read/write Master rmw | ||||||||||||||||||||||||||
Data port size | variable | ||||||||||||||||||||||||||
Data port granularity | 8-bit | ||||||||||||||||||||||||||
Data port maximum operand size | same as data port size | ||||||||||||||||||||||||||
Data transfer ordering | n/a | ||||||||||||||||||||||||||
Data transfer sequencing | n/a | ||||||||||||||||||||||||||
Supported signal list and cross reference to equivalent Wishbone signals |
+
|
Parameter description
+Parameter name | Description |
---|---|
width | Data bus width |
addr_width | Address bus width |
Signal description
+Signal name | Description |
---|---|
S_CYC_O | Wishbone cycle signal. High value frames blocks of access |
S_STB_O | Wishbone strobe signal. High value indicates cycle to this particular device |
S_WE_O | Wishbone write enable signal. High indicates data flowing from master to slave |
S_ACK_I | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
S_RTY_I | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
S_ERR_I | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
S_ADR_O(addr_width-2..0) | Wishbone address bus signals |
S_SEL_O(width/8-1..0) | Wishbone byte-selection signals |
S_DAT_I(width-1..0) | Wishbone data bus input (to slave direction) signals |
S_DAT_O(width-1..0) | Wishbone data bus output (to master direction) signals |
Aysncronous interfce signals | |
A_DATA(width-1..0) | Bidirectional data bus signals |
A_ADDR(addr_width-1..0) | Address bus output signals |
A_RDN | Active low read signal |
A_WRN | Active low write signal |
A_CEN | Active low chip-select signal |
A_BYEN(addr_width/8-1..0) | Active-low byte-enable signals |
A_WAITN | Active low wait signal |
Author & Maintainer
++Andras Tantos + Index: wb_bus_resizer.shtml =================================================================== --- wb_bus_resizer.shtml (nonexistent) +++ wb_bus_resizer.shtml (revision 9) @@ -0,0 +1,95 @@ + + + +
WisboneTK
+WishboneTK bus resizer
+Description
+WishboneTK bus resizer converts an X-bit Wishbone bus access to an Y-bit bus access. +The conversion is done by asserting the correct byte select signals and multiplex the data-bus according to the access. +The core cannot change the granularity of the access. It is 100% Wishbone compatible with the +WishboneTK extensions. The device contains only simple logic with no feed-back thus it is +asyncronous without any state. For this reason the CLK_I and RST_I signals, required for most Wishbone devies are not used. +The core can do up- and down-size. If master and slave interface has the same size, the core compiles into a bunch of wires +except for Wishbone extension gates. + +Wishbone datasheet
+Description | Specification | ||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
General Description | Bus up-sizer. | ||||||||||||||||||||||||||||||||||||||||||||||
Supported cycles | Slave read/write Slave block read/write Slave rmw + Master read/write Master block read/write Master rmw | ||||||||||||||||||||||||||||||||||||||||||||||
Data port size | Configurable on both slave and master side | ||||||||||||||||||||||||||||||||||||||||||||||
Data port granularity | 8-bit | ||||||||||||||||||||||||||||||||||||||||||||||
Data port maximum operand size | Bus size | ||||||||||||||||||||||||||||||||||||||||||||||
Data transfer ordering | Little and big endien | ||||||||||||||||||||||||||||||||||||||||||||||
Data transfer sequencing | n/a | ||||||||||||||||||||||||||||||||||||||||||||||
Supported signal list and cross reference to equivalent Wishbone signals |
+
|
Parameter description
+Parameter name | Description |
---|---|
m_bus_width | Master data bus width. |
m_addr_width | Master address bus width |
s_bus_width | Slave data bus width. |
little_endien | True for little endien, False for big endien address decoding |
Signal description
+Signal name | Description |
---|---|
Signals to connect to master | |
M_CYC_I | Wishbone cycle signal. High value frames blocks of access |
M_STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
M_WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
M_ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
M_ACK_OI | WhisboneTK acknowledge chain input signal |
M_RTY_O | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
M_RTY_OI | WhisboneTK retry chain input signal |
M_ERR_O | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
M_ERR_OI | WhisboneTK error chain input signal |
M_ADR_I(m_addr_width-1..0) | Wishbone address bus signals |
M_SEL_I(m_bus_width/8-1..0) | Wishbone byte-selection signals |
M_DAT_I(m_bus_width-1..0) | Wishbone data bus input (to slave direction) signals |
M_DAT_O(m_bus_width-1..0) | Wishbone data bus output (to master direction) signals |
M_DAT_OI(m_bus_width-1..0) | WhisboneTK data bus chain input signal |
Signals to connect to slave | |
S_CYC_O | Wishbone cycle signal. High value frames blocks of access |
S_STB_O | Wishbone strobe signal. High value indicates cycle to this particular device |
S_WE_O | Wishbone write enable signal. High indicates data flowing from master to slave |
S_ACK_I | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
S_RTY_I | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
S_ERR_I | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
S_ADR_O(m_addr_width-2..0) | Wishbone address bus signals |
S_SEL_O(s_bus_width/8-1..0) | Wishbone byte-selection signals |
S_DAT_I(s_bus_width-1..0) | Wishbone data bus input (to slave direction) signals |
S_DAT_O(s_bus_width-1..0) | Wishbone data bus output (to master direction) signals |
Author & Maintainer
++Andras Tantos + Index: index.shtml =================================================================== --- index.shtml (nonexistent) +++ index.shtml (revision 9) @@ -0,0 +1,49 @@ + + + +
The WishboneTK
+General Description
++WhisnoneTK is a set of IP cores designed to be compatible with the Wishbone bus +specification. The members of the tool-kit are general purpose building-blocks whose (hopefuly) make designing Wishbone compatible +devices easier. The elements in the libarary are avaliable free for any kind of use . +The parts in the library use an extended signal-set than defined in the Wishbone interface. +The toolkit supposed to be technology independent. That's acheaved by moving all technology-specific code to a different package. Porting +that package to other technologies than the current one (Altera+Exemplar) is easy. That package can also be downloaded. +
+The elements currently in the library are: +
-
+
- Output register +
- Two-way bus arbiter +
- Asyncronous (SRAM-like) slave interface +
- Asyncronous master interface +
- Bus up-sizer +
- Single-port RAM +
wb_tk
package.
+
+There are some procedures useful for testing Wishbone devices in the package
+test
.
+
+Other elements planned for the toolkit: +
-
+
- FIFO buffer + +
- Various DRAM (FP, EDO, SD) interfaces +
- Input register +
- Timer +
- UART +
- Syncronous serial interface +
- Dual-ported (shared) memory +
- CACHE memory +
Download
++The source for the toolkit can be downloaded from the CVS repository. +You can browse the repository here or +use CVSget with module name wb_tk. + +
Author & Maintainer
++Andras Tantos + Index: wb_extensions.shtml =================================================================== --- wb_extensions.shtml (nonexistent) +++ wb_extensions.shtml (revision 9) @@ -0,0 +1,100 @@ + + + +
WisboneTK
+WishboneTK extensions
+General Description
++WhisnoneTK extends the original Wishbone specification with some signals. These signals are common in all WishboneTK cores. +The cores are still 100% compatible with the original Wishbone specification. Other Wishbone cores without this extended signal set +can be integrated with WishboneTK cores with no problem. The Wishbone specification does not specifiy the topology of the bus. It +allows for both multiplexer-driven, three-stated, cross-bar or any other topology. WishboneTK extensions make this integration effort +easyer by introducing a distributed multiplexer scheme. +
Additional signals
++The following additional signals are defined: +
Signal name | Description |
---|---|
ACK_OI | WhisboneTK acknowledge chain input signal |
RTY_OI | WhisboneTK retry chain input signal |
ERR_OI | WhisboneTK error chain input signal |
DAT_OI(..) | WhisboneTK data bus chain input signal |
+The operation of these pins are simple and the same for all pins. They all have a pair in the original Wishbone specification. ACK_OI for +example paired with ACK_O. The rule is that an additional 'I' character is appended to the original Wishbone name to get the name for +the extended signal. So the pairing of the signals is as follows: +
WishboneTK signal name | Paired Wishbone signal name |
---|---|
ACK_OI | ACK_O |
RTY_OI | RTY_O |
ERR_OI | ERR_O |
DAT_OI(..) | DATA_O() |
Signal operation
++All signal with it's associated pair works in a similar way so operation will be described using the ACK_O/ACK_OI signals. +
+The generation of the original Wishbone signal was slightly modified. There is an internal (let's call it I_ACK_O) signal inside each
+core which has the same behaviour that Wishbone specification dictates. The external ACK_O signal will be the same as the internal
+I_ACK_O signal if the device is selected (STB_I is active) and will be tha same as ACK_OI otherwise. The logic representation of
+this is:
+ACK_OI <= (I_ACK_O and STB_I) or (ACK_IO and not STB_I);
+
+Because Wishbone does not specify any bahaviour for these lines when STB_I is inactive this modification still fully conforms with +the original spec. + +
Signal usage for multiplexed buses
++Multiplexed buses it is much easyer to build using this aproach. If you connect all salve devices in a chain by connecting previous +slave's ACK_O to the next devices ACK_OI and all other mentioned pins likewise you get a distributed multiplexer achitecture. Note +that during flattening the design (part of the synthetizis process) this distributed multiplexer will turn into a normal multiplexer. +
+For this achitecture you should connect the outputs of the last slave in the chain to the inputs of the master device. (As Wishbone +does not provide any arbitation mechanism there can be only one master in a bus and arbiter bridges must be used for a multi-master +configuration.) +
+The inputs of the first slave in the chain must be connected as follows: +
WishboneTK signal name | Default value |
---|---|
ACK_OI | '0' |
RTY_OI | '0' |
ERR_OI | '1' |
DAT_OI(..) | '-' (don't care) |
+You can easily do this by setting these values as the defaults in your component declaration. This will give you another benefit: +Wishbone defines a handshake between masters and slaves. The master will wait after a cycle issued until the slave signals the +end of the cycle by asserting either ACK_O, ERR_O or RTY_O. If the master (a micro-processor program) issues an access to an undefined +address, no slave will be addressed. In this case the master will wait endlessly if none of the handshake signals default to '1'. +If your design does not use the ERR_O handshake mechanism you should default another signal to '1'. + +
Signal usage for three-stated buses
++For WishboneTK cores to be connected to three-stated buses use the following defaults: +
WishboneTK signal name | Default value |
---|---|
ACK_OI | 'L' (weak pull-down) |
RTY_OI | 'L' (weak pull-down) |
ERR_OI | 'H' (weak pull-up) |
DAT_OI(..) | 'Z' (hi-Z state) |
Signal usage in none-WishboneTK multiplexed-bus applications
++If an external multiplexer is used to connect slave signals to master, use the following defaults: +
WishboneTK signal name | Default value |
---|---|
ACK_OI | '-' (don't care) |
RTY_OI | '-' (don't care) |
ERR_OI | '-' (don't care) |
DAT_OI(..) | '-' (don't care) |
Author & Maintainer
++Andras Tantos + Index: wb_ram.shtml =================================================================== --- wb_ram.shtml (nonexistent) +++ wb_ram.shtml (revision 9) @@ -0,0 +1,64 @@ + + + +
WisboneTK
+Single-port RAM
+Description
+The Single-port RAM is a small, fast, on-chip RAM implementation utilizing the embedded RAM blocks +available in many FPGA architectures. Although it can be paramerized to arbitrary size and width it won't fit into +a physical device if larger than a few K-bits. If you need larger memories for your design consider using an +external memory chip and interfacing it to the Wishbone bus with one of the many interface circuits available. +Also you can consider using another Wishbone-compatible single- and dual-ported RAM implementation by +Jamil Khatib which you can find +here. +The core is 100% Wishbone compatible with the WishboneTK extensions. +The core allows zero-wait-state operation. + +Wishbone datasheet
+Description | Specification | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
General Description | Single-port RAM | ||||||||||||||||||
Supported cycles | Slave read/write Slave block read/write Slave rmw | ||||||||||||||||||
Data port size | variable | ||||||||||||||||||
Data port granularity | same as port size | ||||||||||||||||||
Data port maximum operand size | same as data port size | ||||||||||||||||||
Data transfer ordering | n/a | ||||||||||||||||||
Data transfer sequencing | n/a | ||||||||||||||||||
Supported signal list and cross reference to equivalent Wishbone signals |
+
|
Parameter description
+Parameter name | Description |
---|---|
data_width | Data bus width |
addr_width | Address bus width |
Signal description
+Signal name | Description |
---|---|
CLK_I | Wishbone clock signal |
CYC_I | Wishbone active cycle indication signal. High value indicates an active Wishbone cycle on the bus |
STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
ACK_OI | WhisboneTK acknowledge chain input signal |
ADR_I(addr_width-1..0) | Wishbone address bus signals |
DAT_I(data_width-1..0) | Wishbone data bus input (to slave direction) signals |
DAT_O(data_width-1..0) | Wishbone data bus output (to master direction) signals |
DAT_OI(data_width-1..0) | WhisboneTK data bus chain input signal |
Author & Maintainer
++Andras Tantos + Index: wb_test.shtml =================================================================== --- wb_test.shtml (nonexistent) +++ wb_test.shtml (revision 9) @@ -0,0 +1,111 @@ + + + +
WisboneTK
+Test package
+Description
+The WishboneTK test package contains some procedures that can become useful when it comes to testing. These facilities might +not sythetize and that's not their purpose. The procedures contained in this package can read, write and check various values +to/from Wishbone slave devices. The procedures handle all handshaking required between master and slave devices. Currently +the following procedures are available: +-
+
- wr_chk_val +
- wr_val +
- rd_val +
- chk_val +
wr_chk_val
+The procedure issues a write cycle using the wires passed to the function to the address and with the data specified. +Than it issues a read cycle to the same address and compares the value with the data specified. It the two values are +not the same an assert (severity ERROR) is generated. ++The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. +Later versions probably will add this functionality. +
Paramters
+Name | Direction | Specification |
---|---|---|
CLK_I | IN | Wishbone clock signal |
ADR_I | OUT | Wishbone address bus |
DAT_O | IN | Wishbone data bus slave->master direction |
DAT_I | OUT | Wishbone data bus master->slave direction |
WE_I | OUT | Wishbone write enable signal |
CYC_I | OUT | Wishbone active bus-cycle signal |
STB_I | OUT | Wishbone strobe signal |
ACK_O | IN | Wishbone acknowledge signal |
ADDR | IN | Address to write to / read from |
DATA | IN | Data to be written / checked against |
wr_val
+The procedure issues a write cycle using the wires passed to the function to the address and with the data specified. ++The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. +Later versions probably will add this functionality. +
Paramters
+Name | Direction | Specification |
---|---|---|
CLK_I | IN | Wishbone clock signal |
ADR_I | OUT | Wishbone address bus |
DAT_O | IN | Wishbone data bus slave->master direction |
DAT_I | OUT | Wishbone data bus master->slave direction |
WE_I | OUT | Wishbone write enable signal |
CYC_I | OUT | Wishbone active bus-cycle signal |
STB_I | OUT | Wishbone strobe signal |
ACK_O | IN | Wishbone acknowledge signal |
ADDR | IN | Address to write to |
DATA | IN | Data to be written |
rd_val
+The procedure issues a read cycle to the address specified. It copies the value read from the Wishbone bus to the +data paramter. ++The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. +Later versions probably will add this functionality. +
Paramters
+Name | Direction | Specification |
---|---|---|
CLK_I | IN | Wishbone clock signal |
ADR_I | OUT | Wishbone address bus |
DAT_O | IN | Wishbone data bus slave->master direction |
DAT_I | OUT | Wishbone data bus master->slave direction |
WE_I | OUT | Wishbone write enable signal |
CYC_I | OUT | Wishbone active bus-cycle signal |
STB_I | OUT | Wishbone strobe signal |
ACK_O | IN | Wishbone acknowledge signal |
ADDR | IN | Address to read from |
DATA | OUT | Returns data read from the Wishbone bus |
chk_val
+The procedure issues a read cycle to the address specified and compares the value read from the bus with the data specified. +It the two values are not the same an assert (severity ERROR) is generated. ++The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. +Later versions probably will add this functionality. +
Paramters
+Name | Direction | Specification |
---|---|---|
CLK_I | IN | Wishbone clock signal |
ADR_I | OUT | Wishbone address bus |
DAT_O | IN | Wishbone data bus slave->master direction |
DAT_I | OUT | Wishbone data bus master->slave direction |
WE_I | OUT | Wishbone write enable signal |
CYC_I | OUT | Wishbone active bus-cycle signal |
STB_I | OUT | Wishbone strobe signal |
ACK_O | IN | Wishbone acknowledge signal |
ADDR | IN | Address to read from |
DATA | IN | Data to be checked against |