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URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

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  • This comparison shows the changes necessary to convert path 
    /wbddr3/trunk/bench/cpp
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/ddrsdram_tb.cpp
83,6 → 83,7
m_core->o_ddr_data);
 
bool writeout = (!m_core->v__DOT__reset_override);
writeout = true;
 
if (writeout) {
int cmd;
122,7 → 123,21
(m_core->i_ddr_data),
(m_core->o_ddr_data));
 
/*
printf(" FIFO[%x,%x](%d,%d,%08x-%08x-%08x)",
m_core->v__DOT__bus_fifo_head,
m_core->v__DOT__bus_fifo_tail,
m_core->v__DOT__bus_fifo_new[m_core->v__DOT__bus_fifo_tail],
m_core->v__DOT__bus_fifo_sub[m_core->v__DOT__bus_fifo_tail],
m_core->v__DOT__r_data,
m_core->v__DOT__bus_fifo_data[(m_core->v__DOT__bus_fifo_head-1)&15],
m_core->v__DOT__bus_fifo_data[m_core->v__DOT__bus_fifo_tail]);
 
printf(" BUS[%03x/%03x/%03x/%d]",
(m_core->v__DOT__bus_active),
(m_core->v__DOT__bus_read),
(m_core->v__DOT__bus_new),
(m_core->v__DOT__bus_subaddr[8]));
 
// Reset logic
printf(" RST(%06x%s[%d] - %08x->%08x)",
m_core->v__DOT__reset_timer,
130,7 → 145,6
(m_core->v__DOT__reset_address),
(m_core->v__DOT__reset_instruction),
(m_core->v__DOT__reset_cmd));
*/
 
printf(" %s%03x[%d]%04x:%d",
(m_core->v__DOT__r_pending)?"R":" ",
139,13 → 153,14
(m_core->v__DOT__r_col),0);
// (m_core->v__DOT__r_sub));
printf(" %s%s%s",
(m_core->v__DOT__all_banks_closed)?"b":"B",
"B",
// (m_core->v__DOT__all_banks_closed)?"b":"B",
(m_core->v__DOT__need_close_bank)?"C":"N",
//:(m_core->v__DOT__maybe_close_next_bank)?"c":"N",
(m_core->v__DOT__need_open_bank)?"O":"K");
// :(m_core->v__DOT__maybe_open_next_bank)?"o":"K");
for(int i=0; i<8; i++) {
printf("%s%x@%05x%s",
printf("%s%x@%x%s",
(m_core->v__DOT__r_bank==i)?"R":"[",
m_core->v__DOT__bank_status[i],
m_core->v__DOT__bank_address[i],
156,22 → 171,22
extern int gbl_state, gbl_counts;
printf(" %2d:%08x ", gbl_state, gbl_counts);
 
printf(" %s%s%s%s%s:%08x:%08x",
printf(" %s%s%s%s%s%s%s:%08x:%08x",
(m_core->v__DOT__reset_override)?"R":" ",
(m_core->v__DOT__need_refresh)?"N":" ",
(m_core->v__DOT__need_close_bank)?"C":" ",
(m_core->v__DOT__need_open_bank)?"O":" ",
(m_core->v__DOT__valid_bank)?"V":" ",
(m_core->v__DOT__r_move)?"R":" ",
(m_core->v__DOT__m_move)?"M":" ",
m_core->v__DOT__activate_bank_cmd,
m_core->v__DOT__cmd);
 
printf(" F%05x:%d%d%d:%d:%08x",
m_core->v__DOT__refresh_clk,
m_core->v__DOT__need_refresh,
m_core->v__DOT__midrefresh,
m_core->v__DOT__endrefresh,
m_core->v__DOT__midrefresh_hctr,
m_core->v__DOT__midrefresh_lctr);
printf(" F%s%05x:%x/%s",
(m_core->v__DOT__refresh_ztimer)?"Z":" ",
m_core->v__DOT__refresh_counter,
m_core->v__DOT__refresh_addr,
(m_core->v__DOT__need_refresh)?"N":" ");
 
if (m_core->v__DOT__reset_override)
printf(" OVERRIDE");
413,7 → 428,7
printf("Giving the core 140k cycles to start up\n");
// Before testing, let's give the unit time enough to warm up
tb->reset();
for(int i=0; i<140850; i++)
for(int i=0; i<141195; i++)
tb->wb_tick();
 
printf("Getting some memory ...\n");
/ddrsdramsim.cpp
193,6 → 193,7
gbl_state = m_reset_state;
gbl_counts= m_reset_counts;
m_nrefresh_issued = nREF;
m_clocks_since_refresh++;
} else if (!cke) {
assert(0&&"Clock not enabled!");
} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
199,7 → 200,7
if (DDR_REFRESH == cmd) {
m_clocks_since_refresh = 0;
if (m_nrefresh_issued >= (int)nREF)
m_nrefresh_issued = 0;
m_nrefresh_issued = 1;
else
m_nrefresh_issued++;
} else {
208,11 → 209,18
}
for(int i=0; i<NBANKS; i++)
m_bank[i].tick(DDR_REFRESH,0);
 
if (m_nrefresh_issued == nREF)
printf("DDRSDRAM::Refresh cycle complete\n");
} else {
// In operational mode!!
 
m_clocks_since_refresh++;
assert(m_clocks_since_refresh < (int)ckREFIn);
printf("Clocks to refresh should be %4d-%4d = %4d = 0x%04x\n",
ckREFIn, m_clocks_since_refresh,
ckREFIn- m_clocks_since_refresh,
ckREFIn- m_clocks_since_refresh);
switch(cmd) {
case DDR_MRSET:
assert(0&&"Modes should only be set in reset startup");
238,6 → 246,8
}
break;
case DDR_ACTIVATE:
printf("DDRSIM::ACTIVE, clocks_since_refresh = %d >= %d\n", m_clocks_since_refresh, ckRFC);
assert(m_clocks_since_refresh >= (int)ckRFC);
m_bank[ba].tick(DDR_ACTIVATE,addr);
for(int i=0; i<NBANKS; i++)
if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
249,32 → 259,38
m_bank[ba].tick(DDR_WRITE, addr);
for(int i=0; i<NBANKS; i++)
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
unsigned addr = m_bank[ba].m_row;
addr <<= 13;
addr |= ba;
addr <<= 10;
addr |= addr;
addr &= ~3;
unsigned caddr = m_bank[ba].m_row;
caddr <<= 13;
caddr |= ba;
caddr <<= 10;
caddr |= addr;
caddr &= ~7;
caddr >>= 1;
 
printf("DDRSDRAM::WRITE ADDR = %04x|%d|%04x|%d -> %06x\n",
m_bank[ba].m_row, ba, addr, 0, caddr);
 
BUSTIMESLOT *tp;
int offset = m_busloc+ckCL+1;
 
tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
tp->m_addr = addr ;
tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
tp->m_addr = caddr ;
tp->m_used = 1;
tp->m_read = 0;
 
tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
tp->m_addr = addr+1;
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
tp->m_addr = caddr+1;
tp->m_used = 1;
tp->m_read = 0;
 
tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
tp->m_addr = addr+2;
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
tp->m_addr = caddr+2;
tp->m_used = 1;
tp->m_read = 0;
 
tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
tp->m_addr = addr+3;
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
tp->m_addr = caddr+3;
tp->m_used = 1;
tp->m_read = 0;
} break;
285,36 → 301,37
m_bank[ba].tick(DDR_READ, addr);
for(int i=0; i<NBANKS; i++)
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
unsigned addr = m_bank[ba].m_row;
addr <<= 13;
addr |= ba;
addr <<= 10;
addr |= addr;
addr &= ~3;
unsigned caddr = m_bank[ba].m_row;
caddr <<= 13;
caddr |= ba;
caddr <<= 10;
caddr |= addr;
caddr &= ~7;
caddr >>= 1;
 
BUSTIMESLOT *tp;
tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
tp->m_data = m_mem[addr];
tp->m_addr = addr;
tp->m_data = m_mem[caddr];
tp->m_addr = caddr;
tp->m_used = 1;
tp->m_read = 1;
tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
tp->m_data = m_mem[addr+1];
tp->m_addr = addr+1;
tp->m_data = m_mem[caddr+1];
tp->m_addr = caddr+1;
tp->m_used = 1;
tp->m_read = 1;
 
tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
tp->m_data = m_mem[addr+2];
tp->m_addr = addr+2;
tp->m_data = m_mem[caddr+2];
tp->m_addr = caddr+2;
tp->m_used = 1;
tp->m_read = 1;
 
tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
tp->m_data = m_mem[addr+3];
tp->m_addr = addr+3;
tp->m_data = m_mem[caddr+3];
tp->m_addr = caddr+3;
tp->m_used = 1;
tp->m_read = 1;
} break;
335,13 → 352,21
m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
 
BUSTIMESLOT *ts = &m_bus[m_busloc];
if (ts->m_used) {
printf("Current timeslot = %2d, used", m_busloc);
if (ts->m_read)
printf(", read");
printf("\n");
}
unsigned vl = ts->m_data;
assert( ((!ts->m_used)||(busoe))
|| ((ts->m_used)&&(ts->m_read)));
 
assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
if ((ts->m_used)&&(!ts->m_read)&&(!dm))
if ((ts->m_used)&&(!ts->m_read)&&(!dm)) {
printf("Setting MEM[%08x] = %08x\n", ts->m_addr, data);
m_mem[ts->m_addr] = data;
}
ts->m_used = 0;
ts->m_read = 0;
ts->m_addr = -1;

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