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- from Rev 8 to Rev 13
- ↔ Reverse comparison
Rev 8 → Rev 13
/spec.tex
74,7 → 74,7
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy. |
\end{license} |
\begin{revisionhistory} |
0.0 & 6/20/2016 & D. Gisselquist & Initial Version\\\hline |
0.0 & 8/02/2016 & D. Gisselquist & (Pre-release) Initial Version\\\hline |
\end{revisionhistory} |
% Revision History |
% Table of Contents, named Contents |
142,6 → 142,11
|
% This section describes the architecture of the block. A block level diagram |
% should be included describing the top level of the design. |
\section{Data Structures} |
There are two basic data structures within the core: the bank data structures, |
and the bus data structure(s). The first keeps track of the persistent state |
of each bank, while the second keeps track of I/O transactions that have been |
initiated but not completed. |
|
\section{Strategies} |
\subsection{Bank} |
227,13 → 232,14
\end{wishboneds} |
\caption{Wishbone Datasheet}\label{tbl:wishbone} |
\end{center}\end{table} |
is required by the wishbone specification, and so |
it is included here. The big thing to notice is that all accesses to the |
DDR3 SDRAM memory are via 32--bit reads and writes to this interface. You may |
also wish to note that the scope supports pipeline reading and writing, to |
speed up reading the results out. As a result, the memory interface speed |
should approach one transfer per clock once the pipeline is loaded, although |
there will be delays loading the pipeline. |
is required by the wishbone specification, and so it is included here. The big |
thing to notice is that all accesses to the DDR3 SDRAM memory are via 32--bit |
reads and writes to this interface. You may also wish to note that the memory |
interface supports pipeline reading and writing, to speed up any transfers. As |
a result, the memory interface speed should approach one transfer per clock |
once the pipeline is loaded, although there will be delays loading the pipeline. |
Other than refresh cycles, once the pipeline is loaded it will continue its |
transfer rate at one cycle per clock for as long as it is fed at that speed. |
|
Further, the Wishbone specification this core communicates with has been |
simplified in this manner: The {\tt STB\_I} signal has been constrained so that |