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URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

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    /wbddr3/trunk/rtl
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Rev 17 → Rev 18

/wbddrsdram.v
64,6 → 64,7
`define DDR_CKEBIT 21 // Should this reset command set CKE?
//
// Refresh command bit fields
`define DDR_PREREFRESH_STALL 24
`define DDR_NEEDREFRESH 23
`define DDR_RFTIMER 22
`define DDR_RFBEGIN 21
86,15 → 87,15
o_wb_ack, o_wb_stall, o_wb_data,
// Memory command wires
o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
o_ddr_cmd_a, o_ddr_cmd_b,
o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_cmd_c, o_ddr_cmd_d,
// And the data wires to go with them ....
o_ddr_data, i_ddr_data);
o_ddr_data, i_ddr_data, o_bus);
// These parameters are not really meant for adjusting from the
// top level. These are more internal variables, recorded here
// so that things can be automatically adjusted without much
// problem.
parameter CKRP = 3;
parameter BUSNOW = 4, BUSREG = BUSNOW-1;
parameter CKRP = 0;
parameter BUSNOW = 2, BUSREG = BUSNOW-1;
// The commands (above) include (in this order):
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
// o_ddr_dqs, o_ddr_dm, o_ddr_odt
101,15 → 102,17
input i_clk, // *MUST* be at 200 MHz for this to work
i_reset;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
input [24:0] i_wb_addr; // Identifies a 64-bit word of interest
input [63:0] i_wb_data;
input [7:0] i_wb_sel;
input i_wb_cyc, i_wb_stb, i_wb_we;
// The bus address needs to identify a single 128-bit word of interest
input [23:0] i_wb_addr;
input [127:0] i_wb_data;
input [15:0] i_wb_sel;
// Wishbone responses/outputs
output reg o_wb_ack, o_wb_stall;
output reg [63:0] o_wb_data;
output reg [127:0] o_wb_data;
// DDR memory command wires
output reg o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe;
output reg o_ddr_reset_n, o_ddr_cke;
output reg [1:0] o_ddr_bus_oe;
// CMDs are:
// 4 bits of CS, RAS, CAS, WE
// 3 bits of bank
119,11 → 122,18
// 1 bit of ODT
// ----
// 27 bits total
output wire [26:0] o_ddr_cmd_a, o_ddr_cmd_b;
output reg [63:0] o_ddr_data;
input [63:0] i_ddr_data;
output wire [26:0] o_ddr_cmd_a, o_ddr_cmd_b,
o_ddr_cmd_c, o_ddr_cmd_d;
output reg [127:0] o_ddr_data;
input [127:0] i_ddr_data;
output reg o_bus;
reg [2:0] cmd_pipe;
reg [1:0] nxt_pipe;
 
always @(posedge i_clk)
o_bus <= (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall);
 
 
//////////
//
//
140,19 → 150,20
// timer commands indicate whether or not the command during the timer is to
// be set to idle, or whether the command is instead left as it was.
reg reset_override, reset_ztimer, maintenance_override;
reg [4:0] reset_address;
reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd_a, cmd_b, refresh_cmd,
maintenance_cmd;
reg [3:0] reset_address;
reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd_a, cmd_b, cmd_c, cmd_d,
refresh_cmd, maintenance_cmd;
reg [24:0] reset_instruction;
reg [16:0] reset_timer;
reg r_move;
initial reset_override = 1'b1;
initial reset_address = 5'h0;
initial reset_address = 4'h0;
always @(posedge i_clk)
if (i_reset)
begin
reset_override <= 1'b1;
reset_cmd <= { `DDR_NOOP, reset_instruction[16:0]};
end else if (reset_ztimer)
end else if ((reset_ztimer)&&(reset_override))
begin
if (reset_instruction[`DDR_RSTDONE])
reset_override <= 1'b0;
178,59 → 189,58
wire [16:0] w_ckXPR, w_ckRFC_first;
wire [13:0] w_MR0, w_MR1, w_MR2;
assign w_MR0 = 14'h0420;
assign w_MR0 = 14'h0210;
assign w_MR1 = 14'h0044;
assign w_MR2 = 14'h0040;
assign w_ckXPR = 17'd68; // Table 68, p186
assign w_ckRFC_first = 17'd30; // i.e. 64 nCK, or ckREFI
assign w_ckXPR = 17'd12; // Table 68, p186: 56 nCK / 4 sys clks= 14(-2)
assign w_ckRFC_first = 17'd11; // i.e. 52 nCK, or ckREFI
always @(posedge i_clk)
// DONE, TIMER, RESET, CKE,
if (i_reset)
reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
// 1. Reset asserted (active low) for 200 us. (@200MHz)
5'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
// 1. Reset asserted (active low) for 200 us. (@80MHz)
4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd16_000 };
// 2. Reset de-asserted, wait 500 us before asserting CKE
5'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd100_000 };
4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd40_000 };
// 3. Assert CKE, wait minimum of Reset CKE Exit time
5'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
// 4. Set MR2. (4 nCK, no TIMER, but needs a NOOP cycle)
5'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };
5'h4: reset_instruction <= { 4'h3, `DDR_NOOP, 17'h00 };
4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };
// 5. Set MR1. (4 nCK, no TIMER, but needs a NOOP cycle)
5'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };
5'h6: reset_instruction <= { 4'h3, `DDR_NOOP, 17'h00 };
4'h4: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };
// 6. Set MR0
5'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };
// 7. Wait 12 clocks
5'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd10 };
4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };
// 7. Wait 12 nCK clocks, or 3 sys clocks
4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd1 };
// 8. Issue a ZQCL command to start ZQ calibration, A10 is high
5'h9: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
4'h7: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
//11.Wait for both tDLLK and tZQinit completed, both are
// 512 cks. Of course, since every one of these commands takes
// two clocks, we wait for half as many clocks (minus two for
// our timer logic)
5'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd254 };
// two clocks, we wait for one quarter as many clocks (minus
// two for our timer logic)
4'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd126 };
// 12. Precharge all command
5'hb: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
// 13. Wait for the precharge to complete. A count of one,
// will have us waiting (1+2)*2 or 6 clocks, so we should be
// good here.
5'hc: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd1 };
4'h9: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
// 13. Wait 5 memory clocks (8 memory clocks) for the precharge
// to complete. A single NOOP here will have us waiting
// 8 clocks, so we should be good here.
4'ha: reset_instruction <= { 4'h3, `DDR_NOOP, 17'd0 };
// 14. A single Auto Refresh commands
5'hd: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
4'hb: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
// 15. Wait for the auto refresh to complete
5'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
4'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
4'hd: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd3 };
default:
reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
endcase
 
initial reset_address = 5'h0;
initial reset_address = 4'h0;
always @(posedge i_clk)
if (i_reset)
reset_address <= 5'h1;
else if ((reset_ztimer)&&(reset_override))
reset_address <= reset_address + 5'h1;
reset_address <= 4'h0;
else if ((reset_ztimer)&&(reset_override)&&(!reset_instruction[`DDR_RSTDONE]))
reset_address <= reset_address + 4'h1;
 
//////////
//
245,23 → 255,24
// Okay, let's investigate when we need to do a refresh. Our plan will be to
// do a single refreshes every tREFI seconds. We will not push off refreshes,
// nor pull them in--for simplicity. tREFI = 7.8us, but it is a parameter
// in the number of clocks. In our case, 7.8us / 5ns = 1560 clocks (not nCK!)
// in the number of clocks (2496 nCK). In our case, 7.8us / 12.5ns = 624 clocks
// (not nCK!)
//
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
// 32 clocks @200MHz. After this time, no more refreshes will be needed for
// (1560-32) clocks (@ 200 MHz).
// 52 clocks @320MHz. After this time, no more refreshes will be needed for
// (2496-52) clocks (@ 320 MHz), or (624-13) clocks (@80MHz).
//
// This logic is very similar to the refresh logic, both use a memory as a
// script.
//
reg need_refresh;
reg need_refresh, pre_refresh_stall;
reg refresh_ztimer;
reg [16:0] refresh_counter;
reg [2:0] refresh_addr;
reg [23:0] refresh_instruction;
reg [24:0] refresh_instruction;
always @(posedge i_clk)
if (reset_override)
refresh_addr <= 3'hf;
refresh_addr <= 3'h0;
else if (refresh_ztimer)
refresh_addr <= refresh_addr + 3'h1;
else if (refresh_instruction[`DDR_RFBEGIN])
270,8 → 281,8
always @(posedge i_clk)
if (reset_override)
begin
refresh_ztimer <= 1'b1;
refresh_counter <= 17'd0;
refresh_ztimer <= 1'b0;
refresh_counter <= 17'd4;
end else if (!refresh_ztimer)
begin
refresh_ztimer <= (refresh_counter == 17'h1);
286,7 → 297,7
assign w_ckREFI = 17'd1560; // == 6240/4
 
wire [16:0] w_ckREFI_left, w_ckRFC_nxt, w_wait_for_idle,
w_precharge_to_refresh;
w_pre_stall_counts;
 
// We need to wait for the bus to become idle from whatever state
// it is in. The difficult time for this measurement is assuming
295,31 → 306,35
// recovery time) or 6 nCK clocks from the end of the write. This
// works out to seven idle bus cycles from the time of the write
// command, or a count of 5 (7-2).
assign w_wait_for_idle = 17'd5; //
assign w_precharge_to_refresh = 17'd1; // = 3-2
assign w_ckREFI_left[16:0] = 17'd1560 // The full interval
-17'd32 // Min what we've already waited
assign w_pre_stall_counts = 17'd3; //
assign w_wait_for_idle = 17'd0; //
assign w_ckREFI_left[16:0] = 17'd624 // The full interval
-17'd13 // Minus what we've already waited
-w_wait_for_idle
-w_precharge_to_refresh-17'd12;
assign w_ckRFC_nxt[16:0] = 17'd32-17'd2;
-17'd19;
assign w_ckRFC_nxt[16:0] = 17'd12-17'd3;
 
always @(posedge i_clk)
if (refresh_ztimer)
if (reset_override)
refresh_instruction <= { 4'h2, `DDR_NOOP, 17'd1 };
else if (refresh_ztimer)
case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
// First, a number of clocks needing no refresh
3'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFI_left };
3'h0: refresh_instruction <= { 4'h2, `DDR_NOOP, w_ckREFI_left };
// Then, we take command of the bus and wait for it to be
// guaranteed idle
3'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, w_wait_for_idle };
3'h1: refresh_instruction <= { 4'ha, `DDR_NOOP, w_pre_stall_counts };
3'h2: refresh_instruction <= { 4'hc, `DDR_NOOP, w_wait_for_idle };
// Once the bus is idle, all commands complete, and a minimum
// recovery time given, we can issue a precharge all command
3'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
3'h3: refresh_instruction <= { 4'hc, `DDR_PRECHARGE, 17'h0400 };
// Now we need to wait tRP = 3 clocks (6 nCK)
3'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, w_precharge_to_refresh };
3'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
3'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC_nxt };
default:
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
3'h4: refresh_instruction <= { 4'hc, `DDR_NOOP, 17'h00 };
3'h5: refresh_instruction <= { 4'hc, `DDR_REFRESH, 17'h00 };
3'h6: refresh_instruction <= { 4'he, `DDR_NOOP, w_ckRFC_nxt };
3'h7: refresh_instruction <= { 4'h2, `DDR_NOOP, 17'd12 };
// default:
// refresh_instruction <= { 4'h1, `DDR_NOOP, 17'h00 };
endcase
 
// Note that we don't need to check if (reset_override) here since
332,74 → 347,37
always @(posedge i_clk)
if (refresh_ztimer)
need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
always @(posedge i_clk)
if (refresh_ztimer)
pre_refresh_stall <= refresh_instruction[`DDR_PREREFRESH_STALL];
 
 
/*
input i_clk, i_reset;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
input [25:0] i_wb_addr;
input [31:0] i_wb_data;
// Wishbone outputs
output reg o_wb_ack;
output reg o_wb_stall;
output reg [31:0] o_wb_data;
// DDR3 RAM Controller
output reg o_ddr_reset_n, o_ddr_cke;
// Control outputs
output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
output wire o_ddr_dqs;
output reg o_ddr_odt;
output wire o_ddr_bus_oe;
// Address outputs
output wire [13:0] o_ddr_addr;
output wire [2:0] o_ddr_ba;
// And the data inputs and outputs
output reg [31:0] o_ddr_data;
input [31:0] i_ddr_data;
*/
 
 
reg [1:0] drive_dqs;
// Our chosen timing doesn't require any more resolution than one
// bus clock for ODT. (Of course, this really isn't necessary, since
// we aren't using ODT as per the MRx registers ... but we keep it
// around in case we change our minds later.)
reg ddr_odt;
reg [7:0] ddr_dm;
reg [15:0] ddr_dm;
 
// The pending transaction
reg [63:0] r_data;
reg [127:0] r_data;
reg r_pending, r_we;
reg [24:0] r_addr;
reg [13:0] r_row;
reg [2:0] r_bank;
reg [9:0] r_col;
reg r_sub;
reg [7:0] r_sel;
reg [15:0] r_sel;
 
// The pending transaction, one further into the pipeline. This is
// the stage where the read/write command is actually given to the
// interface if we haven't stalled.
reg [63:0] s_data;
reg s_pending, s_we; // , s_match;
reg [24:0] s_addr;
reg [127:0] s_data;
reg s_pending, s_we;
reg [13:0] s_row, s_nxt_row;
reg [2:0] s_bank, s_nxt_bank;
reg [9:0] s_col;
reg s_sub;
reg [7:0] s_sel;
reg [15:0] s_sel;
 
// Can the pending transaction be satisfied with the current (ongoing)
// transaction?
reg m_move, m_match, m_pending, m_we;
reg [24:0] m_addr;
reg [13:0] m_row;
reg [2:0] m_bank;
reg [9:0] m_col;
reg [1:0] m_sub;
 
// Can we preload the next bank?
reg [13:0] r_nxt_row;
reg [2:0] r_nxt_bank;
412,7 → 390,6
valid_bank;
reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd,
maybe_close_cmd, maybe_open_cmd, rw_cmd;
reg rw_sub;
reg rw_we;
 
wire w_this_closing_bank, w_this_opening_bank,
420,7 → 397,7
w_this_rw_move;
reg last_closing_bank, last_opening_bank;
wire w_need_close_this_bank, w_need_open_bank,
w_r_valid, w_s_valid, w_s_match;
w_r_valid, w_s_valid;
 
//////////
//
434,123 → 411,110
//
// Let's keep track of any open banks. There are 8 of them to keep track of.
//
// A precharge requires 3 clocks at 200MHz to complete.
// An activate also requires 3 clocks at 200MHz to complete.
// A precharge requires 1 clocks at 80MHz to complete.
// An activate also requires 1 clocks at 80MHz to complete.
// By the time we log these, they will be complete.
// Precharges are not allowed until the maximum of:
// 2 clocks (200 MHz) after a read command
// 8 clocks after a write command
// 4 clocks after a write command
//
//
wire w_precharge_all;
reg [CKRP:0] bank_status [0:7];
reg [13:0] bank_address [0:7];
reg [3:0] bank_wr_ck [0:7]; // tWTR
reg [1:0] bank_wr_ck [0:7]; // tWTR
reg bank_wr_ckzro [0:7]; // tWTR
reg [7:0] bank_open;
reg [7:0] bank_closed;
wire [7:0] bank_open;
wire [7:0] bank_closed;
 
wire [3:0] write_recycle_clocks;
assign write_recycle_clocks = 4'h8;
wire [1:0] write_recycle_clocks;
assign write_recycle_clocks = 2'h3;
 
genvar k;
generate
for(k=0; k<8; k=k+1)
assign bank_open[k] = bank_status[k][0];
for(k=0; k<8; k=k+1)
assign bank_closed[k] = !bank_status[k][0];
endgenerate
 
initial bank_open = 0;
initial bank_closed = 8'hff;
always @(posedge i_clk)
begin
bank_status[0] <= { bank_status[0][(CKRP-1):0], bank_status[0][0] };
bank_status[1] <= { bank_status[1][(CKRP-1):0], bank_status[1][0] };
bank_status[2] <= { bank_status[2][(CKRP-1):0], bank_status[2][0] };
bank_status[3] <= { bank_status[3][(CKRP-1):0], bank_status[3][0] };
bank_status[4] <= { bank_status[4][(CKRP-1):0], bank_status[4][0] };
bank_status[5] <= { bank_status[5][(CKRP-1):0], bank_status[5][0] };
bank_status[6] <= { bank_status[6][(CKRP-1):0], bank_status[6][0] };
bank_status[7] <= { bank_status[7][(CKRP-1):0], bank_status[7][0] };
bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-2'h1):2'h0;
bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-2'h1):2'h0;
bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-2'h1):2'h0;
bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-2'h1):2'h0;
bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-2'h1):2'h0;
bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-2'h1):2'h0;
bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-2'h1):2'h0;
bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-2'h1):2'h0;
 
bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-4'h1):4'h0;
bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-4'h1):4'h0;
bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-4'h1):4'h0;
bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-4'h1):4'h0;
bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-4'h1):4'h0;
bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-4'h1):4'h0;
bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-4'h1):4'h0;
bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-4'h1):4'h0;
bank_wr_ckzro[0] <= (bank_wr_ck[0][1]==1'b0);
bank_wr_ckzro[1] <= (bank_wr_ck[1][1]==1'b0);
bank_wr_ckzro[2] <= (bank_wr_ck[2][1]==1'b0);
bank_wr_ckzro[3] <= (bank_wr_ck[3][1]==1'b0);
bank_wr_ckzro[4] <= (bank_wr_ck[4][1]==1'b0);
bank_wr_ckzro[5] <= (bank_wr_ck[5][1]==1'b0);
bank_wr_ckzro[6] <= (bank_wr_ck[6][1]==1'b0);
bank_wr_ckzro[7] <= (bank_wr_ck[7][1]==1'b0);
 
bank_wr_ckzro[0] <= (bank_wr_ck[0][3:1]==3'b00);
bank_wr_ckzro[1] <= (bank_wr_ck[1][3:1]==3'b00);
bank_wr_ckzro[2] <= (bank_wr_ck[2][3:1]==3'b00);
bank_wr_ckzro[3] <= (bank_wr_ck[3][3:1]==3'b00);
bank_wr_ckzro[4] <= (bank_wr_ck[4][3:1]==3'b00);
bank_wr_ckzro[5] <= (bank_wr_ck[5][3:1]==3'b00);
bank_wr_ckzro[6] <= (bank_wr_ck[6][3:1]==3'b00);
bank_wr_ckzro[7] <= (bank_wr_ck[7][3:1]==3'b00);
// bank_open[0] <= (bank_status[0][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[1] <= (bank_status[1][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[2] <= (bank_status[2][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[3] <= (bank_status[3][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[4] <= (bank_status[4][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[5] <= (bank_status[5][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[6] <= (bank_status[6][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_open[7] <= (bank_status[7][(CKRP-2):0] =={(CKRP-1){1'b1}});
 
bank_open[0] <= (bank_status[0][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[1] <= (bank_status[1][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[2] <= (bank_status[2][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[3] <= (bank_status[3][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[4] <= (bank_status[4][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[5] <= (bank_status[5][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[6] <= (bank_status[6][(CKRP-2):0] =={(CKRP-1){1'b1}});
bank_open[7] <= (bank_status[7][(CKRP-2):0] =={(CKRP-1){1'b1}});
// bank_closed[0] <= (bank_status[0][(CKRP-3):0] == 0);
// bank_closed[1] <= (bank_status[1][(CKRP-3):0] == 0);
// bank_closed[2] <= (bank_status[2][(CKRP-3):0] == 0);
// bank_closed[3] <= (bank_status[3][(CKRP-3):0] == 0);
// bank_closed[4] <= (bank_status[4][(CKRP-3):0] == 0);
// bank_closed[5] <= (bank_status[5][(CKRP-3):0] == 0);
// bank_closed[6] <= (bank_status[6][(CKRP-3):0] == 0);
// bank_closed[7] <= (bank_status[7][(CKRP-3):0] == 0);
 
bank_closed[0] <= (bank_status[0][(CKRP-3):0] == 0);
bank_closed[1] <= (bank_status[1][(CKRP-3):0] == 0);
bank_closed[2] <= (bank_status[2][(CKRP-3):0] == 0);
bank_closed[3] <= (bank_status[3][(CKRP-3):0] == 0);
bank_closed[4] <= (bank_status[4][(CKRP-3):0] == 0);
bank_closed[5] <= (bank_status[5][(CKRP-3):0] == 0);
bank_closed[6] <= (bank_status[6][(CKRP-3):0] == 0);
bank_closed[7] <= (bank_status[7][(CKRP-3):0] == 0);
 
if (w_this_rw_move)
bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 4'h0
bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 2'h0
: write_recycle_clocks;
 
if (cmd_pipe[0])
begin
bank_status[s_bank] <= 1'b0;
if (nxt_pipe[1])
bank_status[s_nxt_bank] <= 1'b1;
end else begin
if (cmd_pipe[1])
bank_status[s_bank] <= 1'b1;
else if (nxt_pipe[1])
bank_status[s_nxt_bank] <= 1'b1;
if (nxt_pipe[0])
bank_status[s_nxt_bank] <= 1'b0;
end
 
if (maintenance_override)
begin
bank_status[0][0] <= 1'b0;
bank_status[1][0] <= 1'b0;
bank_status[2][0] <= 1'b0;
bank_status[3][0] <= 1'b0;
bank_status[4][0] <= 1'b0;
bank_status[5][0] <= 1'b0;
bank_status[6][0] <= 1'b0;
bank_status[7][0] <= 1'b0;
bank_open <= 0;
bank_closed <= 8'hff;
end else if (need_close_bank)
begin
bank_status[close_bank_cmd[16:14]]
<= { bank_status[close_bank_cmd[16:14]][(CKRP-1):0], 1'b0 };
bank_open[close_bank_cmd[16:14]] <= 1'b0;
end else if (need_open_bank)
begin
bank_status[activate_bank_cmd[16:14]]
<= { bank_status[activate_bank_cmd[16:14]][(CKRP-1):0], 1'b1 };
bank_closed[activate_bank_cmd[16:14]] <= 1'b0;
end else if (valid_bank)
; // Read/write command was issued. This neither opens
// nor closes any banks, and hence it needs no logic
// here
else if (maybe_close_next_bank)
begin
bank_status[maybe_close_cmd[16:14]]
<= { bank_status[maybe_close_cmd[16:14]][(CKRP-1):0], 1'b0 };
bank_open[maybe_close_cmd[16:14]] <= 1'b0;
end else if (maybe_open_next_bank)
begin
bank_status[maybe_open_cmd[16:14]]
<= { bank_status[maybe_open_cmd[16:14]][(CKRP-1):0], 1'b1 };
bank_closed[maybe_open_cmd[16:14]] <= 1'b0;
bank_status[0] <= 1'b0;
bank_status[1] <= 1'b0;
bank_status[2] <= 1'b0;
bank_status[3] <= 1'b0;
bank_status[4] <= 1'b0;
bank_status[5] <= 1'b0;
bank_status[6] <= 1'b0;
bank_status[7] <= 1'b0;
end
 
end
 
always @(posedge i_clk)
if (w_this_opening_bank)
bank_address[activate_bank_cmd[16:14]]
<= activate_bank_cmd[13:0];
else if (w_this_maybe_open)
bank_address[maybe_open_cmd[16:14]]
<= maybe_open_cmd[13:0];
if (cmd_pipe[1])
bank_address[s_bank] <= s_row;
else if (nxt_pipe[1])
bank_address[s_nxt_bank] <= s_nxt_row;
 
 
//////////
571,8 → 535,8
//
//
 
reg [BUSNOW:0] bus_active, bus_read, bus_new, bus_ack;
reg [BUSNOW:0] bus_subaddr, bus_odt;
reg [BUSNOW:0] bus_active, bus_read, bus_ack;
reg [BUSNOW:0] bus_subaddr;
initial bus_active = 0;
initial bus_ack = 0;
always @(posedge i_clk)
580,70 → 544,39
bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };
// Drive the d-bus?
bus_read[BUSNOW:0] <= { bus_read[(BUSNOW-1):0], 1'b0 };
// Is this a new command? i.e., the start of a transaction?
bus_new[BUSNOW:0] <= { bus_new[(BUSNOW-1):0], 1'b0 };
bus_odt[BUSNOW:0] <= { bus_odt[(BUSNOW-1):0], 1'b0 };
// Will this position on the bus get a wishbone acknowledgement?
bus_ack[BUSNOW:0] <= { bus_ack[(BUSNOW-1):0], 1'b0 };
//
bus_subaddr[BUSNOW:0] <= { bus_subaddr[(BUSNOW-1):0], 1'b1 };
 
if (w_this_rw_move)
if (cmd_pipe[2])
begin
bus_active[1:0]<= 2'h3; // Data transfers in two clocks
bus_subaddr[1] <= 1'h0;
bus_new[{ 2'b0, rw_sub }] <= 1'b1;
bus_ack[1:0] <= 2'h0;
bus_ack[{ 2'b0, rw_sub }] <= 1'b1;
bus_active[0]<= 1'b1; // Data transfers in one clocks
bus_ack[0] <= 1'b1;
bus_ack[0] <= 1'b1;
 
bus_read[1:0] <= (rw_we)? 2'h0:2'h3;
bus_odt[3:0]<= (rw_we)? 4'he:4'h0; // Data transfers in 2 clks
end else if ((s_pending)&&(!pipe_stall))
begin
if (bus_subaddr[1] == s_sub)
bus_ack[2] <= 1'b1;
if (bus_subaddr[0] == s_sub)
bus_ack[1] <= 1'b1;
bus_read[0] <= !(rw_we);
end
end
 
// Need to set o_wb_dqs high one clock prior to any read.
always @(posedge i_clk)
begin
drive_dqs[1] <= (bus_active[(BUSREG)])
&&(!bus_read[(BUSREG)]);
drive_dqs[0] <= (bus_active[BUSREG:(BUSREG-1)] != 2'b00)
&&(bus_read[BUSREG:(BUSREG-1)] == 2'b00);
end
 
//
//
// Now, let's see, can we issue a read command?
//
//
reg pre_valid;
always @(posedge i_clk)
if ((refresh_ztimer)&&(refresh_instruction[`DDR_NEEDREFRESH]))
pre_valid <= 1'b0;
else if (need_refresh)
pre_valid <= 1'b0;
else
pre_valid <= 1'b1;
wire pre_valid;
assign pre_valid = !maintenance_override;
 
reg pipe_stall;
assign w_r_valid = (pre_valid)&&(r_pending)
&&(bank_status[r_bank][(CKRP-2)])
&&(bank_status[r_bank][0])
&&(bank_address[r_bank]==r_row)
&&((r_we)||(bank_wr_ckzro[r_bank]));
assign w_s_valid = (pre_valid)&&(s_pending)
&&(bank_status[s_bank][(CKRP-2)])
assign w_s_valid = ((pre_valid)&&(s_pending)&&(pipe_stall)
&&(bank_status[s_bank][0])
&&(bank_address[s_bank]==s_row)
&&((s_we)||(bank_wr_ckzro[s_bank]));
assign w_s_match = (s_pending)&&(r_pending)&&(r_we == s_we)
&&(r_row == s_row)&&(r_bank == s_bank)
&&(r_col == s_col)
&&(r_sub)&&(!s_sub);
&&((s_we)||(bank_wr_ckzro[s_bank])));
 
reg pipe_stall;
always @(posedge i_clk)
begin
r_pending <= (i_wb_stb)&&(~o_wb_stall)
652,24 → 585,53
s_pending <= r_pending;
if (~pipe_stall)
begin
pipe_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
o_wb_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
if (r_pending)
begin
pipe_stall <= 1'b1;
o_wb_stall <= 1'b1;
if (!bank_status[r_bank][0])
cmd_pipe <= 3'b010;
else if (bank_address[r_bank] != r_row)
cmd_pipe <= 3'b001; // Read in two clocks
else begin
cmd_pipe <= 3'b100; // Read now
pipe_stall <= 1'b0;
o_wb_stall <= 1'b0;
end
 
if (!bank_status[r_nxt_bank][0])
nxt_pipe <= 2'b10;
else if (bank_address[r_nxt_bank] != r_row)
nxt_pipe <= 2'b01; // Read in two clocks
else
nxt_pipe <= 2'b00; // Next is ready
if (nxt_pipe[1])
nxt_pipe[1] <= 1'b0;
end else begin
cmd_pipe <= 3'b000;
nxt_pipe <= { nxt_pipe[0], 1'b0 };
pipe_stall <= 1'b0;
o_wb_stall <= 1'b0;
end
end else begin // if (pipe_stall)
pipe_stall <= (s_pending)&&((!w_s_valid)||(valid_bank));
o_wb_stall <= (s_pending)&&((!w_s_valid)||(valid_bank));
pipe_stall <= (s_pending)&&(cmd_pipe[0]);
o_wb_stall <= (s_pending)&&(cmd_pipe[0]);
cmd_pipe <= { cmd_pipe[1:0], 1'b0 };
 
nxt_pipe[0] <= (cmd_pipe[0])&&(nxt_pipe[0]);
nxt_pipe[1] <= ((cmd_pipe[0])&&(nxt_pipe[0])) ? 1'b0
: ((cmd_pipe[1])?(|nxt_pipe[1:0]) : nxt_pipe[0]);
end
if (need_refresh)
if (pre_refresh_stall)
o_wb_stall <= 1'b1;
 
if (~pipe_stall)
begin
r_we <= i_wb_we;
r_addr <= i_wb_addr;
r_data <= i_wb_data;
r_row <= i_wb_addr[24:11]; // 14 bits row address
r_bank <= i_wb_addr[10:8];
r_col <= { i_wb_addr[7:1], 3'b000 }; // 10 bits Caddr
r_sub <= i_wb_addr[0]; // Select which 64-bit word
r_row <= i_wb_addr[23:10]; // 14 bits row address
r_bank <= i_wb_addr[9:7];
r_col <= { i_wb_addr[6:0], 3'b000 }; // 10 bits Caddr
r_sel <= i_wb_sel;
 
// i_wb_addr[0] is the 8-bit byte selector of 16-bits (ignored)
678,10 → 640,10
// i_wb_addr[3] is the 64-bit long word selector of 128-bits
 
// pre-emptive work
r_nxt_row <= (i_wb_addr[10:8]==3'h7)
? (i_wb_addr[24:11]+14'h1)
: i_wb_addr[24:11];
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
r_nxt_row <= (i_wb_addr[9:7]==3'h7)
? (i_wb_addr[23:10]+14'h1)
: i_wb_addr[23:10];
r_nxt_bank <= i_wb_addr[9:7]+3'h1;
end
 
if (~pipe_stall)
688,13 → 650,11
begin
// Moving one down the pipeline
s_we <= r_we;
s_addr <= r_addr;
s_data <= r_data;
s_row <= r_row;
s_bank <= r_bank;
s_col <= r_col;
s_sub <= r_sub;
s_sel <= (r_we)?(~r_sel):8'h00;
s_sel <= (r_we)?(~r_sel):16'h00;
 
// pre-emptive work
s_nxt_row <= r_nxt_row;
702,72 → 662,17
end
end
 
assign w_need_close_this_bank = (r_pending)
&&(bank_open[r_bank])
&&(bank_wr_ckzro[r_bank])
&&(r_row != bank_address[r_bank])
||(pipe_stall)&&(s_pending)&&(bank_open[s_bank])
&&(s_row != bank_address[s_bank]);
assign w_need_open_bank = (r_pending)&&(bank_closed[r_bank])
||(pipe_stall)&&(s_pending)&&(bank_closed[s_bank]);
wire [2:0] this_bank;
wire [13:0] this_row;
wire [9:0] this_col;
assign this_bank = (pipe_stall)?s_bank : r_bank;
assign this_row = (pipe_stall)?s_row : r_row;
assign this_col = (pipe_stall)?s_col : r_col;
 
always @(posedge i_clk)
begin
need_close_bank <= (w_need_close_this_bank)
&&(!need_open_bank)
&&(!need_close_bank)
&&(!w_this_closing_bank);
assign w_need_close_this_bank = (cmd_pipe == 3'b000);
wire w_this_bank_valid;
assign w_this_bank_valid = (cmd_pipe[2]);
 
maybe_close_next_bank <= (s_pending)
&&(bank_open[s_nxt_bank])
&&(bank_wr_ckzro[s_nxt_bank])
&&(s_nxt_row != bank_address[s_nxt_bank])
&&(!w_this_maybe_close)&&(!last_maybe_close);
 
close_bank_cmd <= { `DDR_PRECHARGE, r_bank, r_row[13:11], 1'b0, r_row[9:0] };
maybe_close_cmd <= { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[13:11], 1'b0, r_nxt_row[9:0] };
 
 
need_open_bank <= (w_need_open_bank)
&&(!w_this_opening_bank);
last_open_bank <= (w_this_opening_bank);
 
maybe_open_next_bank <= (s_pending)
&&(!need_close_bank)
&&(!need_open_bank)
&&(bank_closed[s_nxt_bank])
&&(!w_this_maybe_open); // &&(!last_maybe_open);
 
activate_bank_cmd<= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
 
 
 
valid_bank <= ((w_r_valid)||((pipe_stall)&&(w_s_valid)))
// &&(!last_valid_bank)&&(!r_move)
&&(!w_this_rw_move);
 
if ((s_pending)&&(pipe_stall))
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
else if (r_pending)
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (r_we)?`DDR_WRITE:`DDR_READ;
else
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= `DDR_NOOP;
if ((s_pending)&&(pipe_stall))
rw_cmd[`DDR_WEBIT-1:0] <= { s_bank, 3'h0, 1'b0, s_col };
else
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 3'h0, 1'b0, r_col };
if ((s_pending)&&(pipe_stall))
rw_sub <= 1'b1 - s_sub;
else
rw_sub <= 1'b1 - r_sub;
if ((s_pending)&&(pipe_stall))
rw_we <= s_we;
else
rw_we <= r_we;
end
 
//
//
// Okay, let's look at the last assignment in our chain. It should look
796,22 → 701,17
else
maintenance_cmd <= (reset_override)?reset_cmd:refresh_cmd;
 
assign w_this_closing_bank = (!maintenance_override)
&&(need_close_bank);
assign w_this_opening_bank = (!maintenance_override)
&&(!need_close_bank)&&(need_open_bank);
assign w_this_rw_move = (!maintenance_override)
&&(!need_close_bank)&&(!need_open_bank)
&&(valid_bank);
assign w_this_maybe_close = (!maintenance_override)
&&(!need_close_bank)&&(!need_open_bank)
&&(!valid_bank)
&&(maybe_close_next_bank);
assign w_this_maybe_open = (!maintenance_override)
&&(!need_close_bank)&&(!need_open_bank)
&&(!valid_bank)
&&(!maybe_close_next_bank)
&&(maybe_open_next_bank);
assign w_need_open_bank = ((r_pending)||(s_pending))
&&(bank_closed[this_bank])
||((pipe_stall)&&(!cmd_b[20]));
 
assign w_this_closing_bank = (!maintenance_override)&&(cmd_pipe[0]);
assign w_this_opening_bank = (!maintenance_override)&&(cmd_pipe[1]);
assign w_this_rw_move = (!maintenance_override)&&(cmd_pipe[2]);
assign w_this_maybe_close = (!maintenance_override)&&(!cmd_pipe[0])&&(nxt_pipe[0]);
assign w_this_maybe_open = (!maintenance_override)&&(!cmd_pipe[1])&&(nxt_pipe[1]);
reg [2:0] r_odt;
 
always @(posedge i_clk)
begin
last_opening_bank <= 1'b0;
818,50 → 718,77
last_closing_bank <= 1'b0;
last_maybe_open <= 1'b0;
last_maybe_close <= 1'b0;
cmd_a <= { `DDR_NOOP, 17'h00 };
cmd_b <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
 
 
// We run our commands by timeslots, A, B, C, and D in that
// order.
 
// Timeslot A always contains any maintenance commands we might
// have.
// Timeslot B always contains any precharge command, excluding
// the maintenance precharge-all command.
// Timeslot C always contains any activate command
// Timeslot D always contains any read/write command
//
// We can always set these commands to whatever, to reduce the
// used logic, as long as the top bit (CS_N) is used to select
// whether or not the command is active. If CS_N is 0 the
// command will be applied by the chip, if 1 the command turns
// into a deselect command that the chip will ignore.
//
cmd_a <= maintenance_cmd;
 
cmd_b <= { `DDR_PRECHARGE, s_nxt_bank, s_nxt_row[13:11], 1'b0, s_nxt_row[9:0] };
cmd_b[20] <= 1'b1; // Deactivate, unless ...
if (cmd_pipe[0])
cmd_b <= { `DDR_PRECHARGE, s_bank, s_row[13:11], 1'b0, s_row[9:0] };
cmd_b[20] <= (!cmd_pipe[0])&&(!nxt_pipe[0]);
 
cmd_c <= { `DDR_ACTIVATE, s_nxt_bank, s_nxt_row[13:11], 1'b0, s_nxt_row[9:0] };
cmd_c[20] <= 1'b1; // Disable command, unless ...
if (cmd_pipe[1])
cmd_c <= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
else if (nxt_pipe[1])
cmd_c[20] <= 1'b0;
 
if (cmd_pipe[2])
begin
cmd_d[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
cmd_d[(`DDR_WEBIT-1):0] <= { s_bank, 3'h0, 1'b0, s_col };
end
cmd_d[20] <= !(cmd_pipe[2]);
 
 
if ((s_pending)&&(pipe_stall))
rw_we <= s_we;
else
rw_we <= r_we;
 
r_odt <= { r_odt[2:1], (cmd_pipe[2])&&(s_we) };
// cmd_d <= rw_cmd;
r_move <= (!cmd_pipe[2]);
 
// Now, if the maintenance mode must override whatever we are
// doing, we only need to apply this more complicated logic
// to the CS_N bit, or bit[20], since this will activate or
// deactivate the rest of the command--making the rest
// either relevant (CS_N=0) or irrelevant (CS_N=1) as we need.
if (maintenance_override)
begin // Command from either reset or refresh logic
cmd_a <= maintenance_cmd;
// cmd_b <= { `DDR_NOOP, ...
end else if (need_close_bank)
begin
cmd_a <= close_bank_cmd;
// cmd_b <= { `DDR_NOOP, ...}
last_closing_bank <= 1'b1;
end else if (need_open_bank)
begin
cmd_a <= activate_bank_cmd;
// cmd_b <={`DDR_NOOP, ...}
last_opening_bank <= 1'b1;
end else if (valid_bank)
begin
cmd_a <= {(rw_cmd[(`DDR_WEBIT)])?`DDR_READ:`DDR_NOOP,
rw_cmd[(`DDR_WEBIT-1):0] };
cmd_b <= {(rw_cmd[(`DDR_WEBIT)])?`DDR_NOOP:`DDR_WRITE,
rw_cmd[(`DDR_WEBIT-1):0] };
end else if (maybe_close_next_bank)
begin
cmd_a <= maybe_close_cmd;
// cmd_b <= {`DDR_NOOP, ... }
last_maybe_close <= 1'b1;
end else if (maybe_open_next_bank)
begin
cmd_a <= maybe_open_cmd;
// cmd_b <= {`DDR_NOOP, ... }
last_maybe_open <= 1'b1;
begin // Over-ride all commands. Make them deselect commands,
// save for the maintenance timeslot.
cmd_a[20] <= 1'b0;
cmd_b[20] <= 1'b1;
cmd_c[20] <= 1'b1;
cmd_d[20] <= 1'b1;
end else
cmd_a <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
cmd_a[20] <= 1'b1; // Disable maintenance timeslot
end
 
`define LGFIFOLN 4
`define FIFOLEN 16
`define LGFIFOLN 3
`define FIFOLEN 8
reg [(`LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
reg [63:0] bus_fifo_data [0:(`FIFOLEN-1)];
reg [7:0] bus_fifo_sel [0:(`FIFOLEN-1)];
reg bus_fifo_sub [0:(`FIFOLEN-1)];
reg bus_fifo_new [0:(`FIFOLEN-1)];
reg [127:0] bus_fifo_data [0:(`FIFOLEN-1)];
reg [15:0] bus_fifo_sel [0:(`FIFOLEN-1)];
reg pre_ack;
 
// The bus R/W FIFO
885,8 → 812,6
end
end
bus_fifo_data[bus_fifo_head] <= s_data;
bus_fifo_sub[bus_fifo_head] <= s_sub;
bus_fifo_new[bus_fifo_head] <= w_this_rw_move;
bus_fifo_sel[bus_fifo_head] <= s_sel;
end
 
895,24 → 820,33
o_ddr_data <= bus_fifo_data[bus_fifo_tail];
always @(posedge i_clk)
ddr_dm <= (bus_ack[BUSREG])? bus_fifo_sel[bus_fifo_tail]
: ((!bus_read[BUSREG])? 8'hff: 8'h00);
: ((!bus_read[BUSREG])? 16'hffff: 16'h0000);
always @(posedge i_clk)
o_ddr_bus_oe <= (bus_active[BUSREG])&&(!bus_read[BUSREG]);
begin
drive_dqs[1] <= (bus_active[(BUSREG)])
&&(!bus_read[(BUSREG)]);
drive_dqs[0] <= (bus_active[BUSREG:(BUSREG-1)] != 2'b00)
&&(bus_read[BUSREG:(BUSREG-1)] == 2'b00);
//
// Is the strobe on during the last clock?
o_ddr_bus_oe[0] <= (|bus_active[BUSREG:(BUSREG-1)])&&(!bus_read[BUSREG]);
// Is data transmitting the bus throughout?
o_ddr_bus_oe[1] <= (bus_active[BUSREG])&&(!bus_read[BUSREG]);
end
 
// First, or left, command
assign o_ddr_cmd_a = { cmd_a, drive_dqs[1], ddr_dm[7:4], ddr_odt };
// Second, or right, command of two
assign o_ddr_cmd_b = { cmd_b, drive_dqs[0], ddr_dm[3:0], ddr_odt };
// First command
assign o_ddr_cmd_a = { cmd_a, drive_dqs[1], ddr_dm[15:12], drive_dqs[0] };
// Second command (of four)
assign o_ddr_cmd_b = { cmd_b, drive_dqs[1], ddr_dm[11: 8], drive_dqs[0] };
// Third command (of four)
assign o_ddr_cmd_c = { cmd_c, drive_dqs[1], ddr_dm[ 7: 4], drive_dqs[0] };
// Fourth command (of four)--occupies the last timeslot
assign o_ddr_cmd_d = { cmd_d, drive_dqs[0], ddr_dm[ 3: 0], drive_dqs[0] };
 
assign w_precharge_all = (cmd_a[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
&&(cmd_a[10]);
 
// ODT must be in high impedence while reset_n=0, then it can be set
// to low or high. As per spec, ODT = 0 during reads
always @(posedge i_clk)
ddr_odt <= bus_odt[BUSREG];
 
always @(posedge i_clk)
o_wb_ack <= pre_ack;
always @(posedge i_clk)
o_wb_data <= i_ddr_data;

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