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    /wbddr3/trunk/rtl
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Rev 2 → Rev 3

/wbddrsdram.v
50,26 → 50,29
// In this controller, 24-bit commands tend to be passed around. These
// 'commands' are bit fields. Here we specify the bits associated with
// the bit fields.
`define DDR_RSTDONE 26
`define DDR_RSTTIMER 25
`define DDR_RSTBIT 24
`define DDR_CKEBIT 23
`define DDR_RSTDONE 26 // End the reset sequence?
`define DDR_RSTTIMER 25 // Does this reset command take multiple clocks?
`define DDR_RSTBIT 24 // Value to place on reset_n
`define DDR_CKEBIT 23 // Should this reset command set CKE?
`define DDR_CMDLEN 23
`define DDR_CSBIT 22
`define DDR_RASBIT 21
`define DDR_CASBIT 20
`define DDR_WEBIT 19
`define DDR_NOPTIMER 18 // Steal this from BA bits
`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
`define DDR_ADDR_BITS 16
`define DDR_ADDR_BITS 14
 
module wbddrsdram(i_clk_200mhz,
module wbddrsdram(i_clk, i_reset,
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stb, o_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_dir,
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
parameter CKREFI4 = 13'd6240; // 4 * 7.8us at 200 MHz clock
input i_clk_200mhz;
parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
CKRFC = 140;
input i_clk, i_reset;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
input [25:0] i_wb_addr;
79,12 → 82,12
output reg o_wb_stall;
output reg [31:0] o_wb_data;
// DDR3 RAM Controller
output wire o_ddr_reset_n;
output wire o_ddr_reset_cke;
output wire o_ddr_reset_n, o_ddr_cke;
// Control outputs
output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
output reg [2:0] o_ddr_dqs;
output wire o_ddr_dqs;
output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_dir;
// Address outputs
output reg [13:0] o_ddr_addr;
output reg [2:0] o_ddr_ba;
92,6 → 95,31
output reg [31:0] o_ddr_data;
input i_ddr_data;
 
reg drive_dqs;
 
// The pending transaction
reg [31:0] r_data;
reg r_pending, r_we;
reg [25:0] r_addr;
reg [14:0] r_row;
reg [2:0] r_bank;
reg [9:0] r_col;
reg [1:0] r_sub;
reg r_move; // It was accepted, and can move to next stage
 
// Can the pending transaction be satisfied with the current (ongoing)
// transaction?
reg m_move, m_match, m_continue, m_pending, m_we;
reg [25:0] m_addr;
reg [14:0] m_row;
reg [2:0] m_bank;
reg [9:0] m_col;
reg [1:0] m_sub;
 
// Can we preload the next bank?
reg [14:0] r_nxt_row;
reg [2:0] r_nxt_bank;
//
// tWTR = 7.5
// tRRD = 7.5
130,37 → 158,37
// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
// timer commands indicate whether or not the command during the timer is to
// be set to idle, or whether the command is instead left as it was.
reg reset_override;
reg reset_override, reset_ztimer;
reg [3:0] reset_address;
reg [22:0] reset_cmd;
reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd, refresh_cmd;
reg [26:0] reset_instruction;
initial reset_override <= 1'b1;
initial reset_address <= 4'h0;
reg [16:0] reset_timer;
initial reset_override = 1'b1;
initial reset_address = 4'h0;
always @(posedge i_clk)
if (i_reset)
begin
reset_override <= 1'b1;
reset_cmd <= { `DDR_NOOP_CMD, reset_instruction[18:0]};
reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
end else if (!reset_ztimer)
;
else if (reset_instruction[`DDR_RESET_DONE])
else if (reset_instruction[`DDR_RSTDONE])
reset_override <= 1'b0;
else if (reset_instruction[`DDR_RSTTIMER])
begin
if (reset_instruction[29])
reset_cmd <= { `DDR_NOOP_CMD, reset_instruction[20:0]};
if (reset_instruction[`DDR_NOPTIMER])
reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
end else begin
reset_cmd[CKE] <= reset_instruction[27];
reset_cmd[~CKE] <= reset_instruction[22:0];
reset_cmd <= reset_instruction[22:0];
end
always @(posedge i_clk)
if (i_reset)
o_ddr_cke <= 1'b0;
else if (reset_override)&&(reset_ztimer)
else if ((reset_override)&&(reset_ztimer))
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
 
initial reset_ztimer <= 1'b1; // Is the timer zero?
initial reset_timer <= 17'h00;
initial reset_ztimer = 1'b1; // Is the timer zero?
initial reset_timer = 17'h00;
always @(posedge i_clk)
if (i_reset)
begin
178,14 → 206,15
always @(posedge i_clk)
case(reset_address)
case(reset_address) // RSTDONE, TIMER, CKE, ??
4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
4'h3: reset_instruction <= { 4'h3, `DDR_MRS, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
// 4'h5: reset_instruction <= { 4'h3, `DDR_MRS, 3'h3, 13'h0, 2'b00 }; // MRS3
4'h5: reset_instruction <= { 4'h3, `DDR_MRS, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
4'h7: reset_instruction <= { 4'h3, `DDR_MRS, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
4'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
4'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
default:
reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
endcase
195,7 → 224,7
if (i_reset)
reset_address <= 4'h0;
else if (reset_ztimer)
reset_addres <= reset_address + 4'h1;
reset_address <= reset_address + 4'h1;
//
// initial reset_mem =
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
224,7 → 253,10
//
//
//
reg need_refresh;
 
wire w_precharge_all;
reg banks_are_closing, all_banks_closed;
reg [2:0] bank_status[7:0];
always @(posedge i_clk)
begin
267,11 → 299,11
end
 
always @(posedge i_clk)
if (cmd == OPEN_BANK)
bank_row[cmd_bank] <= cmd_address[14:0];
// if (cmd[22:19] == `DDR_ACTIVATE)
if (need_open_bank)
bank_address[activate_bank_cmd[18:16]]
<= activate_bank_cmd[14:0];
 
 
 
//
//
// Okay, let's investigate when we need to do a refresh. Our plan will be to
288,9 → 320,12
//
//
//
reg midrefresh, refresh_clear, endrefresh;
reg [12:0] refresh_clk;
reg [2:0] midrefresh_hctr; // How many refresh cycles?
reg [8:0] midrefresh_lctr; // How many clks in this refresh cycle
always @(posedge i_clk)
if ((endrefresh)&&(refresh_clear))
if ((reset_override)||(refresh_clear))
refresh_clk <= CKREFI4;
else if (|refresh_clk)
refresh_clk <= refresh_clk-1;
297,35 → 332,29
always @(posedge i_clk)
need_refresh <= (refresh_clk == 0)||(midrefresh);
always @(posedge i_clk)
if (need_refresh)
refresh_count <= refresh_count - 1;
else
refresh_count <= 0;
always @(posedge i_clk)
if (!need_refresh)
refresh_cmd <= NOOP;
refresh_cmd <= { `DDR_NOOP, 19'h00 };
else if (~banks_are_closing)
refresh_cmd <= CLOSE_ALL_BANKS;
refresh_cmd <= { `DDR_PRECHARGE, 3'h0, 5'h0, 1'b1, 10'h00 };
else if (~all_banks_closed)
refresh_cmd <= NOOP;
refresh_cmd <= { `DDR_NOOP, 19'h00 };
else
refresh_cmd <= REFRESH;
refresh_cmd <= { `DDR_REFRESH, 19'h00 };
always @(posedge i_clk)
midrefresh <= (need_refresh)&&(all_banks_closed)&&(~endrefresh);
midrefresh <= (need_refresh)&&(all_banks_closed)&&(~refresh_clear);
 
always @(posedge i_clk)
if (!mid_refresh)
if (!midrefresh)
midrefresh_hctr <= 3'h4;
else if ((midrefresh_lctr == 0)&&(|midrefresh_hctr))
midrefresh_hctr <= midrefresh_hctr - 1;
always @(posedge i_clk)
if (!need_refresh)||(!mid_refresh)
if ((!need_refresh)||(!midrefresh))
endrefresh <= 1'b0;
else if (midrefresh_hctr == 3'h0)
endrefresh <= 1'b1;
always @(posedge i_clk)
if (!mid_refresh)
if (!midrefresh)
midrefresh_lctr <= CKRFC;
else if (midrefresh_lctr == 0)
midrefresh_lctr <= 0;
333,7 → 362,7
midrefresh_lctr <= CKRFC;
 
always @(posedge i_clk)
refresh_clear <= (needrefresh)&&(endrefresh)&&(midrefresh_lctr == 0);
refresh_clear <= (need_refresh)&&(endrefresh)&&(midrefresh_lctr == 0);
 
 
//
342,16 → 371,14
// writing?
//
//
reg [8:0] bus_active, bus_read, bus_mask, bus_ack;
reg [8:0] bus_active, bus_read;
reg [1:0] bus_subaddr [8:0];
assign pre_cmd = (~reset_override)&&(~need_refresh)&&(valid_bank)
&&(bus_active[2:0]==3'h0)
initial bus_active <= 0;
initial bus_active = 0;
always @(posedge i_clk)
begin
bus_active[8:0] <= { bus_active[7:0], 1'b0 };
bus_read[8:0] <= { bus_read[7:0], 1'b0 }; // Drive the d-bus?
bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
bus_subaddr[8] <= bus_subaddr[7];
bus_subaddr[7] <= bus_subaddr[6];
bus_subaddr[6] <= bus_subaddr[5];
361,7 → 388,7
bus_subaddr[2] <= bus_subaddr[1];
bus_subaddr[1] <= bus_subaddr[0];
bus_subaddr[0] <= 2'h3;
if (cmd == READ)
if (cmd[22:19] == `DDR_READ)
begin
bus_active[3:0]<= 4'hf; // Once per clock
bus_read[3:0] <= 4'hf; // These will be reads
368,8 → 395,7
bus_subaddr[3] <= 2'h0;
bus_subaddr[2] <= 2'h1;
bus_subaddr[1] <= 2'h2;
bus_ack[r_sub] <= 1'b1;
end else if (cmd == WRITE)
end else if (cmd == `DDR_WRITE)
begin
bus_active[3:0] <= 4'hf;
// bus_read[7:4] = 4'h0;
376,14 → 402,11
bus_subaddr[3] <= 2'h0;
bus_subaddr[2] <= 2'h1;
bus_subaddr[1] <= 2'h2;
bus_ack[r_sub] <= 1'b1;
bus_mask[r_sub] <= 1'b0;
bus_data[r_sub] <= r_data;
end
end
 
always @(posedge i_clk)
drive_dqs <= (~bus_read[8])&&(|busactive[8:7]);
drive_dqs <= (~bus_read[8])&&(|bus_active[8:7]);
 
//
//
394,11 → 417,11
begin
if ((i_wb_stb)&&(~o_wb_stall))
begin
pending <= 1'b1;
r_pending <= 1'b1;
o_wb_stall <= 1'b1;
end else if ((r_move)||(m_move))
begin
pending <= 1'b0;
r_pending <= 1'b0;
o_wb_stall <= 1'b0;
end
 
418,8 → 441,14
end
end
 
reg need_close_bank, last_close_bank,
need_open_bank, last_open_bank;
reg [2:0] bank_active[7:0];
reg [14:0] bank_address[7:0];
 
reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd, rw_cmd;
reg need_close_bank, need_close_this_bank,
last_close_bank, maybe_close_next_bank,
need_open_bank, last_open_bank, maybe_open_next_bank,
valid_bank, last_valid_bank;
always @(posedge i_clk)
begin
need_close_bank <= (r_pending)&&(bank_active[r_bank][0])
434,31 → 463,31
&&(!need_close_this_bank);
 
close_bank_cmd <= (maybe_close_next_bank)
? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[15:11], 1'b0, r_nxt_row[9:0] };
? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[14:10], 1'b0, r_nxt_row[9:0] }
: { `DDR_PRECHARGE, r_bank, r_row[15:11], 1'b0, r_row[9:0] };
 
 
need_open_bank <= (r_pending)&&(bank_active[r_bank]==2'b00)
need_open_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b00)
&&(!last_open_bank);
last_open_bank <= need_open_bank;
 
maybe_open_next_bank <= (r_pending)
&&(bank_active[r_nxt_bank] == 2'b00)
&&(bank_active[r_nxt_bank][1:0] == 2'b00)
&&(!need_open_bank)&&(!need_close_bank);
 
activate_bank_cmd <= (maybe_open_next_bank)
? { `DDR_ACTIVATE,r_nxt_bank,r_nxt_row[15:10] };
: { `DDR_ACTIVATE, r_bank, r_row[15:10] };
? { `DDR_ACTIVATE,r_nxt_bank,1'b0,r_nxt_row[14:0] }
: { `DDR_ACTIVATE, r_bank, 1'b0,r_row[14:0] };
 
 
 
valid_bank <= (r_pending)&&(bank_active[r_bank]==2'b11)
valid_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b11)
&&(bank_address[r_bank]==r_row)
&&(!last_valid_bank);
last_valid_bank <= need_valid_bank;
last_valid_bank <= valid_bank;
 
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (~r_pending)?`DDR_NOOP:((r_we)?`DDR_WRITE:`DDR_READ);
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col }
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col };
end
 
 
478,15 → 507,15
end else if (m_match)
m_sub <= r_sub;
 
m_match <= (m_pending)&&(pending)&&(r_we == m_we)
m_match <= (m_pending)&&(r_pending)&&(r_we == m_we)
&&(r_row == m_row)&&(r_bank == m_bank)
&&(r_col == m_col)
&&(r_sub > m_sub);
m_continue <= (m_pending)&&(pending)&&(r_we == m_we)
m_continue <= (m_pending)&&(r_pending)&&(r_we == m_we)
&&(r_row == m_row)&&(r_bank == m_bank)
&&(r_col == m_col+8'h1)
m_nextbank <= (m_pending)&&(pending)&&(r_we == m_we)
&&(r_row == m_row)&&(r_bank == m_bank)
&&(r_col == m_col+10'h1);
// m_nextbank <= (m_pending)&&(r_pending)&&(r_we == m_we)
// &&(r_row == m_row)&&(r_bank == m_bank);
end
 
//
494,14 → 523,14
// Okay, let's look at the last assignment in our chain. It should look
// something like:
always @(posedge i_clk)
o_ddr_reset_n <= (~reset_override)||(reset_cmd[DDR_RSTBIT]);
o_ddr_reset_n <= (~reset_override)||(reset_instruction[`DDR_RSTBIT]);
always @(posedge i_clk)
o_ddr_cke <= (~reset_override)||(reset_cmd[DDR_CKEBIT]);
o_ddr_cke <= (~reset_override)||(reset_instruction[`DDR_CKEBIT]);
always @(posedge i_clk)
begin
r_move <= 1'b0;
if (reset_override)
cmd <= reset_command[DDR_CSBIT:0];
cmd <= reset_cmd[`DDR_CSBIT:0];
else if (need_refresh)
begin
cmd <= refresh_cmd; // The command from the refresh logc
514,23 → 543,25
cmd <= rw_cmd;
r_move <= 1'b1;
end else
cmd <= noop;
cmd <= { `DDR_NOOP, rw_cmd[20:0] };
end
 
assign o_ddr_cs_n = cmd[DDR_CSBIT];
assign o_ddr_ras_n = cmd[DDR_RASBIT];
assign o_ddr_cas_n = cmd[DDR_CASBIT];
assign o_ddr_we_n = bus_read[8];
reg [31:0] bus_data[8:0];
 
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
assign o_ddr_ras_n = cmd[`DDR_RASBIT];
assign o_ddr_cas_n = cmd[`DDR_CASBIT];
assign o_ddr_we_n = cmd[`DDR_WEBIT];
assign o_ddr_dqs = drive_dqs;
assign o_ddr_addr = cmd[(DDR_ADDR_BITS-1):0];
assign o_ddr_ba = cmd[DDR_BABITS+DDR_ADDR_BITS-1:DDR_ADDR_BITS];
assign o_ddr_addr = cmd[(`DDR_ADDR_BITS-1):0];
assign o_ddr_ba = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
assign o_ddr_data = bus_data[8];
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
assign w_precharge_all = (cmd[DDR_CSBIT:DDR_WEBIT]==`DDR_PRECHARGE)
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
&&(o_ddr_addr[10]); // 5 bits
 
// Need to set o_wb_dqs high one clock prior to any read.
// As per spec, ODT = 0 during reads
assign o_ddr_bus_dir = bus_read[8];
assign o_ddr_odt = o_ddr_bus_dir;
 
 

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