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/src/spec.tex
86,7 → 86,7
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When I then needed to make the project run in real-time, as opposed to the |
manually stepped approach, I generated a scope like this one. I had already |
bench tested the components on the hardware itself. Thu, testing and |
bench tested the components on the hardware itself. Thus, testing and |
development continued on the hardware, and the scope helped me see what was |
going right or wrong. The great advantage of the approach was that, at the |
end of the project, I didn't need to do any hardware in the loop testing. |
160,27 → 160,30
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Let's go through that list again. First, before using the scope, the holdoff |
needs to be set. The scope is designed so that setting the scope control value |
to the holdoff alone will reset the scope from whatever condition it was in, |
to the holdoff alone, with all other bits set to zero, will reset the scope |
from whatever condition it was in, |
freeing it to run. Once running, then upon every clock enabled clock, one |
sample of data is read into the scope and recorded. Once every memory value |
is filled, the scope has been {\tt PRIMED}. Once the scope has been |
{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be |
active on a clock--enabled input, the scope will then be {\tt TRIGGERED}. It |
active on an input clock with the clock--enable line set, the scope will then |
be {\tt TRIGGERED}. It |
will then count for the number of clocks in the holdoff before stopping |
collection, placing it in the {\tt STOPPED} state. (Don't change the holdoff |
during between triggered and stopped, or it may stop at some other non--holdoff |
value!) If the holdoff is zero, the last sample in the buffer will be the |
sample containing the trigger. Likewise if the holdoff is one less than the |
size of the memory, the first sample in the buffer will be the one containing |
the trigger. |
collection, placing it in the {\tt STOPPED} state. \footnote{You can even |
change the holdoff while the scope is running by writing a new holdoff value |
together with setting the {\tt RESET\_n} bit of the control register. However, |
if you do this after the core has triggered it may stop at some other |
non--holdoff value!} If the holdoff is zero, the last sample in the buffer |
will be the sample containing the trigger. Likewise if the holdoff is one |
less than the size of the memory, the first sample in the buffer will be the |
one containing the trigger. |
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There are two further commands that will affect the operation of the scope. The |
first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing |
the holdoff to the control register while setting this bit high. This will |
cause the scope to trigger immediately. If coupled with a {\tt RESET} command, |
that is if the {\tt RESET\_n} bit isn't also set, then recording will start |
at the beginning and the scope will first wait until its {\tt PRIMED} state |
before the manual trigger takes effect. |
cause the scope to trigger as soon as it is primed. If the {\tt RESET\_n} |
bit is also set so as to prevent an internal reset, and if the scope was already |
primed, then manual trigger command will cause it to trigger immediately. |
|
The last command that can affect the operation of the scope is the {\tt DISABLE} |
command/bit in the control register. Setting this bit will prevent the scope |
192,10 → 195,11
reasonable amount of time. |
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So, in summary, to use this scope you first set the holdoff value in the |
control register. Second, you wait until the scope has been {\tt TRIGGERED} and |
stopped. Finally, you read from the data register once for every memory value |
in the buffer and you can then sit back, relax, and study what took place |
within the FPGA. |
control register. Second, you wait until the scope has been {\tt TRIGGERED} |
and {\tt STOPPED}. Finally, you read from the data register once for every |
memory value in the buffer and you can then sit back, relax, and study what |
took place within the FPGA. Additional modes allow you to manually trigger |
the scope, or to disable the automatic trigger entirely. |
|
\chapter{Registers} |
|
331,7 → 335,11
registers become 32--bit reads and writes to this interface. You may also wish |
to note that the scope supports pipeline reads from the data port, to speed |
up reading the results out. |
|
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What this table doesn't show is that all accesses to the port take a single |
clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the |
{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall} |
line is tied to zero. |
\chapter{IO Ports} |
|
The ports are listed in Table.~\ref{tbl:ioports}. |