URL
https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
Subversion Repositories wbuart32
Compare Revisions
- This comparison shows the changes necessary to convert path
/wbuart32/trunk/bench/cpp
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/helloworld.cpp
44,6 → 44,7
#include <sys/types.h> |
#include <signal.h> |
#include "verilated.h" |
#include "verilated_vcd_c.h" |
#include "Vhelloworld.h" |
#include "uartsim.h" |
|
52,21 → 53,42
Vhelloworld tb; |
UARTSIM *uart; |
int port = 0; |
unsigned setup = 25, testcount = 0; |
unsigned setup = 868, clocks = 0, baudclocks; |
|
tb.i_setup = setup; |
uart = new UARTSIM(port); |
uart->setup(tb.i_setup); |
baudclocks = tb.i_setup & 0xfffffff; |
|
while(testcount++ < 0x7f000000) { |
#define VCDTRACE |
#ifdef VCDTRACE |
Verilated::traceEverOn(true); |
VerilatedVcdC* tfp = new VerilatedVcdC; |
tb.trace(tfp, 99); |
tfp->open("helloworld.vcd"); |
#define TRACE_POSEDGE tfp->dump(10*clocks) |
#define TRACE_NEGEDGE tfp->dump(10*clocks+5) |
#define TRACE_CLOSE tfp->close() |
#else |
#define TRACE_POSEDGE |
#define TRACE_NEGEDGE |
#define TRACE_CLOSE |
#endif |
|
clocks = 0; |
while(clocks < 16*32*baudclocks) { |
|
tb.i_clk = 1; |
tb.eval(); |
TRACE_POSEDGE; |
tb.i_clk = 0; |
tb.eval(); |
TRACE_NEGEDGE; |
|
(*uart)(tb.o_uart_tx); |
clocks++; |
} |
|
TRACE_CLOSE; |
printf("\n\nSimulation complete\n"); |
} |