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URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

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  • This comparison shows the changes necessary to convert path 
    /wbuart32/trunk/bench/verilog
    from Rev 15 to Rev 18
    ↔ Reverse comparison
  •

Rev 15 → Rev 18

/Makefile
18,7 → 18,7
##
## // If we have a 100MHz clock, then we can set up for a 115,200
## // baud clock by setting i_setup to (100MHz / 115200) ~= 868.
## // The upper bits of this number also set the protocol to
## // The upper bits of this number also set the protocol to
## // one stop bit, no parity, and 8 data bits.
## assign i_setup = 30'd868; // 115,200 Baud 8N1
##
58,7 → 58,7
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
74,6 → 74,8
FBDIR := .
VDIRFB:= $(FBDIR)/obj_dir
RTLDR := ../../rtl
VERILATOR := verilator
VFLAGS := -Wall --MMD --trace -y ../../rtl -cc
 
.PHONY: test testline testhello speechfifo
test: testline testhello speechfifo
99,7 → 101,7
$(SPEECHVFILES): speechfifo.v $(SPEECHSRCS)
 
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator --trace -cc -y ../../rtl $*.v
$(VERILATOR) $(VFLAGS) $*.v
 
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
111,3 → 113,7
rm -rf $(VDIRFB)/*.h
rm -rf $(VDIRFB)/
 
DIRS := $(wildcard $(VDIRFB)/*.d)
ifneq ($(DIRS),)
-include $(DIRS)
endif
/linetest.v
91,7 → 91,7
reg pwr_reset;
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset = 1'b0;
pwr_reset <= 1'b0;
 
 
 
102,7 → 102,10
// Data (rx_data) is present when rx_stb is true. Any parity or
// frame errors will also be valid at that time. Finally, we'll ignore
// errors, and even the clocked uart input distributed from here.
wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
wire rx_stb, rx_break, rx_perr, rx_ferr;
/* verilator lint_off UNUSED */
wire rx_ignored;
/* verilator lint_on UNUSED */
wire [7:0] rx_data;
 
`ifdef USE_LITE_UART
/speechfifo.v
21,7 → 21,7
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
72,6 → 72,10
// i_setup, but at least it gives us something to start with/from.
parameter INITIAL_UART_SETUP = 31'd868;
 
// Let's set our message length, in case we ever wish to change it in
// the future
localparam MSGLEN=2203;
 
// The i_setup wires are input when run under Verilator, but need to
// be set internally if this is going to run as a standalone top level
// test configuration.
87,11 → 91,22
reg [1:0] wb_addr;
reg [31:0] wb_data;
 
wire uart_stall, uart_ack;
wire uart_stall;
 
// We aren't using the receive interrupts, or the received data, or the
// ready to send line, so we'll just mark them all here as ignored.
 
/* verilator lint_off UNUSED */
wire uart_ack, tx_int;
wire [31:0] uart_data;
wire ignored_rx_int, ignored_rxfifo_int;
wire rts_n_ignored;
/* verilator lint_on UNUSED */
 
wire tx_int, txfifo_int;
/* verilator lint_on UNUSED */
 
wire txfifo_int;
 
// The next four lines create a strobe signal that is true on the first
// clock, but never after. This makes for a decent power-on reset
// signal.
107,7 → 122,7
// element to a space so that if (for some reason) we broadcast past the
// end of our message, we'll at least be sending something useful.
integer i;
reg [7:0] message [0:2047];
reg [7:0] message [0:4095];
initial begin
// xx Verilator needs this file to be in the directory the file
// is run from. For that reason, the project builds, makes,
121,8 → 136,9
// synthesis tool can find it.
//
$readmemh("speech.hex", message);
for(i=1481; i<2048; i=i+1)
for(i=MSGLEN; i<4095; i=i+1)
message[i] = 8'h20;
 
//
// The problem with the above approach is Xilinx's ISE program.
// It's broken. It can't handle HEX files well (at all?) and
164,8 → 180,8
// transmit next. Note, there's a clock delay between setting this
// index and when the wb_data is valid. Hence, we set the index on
// restart[0] to zero.
reg [10:0] msg_index;
initial msg_index = 11'd2040;
reg [11:0] msg_index;
initial msg_index = 12'h000 - 12'h8;
always @(posedge i_clk)
begin
if (restart)
220,7 → 236,7
if (restart)
end_of_message <= 1'b0;
else
end_of_message <= (msg_index >= 1481);
end_of_message <= (msg_index >= MSGLEN);
 
// The wb_stb signal indicates that we wish to write, using the wishbone
// to our peripheral. We have two separate types of writes. First,
248,10 → 264,6
// But once the FIFO gets to half full, stop.
wb_stb <= 1'b0;
 
// We aren't using the receive interrupts, so we'll just mark them
// here as ignored.
wire ignored_rx_int, ignored_rxfifo_int;
 
// The WBUART can handle hardware flow control signals. This test,
// however, cannot. The reason? Simply just to keep things simple.
// If you want to add hardware flow control to your design, simply
259,7 → 271,7
//
// Since this is an output only module demonstrator, what would be the
// cts output is unused.
wire cts_n, rts_n_ignored;
wire cts_n;
assign cts_n = 1'b0;
 
// Finally--the unit under test--now that we've set up all the wires

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