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/trunk/bench/cpp/uartsim.cpp
0,0 → 1,342
////////////////////////////////////////////////////////////////////////////////
//
// Filename: uartsim.cpp
//
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To forward a Verilator simulated UART link over a TCP/IP pipe.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <poll.h>
#include <unistd.h>
#include <arpa/inet.h>
#include <signal.h>
#include <ctype.h>
 
#include "uartsim.h"
 
void UARTSIM::setup_listener(const int port) {
struct sockaddr_in my_addr;
 
signal(SIGPIPE, SIG_IGN);
 
printf("Listening on port %d\n", port);
 
m_skt = socket(AF_INET, SOCK_STREAM, 0);
if (m_skt < 0) {
perror("Could not allocate socket: ");
exit(-1);
}
 
// Set the reuse address option
{
int optv = 1, er;
er = setsockopt(m_skt, SOL_SOCKET, SO_REUSEADDR, &optv, sizeof(optv));
if (er != 0) {
perror("SockOpt Err:");
exit(-1);
}
}
 
memset(&my_addr, 0, sizeof(struct sockaddr_in)); // clear structure
my_addr.sin_family = AF_INET;
// Use *all* internet ports to this computer, allowing connections from
// any/every one of them.
my_addr.sin_addr.s_addr = htonl(INADDR_ANY);
my_addr.sin_port = htons(port);
if (bind(m_skt, (struct sockaddr *)&my_addr, sizeof(my_addr))!=0) {
perror("BIND FAILED:");
exit(-1);
}
 
if (listen(m_skt, 1) != 0) {
perror("Listen failed:");
exit(-1);
}
}
 
UARTSIM::UARTSIM(const int port) {
m_conrd = m_conwr = m_skt = -1;
if (port == 0) {
m_conrd = STDIN_FILENO;
m_conwr = STDOUT_FILENO;
} else
setup_listener(port);
setup(25); // Set us up for (default) 8N1 w/ a baud rate of CLK/25
m_rx_baudcounter = 0;
m_tx_baudcounter = 0;
m_rx_state = RXIDLE;
m_tx_state = TXIDLE;
}
 
void UARTSIM::kill(void) {
// Close any active connection
if (m_conrd >= 0) close(m_conrd);
if ((m_conwr >= 0)&&(m_conwr != m_conrd)) close(m_conwr);
if (m_skt >= 0) close(m_skt);
 
m_conrd = m_conwr = m_skt = -1;
}
 
void UARTSIM::setup(unsigned isetup) {
if (isetup != m_setup) {
m_setup = isetup;
m_baud_counts = (isetup & 0x0ffffff);
m_nbits = 8-((isetup >> 28)&0x03);
m_nstop =((isetup >> 27)&1)+1;
m_nparity = (isetup >> 26)&1;
m_fixdp = (isetup >> 25)&1;
m_evenp = (isetup >> 24)&1;
}
}
 
int UARTSIM::nettick(int i_tx) {
int o_rx = 1;
 
if ((m_conrd < 0)&&(m_conwr<0)&&(m_skt>=0)) {
// Can we accept a connection?
struct pollfd pb;
 
pb.fd = m_skt;
pb.events = POLLIN;
poll(&pb, 1, 0);
 
if (pb.revents & POLLIN) {
m_conrd = accept(m_skt, 0, 0);
m_conwr = m_conrd;
 
if (m_conrd < 0)
perror("Accept failed:");
}
}
 
if ((!i_tx)&&(m_last_tx))
m_rx_changectr = 0;
else m_rx_changectr++;
m_last_tx = i_tx;
 
if (m_rx_state == RXIDLE) {
if (!i_tx) {
m_rx_state = RXDATA;
m_rx_baudcounter =m_baud_counts+m_baud_counts/2;
m_rx_baudcounter -= m_rx_changectr;
m_rx_busy = 0;
m_rx_data = 0;
}
} else if (m_rx_baudcounter <= 0) {
if (m_rx_busy >= (1<<(m_nbits+m_nparity+m_nstop-1))) {
m_rx_state = RXIDLE;
if (m_conwr >= 0) {
char buf[1];
buf[0] = (m_rx_data >> (32-m_nbits-m_nstop-m_nparity))&0x0ff;
if (1 != send(m_conwr, buf, 1, 0)) {
close(m_conwr);
m_conrd = m_conwr = -1;
}
}
} else {
m_rx_busy = (m_rx_busy << 1)|1;
// Low order bit is transmitted first, in this
// order:
// Start bit (1'b1)
// bit 0
// bit 1
// bit 2
// ...
// bit N-1
// (possible parity bit)
// stop bit
// (possible secondary stop bit)
m_rx_data = ((i_tx&1)<<31) | (m_rx_data>>1);
} m_rx_baudcounter = m_baud_counts;
} else
m_rx_baudcounter--;
 
if (m_tx_state == TXIDLE) {
struct pollfd pb;
pb.fd = m_conrd;
pb.events = POLLIN;
if (poll(&pb, 1, 0) < 0)
perror("Polling error:");
if (pb.revents & POLLIN) {
char buf[1];
if (1 == recv(m_conrd, buf, 1, MSG_DONTWAIT)) {
m_tx_data = (-1<<(m_nbits+m_nparity+1))
// << nstart_bits
|((buf[0]<<1)&0x01fe);
if (m_nparity) {
int p;
 
// If m_nparity is set, we need to then
// create the parity bit.
if (m_fixdp)
p = m_evenp;
else {
p = (m_tx_data >> 1)&0x0ff;
p = p ^ (p>>4);
p = p ^ (p>>2);
p = p ^ (p>>1);
p &= 1;
p ^= m_evenp;
}
m_tx_data |= (p<<(m_nbits+m_nparity));
}
m_tx_busy = (1<<(m_nbits+m_nparity+m_nstop+1))-1;
m_tx_state = TXDATA;
o_rx = 0;
m_tx_baudcounter = m_baud_counts;
}
}
} else if (m_tx_baudcounter == 0) {
m_tx_data >>= 1;
m_tx_busy >>= 1;
if (!m_tx_busy)
m_tx_state = TXIDLE;
else
m_tx_baudcounter = m_baud_counts;
o_rx = m_tx_data&1;
} else {
m_tx_baudcounter--;
o_rx = m_tx_data&1;
}
 
return o_rx;
}
 
int UARTSIM::fdtick(int i_tx) {
int o_rx = 1;
 
if ((!i_tx)&&(m_last_tx))
m_rx_changectr = 0;
else m_rx_changectr++;
m_last_tx = i_tx;
 
if (m_rx_state == RXIDLE) {
if (!i_tx) {
m_rx_state = RXDATA;
m_rx_baudcounter =m_baud_counts+m_baud_counts/2;
m_rx_baudcounter -= m_rx_changectr;
m_rx_busy = 0;
m_rx_data = 0;
}
} else if (m_rx_baudcounter <= 0) {
if (m_rx_busy >= (1<<(m_nbits+m_nparity+m_nstop-1))) {
m_rx_state = RXIDLE;
if (m_conwr >= 0) {
char buf[1];
buf[0] = (m_rx_data >> (32-m_nbits-m_nstop-m_nparity))&0x0ff;
if (1 != write(m_conwr, buf, 1)) {
fprintf(stderr, "ERR while attempting to write out--closing output port\n");
perror("UARTSIM::write() ");
m_conrd = m_conwr = -1;
}
}
} else {
m_rx_busy = (m_rx_busy << 1)|1;
// Low order bit is transmitted first, in this
// order:
// Start bit (1'b1)
// bit 0
// bit 1
// bit 2
// ...
// bit N-1
// (possible parity bit)
// stop bit
// (possible secondary stop bit)
m_rx_data = ((i_tx&1)<<31) | (m_rx_data>>1);
} m_rx_baudcounter = m_baud_counts;
} else
m_rx_baudcounter--;
 
if ((m_tx_state == TXIDLE)&&(m_conrd >= 0)) {
struct pollfd pb;
pb.fd = m_conrd;
pb.events = POLLIN;
if (poll(&pb, 1, 0) < 0)
perror("Polling error:");
if (pb.revents & POLLIN) {
char buf[1];
int nr;
if (1==(nr = read(m_conrd, buf, 1))) {
m_tx_data = (-1<<(m_nbits+m_nparity+1))
// << nstart_bits
|((buf[0]<<1)&0x01fe);
if (m_nparity) {
int p;
 
// If m_nparity is set, we need to then
// create the parity bit.
if (m_fixdp)
p = m_evenp;
else {
p = (m_tx_data >> 1)&0x0ff;
p = p ^ (p>>4);
p = p ^ (p>>2);
p = p ^ (p>>1);
p &= 1;
p ^= m_evenp;
}
m_tx_data |= (p<<(m_nbits+m_nparity));
}
m_tx_busy = (1<<(m_nbits+m_nparity+m_nstop+1))-1;
m_tx_state = TXDATA;
o_rx = 0;
m_tx_baudcounter = m_baud_counts;
} else if (nr < 0) {
fprintf(stderr, "ERR while attempting to read in--closing input port\n");
perror("UARTSIM::read() ");
m_conrd = -1;
} // and we really don't care if nr == 0 except that
// the poll above is supposed to keep it from happening
}
} else if (m_tx_baudcounter == 0) {
m_tx_data >>= 1;
m_tx_busy >>= 1;
if (!m_tx_busy)
m_tx_state = TXIDLE;
else
m_tx_baudcounter = m_baud_counts;
o_rx = m_tx_data&1;
} else {
m_tx_baudcounter--;
o_rx = m_tx_data&1;
}
 
return o_rx;
}
 
/trunk/bench/cpp/linetest.cpp
0,0 → 1,219
////////////////////////////////////////////////////////////////////////////////
//
// Filename: linetest.cpp
//
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To create a pass-through test of the receiver and transmitter
// which can be exercised/proven via Verilator.
//
// If you run this program with no arguments, it will run an automatic
// test, returning "SUCCESS" on success, or "FAIL" on failure as a last
// output line--hence it should support automated testing.
//
// If you run with a '-i' argument, the program will run interactively.
// It will then be up to you to determine if it works (or not). As
// always, it may be killed with a control C.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <fcntl.h>
#include <unistd.h>
#include <string.h>
#include <time.h>
#include <sys/types.h>
#include <signal.h>
#include "verilated.h"
#include "Vlinetest.h"
#include "uartsim.h"
 
int main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
Vlinetest tb;
UARTSIM *uart;
bool run_interactively = false;
int port = 0;
unsigned setup = 25;
 
for(int argn=1; argn<argc; argn++) {
if (argv[argn][0] == '-') for(int j=1; (j<1000)&&(argv[argn][j]); j++)
switch(argv[argn][j]) {
case 'i':
run_interactively = true;
break;
case 'p':
port = atoi(argv[argn++]); j+= 4000;
run_interactively = true;
break;
case 's':
setup= strtoul(argv[argn++], NULL, 0); j+= 4000;
break;
default:
printf("Undefined option, -%c\n", argv[argn][j]);
break;
}
}
 
tb.i_setup = setup;
tb.i_uart = 1;
if (run_interactively) {
uart = new UARTSIM(port);
uart->setup(tb.i_setup);
 
while(1) {
 
tb.i_clk = 1;
tb.eval();
tb.i_clk = 0;
tb.eval();
 
tb.i_uart = (*uart)(tb.o_uart);
}
 
} else {
int childs_stdin[2], childs_stdout[2];
 
if ((pipe(childs_stdin)!=0)||(pipe(childs_stdout) != 0)) {
fprintf(stderr, "ERR setting up child pipes\n");
perror("O/S ERR");
printf("TEST FAILURE\n");
exit(EXIT_FAILURE);
}
 
pid_t pid = fork();
 
if (pid < 0) {
fprintf(stderr, "ERR setting up child process\n");
perror("O/S ERR");
printf("TEST FAILURE\n");
exit(EXIT_FAILURE);
}
 
if (pid) {
int nr=-2, nw;
 
// We are the parent
close(childs_stdin[ 0]); // Close the read end
close(childs_stdout[1]); // Close the write end
 
char string[] = "This is a UART testing string\r\n";
char test[256];
 
nw = write(childs_stdin[1], string, strlen(string));
if (nw == (int)strlen(string)) {
int rpos = 0;
test[0] = '\0';
while((rpos<nw)
&&(0<(nr=read(childs_stdout[0],
&test[rpos], strlen(string)-rpos))))
rpos += nr;
nr = rpos;
if (rpos > 0)
test[rpos] = '\0';
printf("Successfully read %d characters: %s\n", nr, test);
}
 
// We are done, kill our child if not already dead
kill(pid, SIGTERM);
 
if ((nr == nw)&&(nw == (int)strlen(string))
&&(strcmp(test, string) == 0))
printf("SUCCESS!\n");
else
printf("TEST FAILED\n");
} else {
close(childs_stdin[ 1]);
close(childs_stdout[0]);
close(STDIN_FILENO);
if (dup(childs_stdin[0]) < 0) {
fprintf(stderr, "ERR setting up child FD\n");
perror("O/S ERR");
exit(EXIT_FAILURE);
}
close(STDOUT_FILENO);
if (dup(childs_stdout[1]) < 0) {
fprintf(stderr, "ERR setting up child FD\n");
perror("O/S ERR");
exit(EXIT_FAILURE);
}
 
// UARTSIM(0) uses stdin and stdout for its FD's
uart = new UARTSIM(0);
uart->setup(tb.i_setup);
 
// Make sure we don't run longer than 4 seconds ...
time_t start = time(NULL);
int iterations_before_check = 2048;
bool done = false;
 
for(int i=0; i<200000; i++) {
// Clear any initial break condition
tb.i_clk = 1;
tb.eval();
tb.i_clk = 0;
tb.eval();
 
tb.i_uart = 1;
}
 
while(!done) {
tb.i_clk = 1;
tb.eval();
tb.i_clk = 0;
tb.eval();
 
tb.i_uart = (*uart)(tb.o_uart);
 
/*
fprintf(stderr, "%02x:%02x (%02x/%d) %d,%d->%02x [%d/%d/%08x]\n",
tb.v__DOT__head,
tb.v__DOT__tail,
tb.v__DOT__lineend,
tb.v__DOT__run_tx,
tb.v__DOT__tx_stb,
tb.v__DOT__transmitter__DOT__r_busy,
tb.v__DOT__tx_data & 0x0ff,
tb.v__DOT__transmitter__DOT__state,
tb.v__DOT__transmitter__DOT__zero_baud_counter,
tb.v__DOT__transmitter__DOT__baud_counter);
*/
 
if (iterations_before_check-- <= 0) {
iterations_before_check = 2048;
done = ((time(NULL)-start)>60);
if (done)
fprintf(stderr, "CHILD-TIMEOUT\n");
}
}
}
}
}
/trunk/bench/cpp/uartsim.h
0,0 → 1,132
////////////////////////////////////////////////////////////////////////////////
//
// Filename: uartsim.h
//
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To forward a Verilator simulated UART link over a TCP/IP pipe.
//
// This file provides the description of the interface between the UARTSIM
// and the rest of the world. See below for more detailed descriptions.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef UARTSIM_H
#define UARTSIM_H
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <poll.h>
#include <unistd.h>
#include <arpa/inet.h>
#include <signal.h>
 
#define TXIDLE 0
#define TXDATA 1
#define RXIDLE 0
#define RXDATA 1
 
class UARTSIM {
// The file descriptors:
// m_skt is the socket/port we are listening on
// m_conrd is the file descriptor to read from
// m_conwr is the file descriptor to write to
int m_skt, m_conrd, m_conwr;
//
// The m_setup register is the 29'bit control register used within
// the core.
unsigned m_setup;
// And the pieces of the setup register broken out.
int m_nparity, m_fixdp, m_evenp, m_nbits, m_nstop, m_baud_counts;
 
// UART state
int m_rx_baudcounter, m_rx_state, m_rx_busy,
m_rx_changectr, m_last_tx;
int m_tx_baudcounter, m_tx_state, m_tx_busy;
unsigned m_rx_data, m_tx_data;
 
// setup_listener is an attempt to encapsulate all of the network
// related setup stuff.
void setup_listener(const int port);
 
// nettick() gets called if we are connected to a network, and
int nettick(const int i_tx);
// fdtick() if we are not.
int fdtick(const int i_tx);
 
// We'll use the file descriptor for the listener socket to determine
// whether we are connected to the network or not. If not connected
// to the network, then we assume m_conrd and m_conwr refer to
// your more traditional file descriptors, and use them as such.
int tick(const int i_tx) {
if (m_skt >= 0)
return nettick(i_tx);
else
return fdtick(i_tx);
}
 
public:
//
// The UARTSIM constructor takes one argument: the port on the
// localhost to listen in on. Once started, connections may be made
// to this port to get the output from the port.
UARTSIM(const int port);
 
// kill() closes any active connection and the socket. Once killed,
// no further output will be sent to the port.
void kill(void);
 
// setup() busts out the bits from isetup to the various internal
// parameters. It is ideally only called between bits at appropriate
// transition intervals.
void setup(unsigned isetup);
 
// The operator() function is called on every tick. The input is the
// the output txuart transmit wire from the device. The output is to
// be connected to the the rxuart receive wire into the device. This
// makes hookup and operation very simple.
//
// This is the most appropriate simulation entry function if the
// setup register will never change.
//
int operator()(int i_tx) {
return tick(i_tx); }
 
// If there is a possibility that the core might change the UART setup,
// then it makes sense to include that current setup when calling the
// tick operator.
int operator()(int i_tx, unsigned isetup) {
setup(isetup); return tick(i_tx); }
};
 
#endif
/trunk/bench/cpp/Makefile
0,0 → 1,66
################################################################################
##
## Filename: Makefile
##
## Project: wbuart32, a full featured UART with simulator
##
## Purpose:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
CXX := g++
FLAGS := -Wall -Og -g
OBJDIR := obj-pc
RTLD := ../verilog
INCS := -I$(RTLD)/obj_dir/ -I/usr/share/verilator/include
SOURCES := linetest.cpp
VOBJDR := $(RTLD)/obj_dir
VLIB := /usr/share/verilator/include/verilated.cpp
SIMSRCS := linetest.cpp uartsim.cpp
SIMOBJ := $(subst .cpp,.o,$(SIMSRCS))
SIMOBJS:= $(addprefix $(OBJDIR)/,$(SIMOBJ))
all: $(OBJDIR)/ linetest
 
$(OBJDIR)/:
@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
 
$(OBJDIR)/uartsim.o: uartsim.cpp uartsim.h
 
$(OBJDIR)/%.o: %.cpp
$(CXX) $(FLAGS) $(INCS) -c $< -o $@
 
linetest: $(OBJDIR)/linetest.o $(OBJDIR)/uartsim.o $(VOBJDR)/Vlinetest__ALL.a
$(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@
 
.PHONY: clean
clean:
rm ./linetest
rm $(OBJDIR)/
 
/trunk/bench/verilog/linetest.v
0,0 → 1,116
////////////////////////////////////////////////////////////////////////////////
//
// Filename: linetest.v
//
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To test that the txuart and rxuart modules work properly, by
// buffering one line's worth of input, and then piping that line
// to the transmitter while (possibly) receiving a new line.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module linetest(i_clk, i_setup, i_uart, o_uart);
input i_clk;
input [29:0] i_setup;
input i_uart;
output wire o_uart;
 
reg [7:0] buffer [0:255];
reg [7:0] head, tail;
 
reg pwr_reset;
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset = 1'b0;
 
wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
wire [7:0] rx_data;
 
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart, rx_stb, rx_data,
rx_break, rx_perr, rx_ferr, rx_ignored);
 
 
wire [7:0] nxt_head;
assign nxt_head = head + 8'h01;
always @(posedge i_clk)
buffer[head] <= rx_data;
initial head= 8'h00;
always @(posedge i_clk)
if (pwr_reset)
head <= 8'h00;
else if ((rx_stb)&&(!rx_break)&&(!rx_perr)&&(!rx_ferr)&&(nxt_head != tail))
head <= nxt_head;
 
wire [7:0] nused;
reg [7:0] lineend;
reg run_tx;
 
assign nused = head-tail;
 
initial run_tx = 0;
initial lineend = 0;
always @(posedge i_clk)
if (pwr_reset)
begin
run_tx <= 1'b0;
lineend <= 8'h00;
end else if ((rx_data == 8'h0a)&&(rx_stb))
begin
lineend <= head+8'h1;
run_tx <= 1'b1;
end else if ((!run_tx)&&(nused>8'd80)&&(head != tail))
begin
lineend <= head;
run_tx <= 1'b1;
end else if (tail == lineend)
run_tx <= 1'b0;
 
wire tx_break, tx_busy;
assign tx_break = 1'b0;
reg [7:0] tx_data;
reg tx_stb;
 
always @(posedge i_clk)
tx_data <= buffer[tail];
initial tx_stb = 1'b0;
always @(posedge i_clk)
tx_stb <= run_tx;
initial tail = 8'h00;
always @(posedge i_clk)
if(pwr_reset)
tail <= 8'h00;
else if ((tx_stb)&&(!tx_busy))
tail <= tail + 8'h01;
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, o_uart, tx_busy);
 
endmodule
/trunk/bench/verilog/Makefile
0,0 → 1,69
################################################################################
##
## Filename: Makefile
##
## Project: wbuart32, a full featured UART with simulator
##
## Purpose: To direct the Verilator build of the Verilog portion of the
## bench test. The result is C++ code (built by Verilator), that
## is then built (herein) into a library.
##
## Targets: The default target, all, builds the target test, which includes
## the linetest Verilator library necessary for testing.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
##
all: test
YYMMDD=`date +%Y%m%d`
CXX := g++
FBDIR := .
VDIRFB:= $(FBDIR)/obj_dir
RTLDR := ../../rtl
 
.PHONY: test
test: $(VDIRFB)/Vlinetest__ALL.a
 
$(VDIRFB)/Vlinetest__ALL.a: $(VDIRFB)/Vlinetest.h $(VDIRFB)/Vlinetest.cpp
$(VDIRFB)/Vlinetest__ALL.a: $(VDIRFB)/Vlinetest.mk
$(VDIRFB)/Vlinetest.h $(VDIRFB)/Vlinetest.cpp $(VDIRFB)/Vlinetest.mk: linetest.v
$(VDIRFB)/Vlinetest.h $(VDIRFB)/Vlinetest.cpp $(VDIRFB)/Vlinetest.mk: $(RTLDR)/rxuart.v $(RTLDR)/txuart.v
 
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -cc -y ../../rtl $*.v
 
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
 
.PHONY: clean
clean:
rm -rf $(VDIRFB)/*.mk
rm -rf $(VDIRFB)/*.cpp
rm -rf $(VDIRFB)/*.h
rm -rf $(VDIRFB)/
 
/trunk/rtl/rxuart.v
0,0 → 1,330
////////////////////////////////////////////////////////////////////////////////
//
// Filename: rxuart.v
//
// Project: FPGA library
//
// Purpose: Receive and decode inputs from a single UART line.
//
//
// To interface with this module, connect it to your system clock,
// pass it the 32 bit setup register (defined below) and the UART
// input. When data becomes available, the o_wr line will be asserted
// for one clock cycle. On parity or frame errors, the o_parity_err
// or o_frame_err lines will be asserted. Likewise, on a break
// condition, o_break will be asserted. These lines are self clearing.
//
// There is a synchronous reset line, logic high.
//
// Now for the setup register. The register is 32 bits, so that this
// UART may be set up over a 32-bit bus.
//
// i_setup[29:28] Indicates the number of data bits per word. This will
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
// for a six bit word, or 2'b11 for a five bit word.
//
// i_setup[27] Indicates whether or not to use one or two stop bits.
// Set this to one to expect two stop bits, zero for one.
//
// i_setup[26] Indicates whether or not a parity bit exists. Set this
// to 1'b1 to include parity.
//
// i_setup[25] Indicates whether or not the parity bit is fixed. Set
// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
// parity to be set based upon data. (Both assume the parity
// enable value is set.)
//
// i_setup[24] This bit is ignored if parity is not used. Otherwise,
// in the case of a fixed parity bit, this bit indicates whether
// mark (1'b1) or space (1'b0) parity is used. Likewise if the
// parity is not fixed, a 1'b1 selects even parity, and 1'b0
// selects odd.
//
// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
// So, for example, if you have a 200 MHz clock and wish to
// run your UART at 9600 baud, you would take 200 MHz and divide
// by 9600 to set this value to 24'd20834. Likewise if you wished
// to run this serial port at 115200 baud from a 200 MHz clock,
// you would set the value to 24'd1736
//
// Thus, to set the UART for the common setting of an 8-bit word,
// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
// would want to set the setup value to:
//
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
// 32'h005161 // For 9600 baud, 8 bit, no parity
//
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
// States: (@ baud counter == 0)
// 0 First bit arrives
// ..7 Bits arrive
// 8 Stop bit (x1)
// 9 Stop bit (x2)
/// c break condition
// d Waiting for the channel to go high
// e Waiting for the reset to complete
// f Idle state
`define RXU_BIT_ZERO 4'h0
`define RXU_BIT_ONE 4'h1
`define RXU_BIT_TWO 4'h2
`define RXU_BIT_THREE 4'h3
`define RXU_BIT_FOUR 4'h4
`define RXU_BIT_FIVE 4'h5
`define RXU_BIT_SIX 4'h6
`define RXU_BIT_SEVEN 4'h7
`define RXU_PARITY 4'h8
`define RXU_STOP 4'h9
`define RXU_SECOND_STOP 4'ha
// Unused 4'hb
// Unused 4'hc
`define RXU_BREAK 4'hd
`define RXU_RESET_IDLE 4'he
`define RXU_IDLE 4'hf
 
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
o_parity_err, o_frame_err, o_ck_uart);
// parameter // CLOCKS_PER_BAUD = 25'd004340,
// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
// 8 data bits, no parity, (at least 1) stop bit
input i_clk, i_reset;
input [29:0] i_setup;
input i_uart;
output reg o_wr;
output reg [7:0] o_data;
output reg o_break;
output reg o_parity_err, o_frame_err;
output wire o_ck_uart;
 
 
wire [27:0] clocks_per_baud, break_condition, half_baud;
wire [1:0] data_bits;
wire use_parity, parity_even, dblstop, fixd_parity;
reg [29:0] r_setup;
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
assign data_bits = r_setup[29:28];
assign dblstop = r_setup[27];
assign use_parity = r_setup[26];
assign fixd_parity = r_setup[25];
assign parity_even = r_setup[24];
assign break_condition = { r_setup[23:0], 4'h0 };
assign half_baud = { 5'h00, r_setup[23:1] };
 
reg q_uart, qq_uart, ck_uart;
initial q_uart = 1'b0;
initial qq_uart = 1'b0;
initial ck_uart = 1'b0;
always @(posedge i_clk)
begin
q_uart <= i_uart;
qq_uart <= q_uart;
ck_uart <= qq_uart;
end
assign o_ck_uart = ck_uart;
 
reg [27:0] chg_counter;
initial chg_counter = 28'h00;
always @(posedge i_clk)
if (i_reset)
chg_counter <= 28'h00;
else if (qq_uart != ck_uart)
chg_counter <= 28'h00;
else if (chg_counter < break_condition)
chg_counter <= chg_counter + 1;
 
reg line_synch;
initial line_synch = 1'b0;
initial o_break = 1'b0;
always @(posedge i_clk)
o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
always @(posedge i_clk)
line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
 
reg [3:0] state;
reg [27:0] baud_counter;
reg [7:0] data_reg;
reg calc_parity, zero_baud_counter, half_baud_time;
initial o_wr = 1'b0;
initial state = `RXU_RESET_IDLE;
initial o_parity_err = 1'b0;
initial o_frame_err = 1'b0;
// initial baud_counter = clocks_per_baud;
always @(posedge i_clk)
begin
if (i_reset)
begin
o_wr <= 1'b0;
o_data <= 8'h00;
state <= `RXU_RESET_IDLE;
baud_counter <= clocks_per_baud-28'h01;// Set, not reset
data_reg <= 8'h00;
calc_parity <= 1'b0;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
end else if (state == `RXU_RESET_IDLE)
begin
r_setup <= i_setup;
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
baud_counter <= clocks_per_baud-28'h01;// Set, not reset
if (line_synch)
// Goto idle state from a reset
state <= `RXU_IDLE;
else // Otherwise, stay in this condition 'til reset
state <= `RXU_RESET_IDLE;
calc_parity <= 1'b0;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
end else if (o_break)
begin // We are in a break condition
state <= `RXU_BREAK;
o_wr <= 1'b0;
o_data <= 8'h00;
baud_counter <= clocks_per_baud-28'h01;// Set, not reset
data_reg <= 8'h00;
calc_parity <= 1'b0;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
r_setup <= i_setup;
end else if (state == `RXU_BREAK)
begin // Goto idle state following return ck_uart going high
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
baud_counter <= clocks_per_baud - 28'h01;
if (ck_uart)
state <= `RXU_IDLE;
else
state <= `RXU_BREAK;
calc_parity <= 1'b0;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
r_setup <= i_setup;
end else if (state == `RXU_IDLE)
begin // Idle state, independent of baud counter
r_setup <= i_setup;
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
baud_counter <= clocks_per_baud - 28'h01;
if ((~ck_uart)&&(half_baud_time))
begin
// We are in the center of a valid start bit
case (data_bits)
2'b00: state <= `RXU_BIT_ZERO;
2'b01: state <= `RXU_BIT_ONE;
2'b10: state <= `RXU_BIT_TWO;
2'b11: state <= `RXU_BIT_THREE;
endcase
end else // Otherwise, just stay here in idle
state <= `RXU_IDLE;
calc_parity <= 1'b0;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
end else if (zero_baud_counter)
begin
baud_counter <= clocks_per_baud-28'h1;
if (state < `RXU_BIT_SEVEN)
begin
// Data arrives least significant bit first.
// By the time this is clocked in, it's what
// you'll have.
data_reg <= { ck_uart, data_reg[7:1] };
calc_parity <= calc_parity ^ ck_uart;
o_data <= 8'h00;
o_wr <= 1'b0;
state <= state + 1;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
end else if (state == `RXU_BIT_SEVEN)
begin
data_reg <= { ck_uart, data_reg[7:1] };
calc_parity <= calc_parity ^ ck_uart;
o_data <= 8'h00;
o_wr <= 1'b0;
state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
end else if (state == `RXU_PARITY)
begin
if (fixd_parity)
o_parity_err <= (ck_uart ^ parity_even);
else
o_parity_err <= ((parity_even && (calc_parity != ck_uart))
||((~parity_even)&&(calc_parity==ck_uart)));
state <= `RXU_STOP;
o_frame_err <= 1'b0;
end else if (state == `RXU_STOP)
begin // Stop (or parity) bit(s)
case (data_bits)
2'b00: o_data <= data_reg;
2'b01: o_data <= { 1'b0, data_reg[7:1] };
2'b10: o_data <= { 2'b0, data_reg[7:2] };
2'b11: o_data <= { 3'b0, data_reg[7:3] };
endcase
o_wr <= 1'b1; // Pulse the write
o_frame_err <= (~ck_uart);
if (~ck_uart)
state <= `RXU_RESET_IDLE;
else if (dblstop)
state <= `RXU_SECOND_STOP;
else
state <= `RXU_IDLE;
// o_parity_err <= 1'b0;
end else // state must equal RX_SECOND_STOP
begin
if (~ck_uart)
begin
o_frame_err <= 1'b1;
state <= `RXU_RESET_IDLE;
end else begin
state <= `RXU_IDLE;
o_frame_err <= 1'b0;
end
o_parity_err <= 1'b0;
end
end else begin
o_wr <= 1'b0; // data_reg = data_reg
baud_counter <= baud_counter - 28'd1;
o_parity_err <= 1'b0;
o_frame_err <= 1'b0;
end
end
 
initial zero_baud_counter = 1'b0;
always @(posedge i_clk)
zero_baud_counter <= (baud_counter == 28'h01);
 
initial half_baud_time = 0;
always @(posedge i_clk)
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
 
 
endmodule
 
 
/trunk/rtl/wbuart-insert.v
0,0 → 1,131
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbuart-insert.v
//
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: This is not a module file. It is an example of the types of
// lines and connections which can be used to connect this UART
// to a local wishbone bus. It was drawn from a working file, and
// modified here for show, so ... let me know if I messed anything up
// along the way.
//
// Why isn't this a full module file? Because I tend to lump all of my
// single cycle I/O peripherals into one module file. It makes the logic
// simpler. This particular file was extracted from the fastio.v file
// within the openarty project.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
 
 
// Ideally, UART_SETUP is defined somewhere. I commonly like to define
// it to CLKRATE / BAUDRATE, to give me 8N1 performance. 4MB is useful
// to me, so 100MHz / 4M = 25 could be the setup. You can also use
// 200MHz / 4MB = 50 ... it all depends upon your clock.
`define UART_SETUP 30'd25
reg [29:0] uart_setup;
initial uart_setup = `UART_SETUP;
always @(posedge i_clk)
if ((i_wb_stb)&&(i_wb_addr == `UART_SETUP_ADDR))
uart_setup[29:0] <= i_wb_data[29:0];
 
//
// First the UART receiver
//
wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
wire [7:0] rx_data_port;
rxuart rx(i_clk, 1'b0, uart_setup, i_rx,
rx_stb, rx_data_port, rx_break,
rx_perr, rx_ferr, ck_uart);
 
wire [31:0] rx_data;
reg [11:0] r_rx_data;
always @(posedge i_clk)
if (rx_stb)
begin
r_rx_data[11] <= rx_break;
r_rx_data[10] <= rx_ferr;
r_rx_data[ 9] <= rx_perr;
r_rx_data[7:0]<= rx_data_port;
end
always @(posedge i_clk)
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
||(rx_stb))
r_rx_data[8] <= !rx_stb;
assign o_cts = rx_stb;
assign rx_data = { 20'h00, r_rx_data };
assign rx_int = r_rx_data[8];
 
//
// Then the UART transmitter
//
wire tx_busy;
reg [7:0] r_tx_data;
reg r_tx_stb, r_tx_break;
wire [31:0] tx_data;
txuart tx(i_clk, 1'b0, uart_setup,
r_tx_break, r_tx_stb, r_tx_data,
o_tx, tx_busy);
always @(posedge i_clk)
if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
begin
r_tx_stb <= (!r_tx_break)&&(!i_wb_data[8]);
r_tx_data <= i_wb_data[7:0];
r_tx_break<= i_wb_data[9];
end else if (~tx_busy)
begin
r_tx_stb <= 1'b0;
r_tx_data <= 8'h0;
end
assign tx_data = { 20'h00,
ck_uart, o_tx, r_tx_break, tx_busy,
r_tx_data };
assign tx_int = ~tx_busy;
 
always @(posedge i_clk)
case(i_wb_addr)
`UART_SETUP_ADDR: o_wb_data <= { 2'b00, uart_setup };
`UART_RX_ADDR : o_wb_data <= rx_data;
`UART_TX_ADDR : o_wb_data <= tx_data;
//
// The rest of these address slots are left open here for
// whatever else you might wish to connect to this bus/STB
// line
default: o_wb_data <= 32'h00;
endcase
 
assign o_wb_stall = 1'b0;
always @(posedge i_clk)
o_wb_ack <= (i_wb_stb);
 
// Interrupts sent to the board from here
assign o_board_ints = { rx_int, tx_int /* any other from this module */};
 
/trunk/rtl/txuart.v
0,0 → 1,251
////////////////////////////////////////////////////////////////////////////////
//
// Filename: txuart.v
//
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: Transmit outputs over a single UART line.
//
// To interface with this module, connect it to your system clock,
// pass it the 32 bit setup register (defined below) and the byte
// of data you wish to transmit. Strobe the i_wr line high for one
// clock cycle, and your data will be off. Wait until the 'o_busy'
// line is low before strobing the i_wr line again--this implementation
// has NO BUFFER, so strobing i_wr while the core is busy will just
// cause your data to be lost. The output will be placed on the o_txuart
// output line. If you wish to set/send a break condition, assert the
// i_break line otherwise leave it low.
//
// There is a synchronous reset line, logic high.
//
// Now for the setup register. The register is 32 bits, so that this
// UART may be set up over a 32-bit bus.
//
// i_setup[29:28] Indicates the number of data bits per word. This will
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
// for a six bit word, or 2'b11 for a five bit word.
//
// i_setup[27] Indicates whether or not to use one or two stop bits.
// Set this to one to expect two stop bits, zero for one.
//
// i_setup[26] Indicates whether or not a parity bit exists. Set this
// to 1'b1 to include parity.
//
// i_setup[25] Indicates whether or not the parity bit is fixed. Set
// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
// parity to be set based upon data. (Both assume the parity
// enable value is set.)
//
// i_setup[24] This bit is ignored if parity is not used. Otherwise,
// in the case of a fixed parity bit, this bit indicates whether
// mark (1'b1) or space (1'b0) parity is used. Likewise if the
// parity is not fixed, a 1'b1 selects even parity, and 1'b0
// selects odd.
//
// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
// So, for example, if you have a 200 MHz clock and wish to
// run your UART at 9600 baud, you would take 200 MHz and divide
// by 9600 to set this value to 24'd20834. Likewise if you wished
// to run this serial port at 115200 baud from a 200 MHz clock,
// you would set the value to 24'd1736
//
// Thus, to set the UART for the common setting of an 8-bit word,
// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
// would want to set the setup value to:
//
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
// 32'h005161 // For 9600 baud, 8 bit, no parity
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`define TXU_BIT_ZERO 4'h0
`define TXU_BIT_ONE 4'h1
`define TXU_BIT_TWO 4'h2
`define TXU_BIT_THREE 4'h3
`define TXU_BIT_FOUR 4'h4
`define TXU_BIT_FIVE 4'h5
`define TXU_BIT_SIX 4'h6
`define TXU_BIT_SEVEN 4'h7
`define TXU_PARITY 4'h8 // Constant 1
`define TXU_STOP 4'h9 // Constant 1
`define TXU_SECOND_STOP 4'ha
// 4'hb // Unused
// 4'hc // Unused
// `define TXU_START 4'hd // An unused state
`define TXU_BREAK 4'he
`define TXU_IDLE 4'hf
//
//
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
input i_clk, i_reset;
input [29:0] i_setup;
input i_break;
input i_wr;
input [7:0] i_data;
output reg o_uart;
output wire o_busy;
 
wire [27:0] clocks_per_baud, break_condition;
wire [1:0] data_bits;
wire use_parity, parity_even, dblstop, fixd_parity;
reg [29:0] r_setup;
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
assign break_condition = { r_setup[23:0], 4'h0 };
assign data_bits = r_setup[29:28];
assign dblstop = r_setup[27];
assign use_parity = r_setup[26];
assign fixd_parity = r_setup[25];
assign parity_even = r_setup[24];
 
reg [27:0] baud_counter;
reg [3:0] state;
reg [7:0] lcl_data;
reg calc_parity, r_busy, zero_baud_counter;
 
initial o_uart = 1'b1;
initial r_busy = 1'b1;
initial state = `TXU_IDLE;
initial lcl_data= 8'h0;
initial calc_parity = 1'b0;
// initial baud_counter = clocks_per_baud;//ILLEGAL--not constant
always @(posedge i_clk)
begin
if (i_reset)
begin
o_uart <= 1'b1;
r_busy <= 1'b1;
state <= `TXU_IDLE;
lcl_data <= 8'h0;
calc_parity <= 1'b0;
end else if (i_break)
begin
o_uart <= 1'b0;
state <= `TXU_BREAK;
calc_parity <= 1'b0;
r_busy <= 1'b1;
end else if (~zero_baud_counter)
begin // r_busy needs to be set coming into here
r_busy <= 1'b1;
end else if (state == `TXU_BREAK)
begin
state <= `TXU_IDLE;
r_busy <= 1'b1;
o_uart <= 1'b1;
calc_parity <= 1'b0;
end else if (state == `TXU_IDLE) // STATE_IDLE
begin
// baud_counter <= 0;
r_setup <= i_setup;
calc_parity <= 1'b0;
if ((i_wr)&&(~r_busy))
begin // Immediately start us off with a start bit
o_uart <= 1'b0;
r_busy <= 1'b1;
case(data_bits)
2'b00: state <= `TXU_BIT_ZERO;
2'b01: state <= `TXU_BIT_ONE;
2'b10: state <= `TXU_BIT_TWO;
2'b11: state <= `TXU_BIT_THREE;
endcase
lcl_data <= i_data;
// baud_counter <= clocks_per_baud-28'h01;
end else begin // Stay in idle
o_uart <= 1'b1;
r_busy <= 0;
// lcl_data is irrelevant
// state <= state;
end
end else begin
// One clock tick in each of these states ...
// baud_counter <= clocks_per_baud - 28'h01;
r_busy <= 1'b1;
if (state[3] == 0) // First 8 bits
begin
o_uart <= lcl_data[0];
calc_parity <= calc_parity ^ lcl_data[0];
if (state == `TXU_BIT_SEVEN)
state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
else
state <= state + 1;
lcl_data <= { 1'b0, lcl_data[7:1] };
end else if (state == `TXU_PARITY)
begin
state <= `TXU_STOP;
if (fixd_parity)
o_uart <= parity_even;
else
o_uart <= calc_parity^((parity_even)? 1'b1:1'b0);
end else if (state == `TXU_STOP)
begin // two stop bit(s)
o_uart <= 1'b1;
if (dblstop)
state <= `TXU_SECOND_STOP;
else
state <= `TXU_IDLE;
calc_parity <= 1'b0;
end else // `TXU_SECOND_STOP and default:
begin
state <= `TXU_IDLE; // Go back to idle
o_uart <= 1'b1;
// Still r_busy, since we need to wait
// for the baud clock to finish counting
// out this last bit.
end
end
end
 
assign o_busy = (r_busy);
 
 
initial zero_baud_counter = 1'b0;
initial baud_counter = 28'h05;
always @(posedge i_clk)
begin
zero_baud_counter <= (baud_counter == 28'h01);
if ((i_reset)||(i_break))
// Give ourselves 16 bauds before being ready
baud_counter <= break_condition;
else if (~zero_baud_counter)
baud_counter <= baud_counter - 28'h01;
else if (state == `TXU_BREAK)
// Give us two stop bits before becoming available
baud_counter <= clocks_per_baud<<2;
else if (state == `TXU_IDLE)
begin
if((i_wr)&&(~r_busy))
baud_counter <= clocks_per_baud - 28'h01;
else
zero_baud_counter <= 1'b1;
end else
baud_counter <= clocks_per_baud - 28'h01;
end
endmodule
 
/trunk/rtl/Makefile
0,0 → 1,72
################################################################################
##
## Filename: Makefile
##
## Project: wbuart32, a full featured UART with simulator
##
## Purpose: To direct the Verilator build of the SoC sources. The result
## is C++ code (built by Verilator), that is then built (herein)
## into a library.
##
## Targets: The default target, all, builds the target test, which includes
## the libraries necessary for Verilator testing.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
##
all: test
YYMMDD=`date +%Y%m%d`
CXX := g++
FBDIR := .
VDIRFB:= $(FBDIR)/obj_dir
 
.PHONY: test
test: $(VDIRFB)/Vtxuart__ALL.a
test: $(VDIRFB)/Vrxuart__ALL.a
 
$(VDIRFB)/Vrxuart__ALL.a: $(VDIRFB)/Vrxuart.h $(VDIRFB)/Vrxuart.cpp
$(VDIRFB)/Vrxuart__ALL.a: $(VDIRFB)/Vrxuart.mk
$(VDIRFB)/Vrxuart.h $(VDIRFB)/Vrxuart.cpp $(VDIRFB)/Vrxuart.mk: rxuart.v
 
$(VDIRFB)/Vtxuart__ALL.a: $(VDIRFB)/Vtxuart.h $(VDIRFB)/Vtxuart.cpp
$(VDIRFB)/Vtxuart__ALL.a: $(VDIRFB)/Vtxuart.mk
$(VDIRFB)/Vtxuart.h $(VDIRFB)/Vtxuart.cpp $(VDIRFB)/Vtxuart.mk: txuart.v
 
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -cc $*.v
 
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
 
.PHONY: clean
clean:
rm -rf $(VDIRFB)/*.mk
rm -rf $(VDIRFB)/*.cpp
rm -rf $(VDIRFB)/*.h
rm -rf $(VDIRFB)/
 
/trunk/doc/spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/spec.pdf
trunk/doc/spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/gpl-3.0.tex =================================================================== --- trunk/doc/src/gpl-3.0.tex (nonexistent) +++ trunk/doc/src/gpl-3.0.tex (revision 2) @@ -0,0 +1,719 @@ +\documentclass[11pt]{article} + +\title{GNU GENERAL PUBLIC LICENSE} +\date{Version 3, 29 June 2007} + +\begin{document} +\maketitle + +\begin{center} +{\parindent 0in + +Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/} + +\bigskip +Everyone is permitted to copy and distribute verbatim copies of this + +license document, but changing it is not allowed.} + +\end{center} + +\renewcommand{\abstractname}{Preamble} +\begin{abstract} +The GNU General Public License is a free, copyleft license for +software and other kinds of works. + +The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + +When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + +To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. 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If you cannot convey a +covered work so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you may +not convey it at all. For example, if you agree to terms that obligate you +to collect a royalty for further conveying from those to whom you convey +the Program, the only way you could satisfy both those terms and this +License would be to refrain entirely from conveying the Program. + +\item Use with the GNU Affero General Public License. + +Notwithstanding any other provision of this License, you have +permission to link or combine any covered work with a work licensed +under version 3 of the GNU Affero General Public License into a single +combined work, and to convey the resulting work. The terms of this +License will continue to apply to the part which is the covered work, +but the special requirements of the GNU Affero General Public License, +section 13, concerning interaction through a network will apply to the +combination as such. + +\item Revised Versions of this License. + +The Free Software Foundation may publish revised and/or new versions of +the GNU General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the +Program specifies that a certain numbered version of the GNU General +Public License ``or any later version'' applies to it, you have the +option of following the terms and conditions either of that numbered +version or of any later version published by the Free Software +Foundation. If the Program does not specify a version number of the +GNU General Public License, you may choose any version ever published +by the Free Software Foundation. + +If the Program specifies that a proxy can decide which future +versions of the GNU General Public License can be used, that proxy's +public statement of acceptance of a version permanently authorizes you +to choose that version for the Program. + +Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. + +\item Disclaimer of Warranty. + +\begin{sloppypar} + THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS'' + WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. + SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL + NECESSARY SERVICING, REPAIR OR CORRECTION. +\end{sloppypar} + +\item Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN + WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES + AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR + DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM + (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED + INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE + OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH + HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + DAMAGES. + +\item Interpretation of Sections 15 and 16. + +If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + +\begin{center} +{\Large\sc End of Terms and Conditions} + +\bigskip +How to Apply These Terms to Your New Programs +\end{center} + +If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the ``copyright'' line and a pointer to where the full notice is found. + +{\footnotesize +\begin{verbatim} + + +Copyright (C) + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +\end{verbatim} +} + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + +{\footnotesize +\begin{verbatim} + Copyright (C) + +This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. +This is free software, and you are welcome to redistribute it +under certain conditions; type `show c' for details. +\end{verbatim} +} + +The hypothetical commands {\tt show w} and {\tt show c} should show +the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an ``about box''. + +You should also get your employer (if you work as a programmer) or +school, if any, to sign a ``copyright disclaimer'' for the program, if +necessary. For more information on this, and how to apply and follow +the GNU GPL, see \texttt{http://www.gnu.org/licenses/}. + +The GNU General Public License does not permit incorporating your +program into proprietary programs. If your program is a subroutine +library, you may consider it more useful to permit linking proprietary +applications with the library. If this is what you want to do, use +the GNU Lesser General Public License instead of this License. But +first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}. + +\end{enumerate} + +\end{document} Index: trunk/doc/src/GT.eps =================================================================== --- trunk/doc/src/GT.eps (nonexistent) +++ trunk/doc/src/GT.eps (revision 2) @@ -0,0 +1,94 @@ +%!PS-Adobe-3.0 EPSF-3.0 +%%BoundingBox: 0 0 504 288 +%%Creator: Gisselquist Technology LLC +%%Title: Gisselquist Technology Logo +%%CreationDate: 11 Mar 2014 +%%EndComments +%%BeginProlog +/black { 0 setgray } def +/white { 1 setgray } def +/height { 288 } def +/lw { height 8 div } def +%%EndProlog +% %%Page: 1 + +false { % A bounding box + 0 setlinewidth + newpath + 0 0 moveto + 0 height lineto + 1.625 height mul lw add 0 rlineto + 0 height neg rlineto + closepath stroke +} if + +true { % The "G" + newpath + height 2 div 1.25 mul height moveto + height 2 div height 4 div sub height lineto + 0 height 3 4 div mul lineto + 0 height 4 div lineto + height 4 div 0 lineto + height 3 4 div mul 0 lineto + height height 4 div lineto + height height 2 div lineto + % + height lw sub height 2 div lineto + height lw sub height 4 div lw 2 div add lineto + height 3 4 div mul lw 2 div sub lw lineto + height 4 div lw 2 div add lw lineto + lw height 4 div lw 2 div add lineto + lw height 3 4 div mul lw 2 div sub lineto + height 4 div lw 2 div add height lw sub lineto + height 2 div 1.25 mul height lw sub lineto + closepath fill + newpath + height 2 div height 2 div moveto + height 2 div 0 rlineto + 0 height 2 div neg rlineto + lw neg 0 rlineto + 0 height 2 div lw sub rlineto + height 2 div height 2 div lw sub lineto + closepath fill +} if + +height 2 div 1.25 mul lw add 0 translate +false { + newpath + 0 height moveto + height 0 rlineto + 0 lw neg rlineto + height lw sub 2 div neg 0 rlineto + 0 height lw sub neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + 0 lw rlineto + closepath fill +} if + +true { % The "T" of "GT". + newpath + 0 height moveto + height lw add 2 div 0 rlineto + 0 height neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + closepath fill + + % The right half of the top of the "T" + newpath + % (height + lw)/2 + lw + height lw add 2 div lw add height moveto + % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw + height 3 lw mul sub 2 div 0 rlineto + 0 lw neg rlineto + height 3 lw mul sub 2 div neg 0 rlineto + closepath fill +} if + + +grestore +showpage +%%EOF Index: trunk/doc/src/gqtekspec.cls =================================================================== --- trunk/doc/src/gqtekspec.cls (nonexistent) +++ trunk/doc/src/gqtekspec.cls (revision 2) @@ -0,0 +1,298 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/ +% +% Copyright (C) 2015, Gisselquist Technology, LLC +% +% This template is free software: you can redistribute it and/or modify it +% under the terms of the GNU General Public License as published by the +% Free Software Foundation, either version 3 of the License, or (at your +% option) any later version. +% +% This template is distributed in the hope that it will be useful, but WITHOUT +% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +% for more details. +% +% You should have received a copy of the GNU General Public License along +% with this program. If not, see for a copy. +% +% License: GPL, v3, as defined and found on www.gnu.org, +% http://www.gnu.org/licenses/gpl.html +% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% \NeedsTeXFormat{LaTeX2e}[1995/12/01] +\ProvidesClass{gqtekspec}[2015/03/03 v0.1 -- Gisselquist Technology Specification] +\typeout{by Dan Gisselquist} +\LoadClassWithOptions{report} +\usepackage{datetime} +\usepackage{graphicx} +\usepackage[dvips]{pstricks} +\usepackage{hhline} +\usepackage{colortbl} +\definecolor{webgreen}{rgb}{0,0.5,0} +\usepackage[dvips,colorlinks=true,linkcolor=webgreen]{hyperref} +\newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}} +\setlength{\hoffset}{0.25in} +\setlength{\voffset}{-0.5in} +\setlength{\marginparwidth}{0in} +\setlength{\marginparsep}{0in} +\setlength{\textwidth}{6in} +\setlength{\oddsidemargin}{0in} + +% ************************************** +% * APPENDIX * +% ************************************** +% +\newcommand\appfl@g{\appendixname} %used to test \@chapapp +% +% \renewcommand\appendix{\par\clearpage + % \setcounter{chapter}{0}% + % \setcounter{section}{0}% + % \renewcommand\@chapapp{\appendixname}% + % \renewcommand\thechapter{\Alph{chapter}} + % \if@nosectnum\else + % \renewcommand\thesection{\Alph{chapter}.\arabic{section}} + % \fi +% } + + +% FIGURE +% redefine the @caption command to put a period after the figure or +% table number in the lof and lot tables +\long\def\@caption#1[#2]#3{\par\addcontentsline{\csname + ext@#1\endcsname}{#1}{\protect\numberline{\csname + the#1\endcsname.}{\ignorespaces #2}}\begingroup + \@parboxrestore + \normalsize + \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par + \endgroup} + +% **************************************** +% * TABLE OF CONTENTS, ETC. * +% **************************************** + +\renewcommand\contentsname{Contents} +\renewcommand\listfigurename{Figures} +\renewcommand\listtablename{Tables} + +\newif\if@toc \@tocfalse +\renewcommand\tableofcontents{% + \begingroup% temporarily set if@toc so that \@schapter will not + % put Table of Contents in the table of contents. + \@toctrue + \chapter*{\contentsname} + \endgroup + \thispagestyle{gqtekspecplain} + + \baselineskip=10pt plus .5pt minus .5pt + + {\raggedleft Page \par\vskip-\parskip} + \@starttoc{toc}% + \baselineskip=\normalbaselineskip + } + +\def\l@appendix{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{8em}} + +\def\l@chapter{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{4em}} + +% \if@nosectnum\else + % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}} + % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}} + % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}} + % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}} + % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}} +% \fi + +% LIST OF FIGURES +% +\def\listoffigures{% + \begingroup + \chapter*{\listfigurename}% + \endgroup + \thispagestyle{gqtekspecplain}% + + \baselineskip=10pt plus .5pt minus .5pt% + + {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}% + + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lof}% + \baselineskip=\normalbaselineskip}% + +\def\l@figure{\@dottedtocline{1}{1em}{4.0em}} + +% LIST OF TABLES +% +\def\listoftables{% + \begingroup + \chapter*{\listtablename}% + \endgroup + \thispagestyle{gqtekspecplain}% + \baselineskip=10pt plus .5pt minus .5pt% + {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}% + + % Added line underneath headings, 20 Jun 01, Capt Todd Hale. + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lot}% + \baselineskip=\normalbaselineskip}% + +\let\l@table\l@figure + +% **************************************** +% * PAGE STYLES * +% **************************************** +% +\def\ps@gqtekspectoc{% + \let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo + \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}} + \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +% \def\author#1{\def\auth@r{#1}} +% \def\title#1{\def\ti@tle{#1}} + +\def\logo{\begin{pspicture}(0,0)(5.67in,0.75in) + \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}} + \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}} + \end{pspicture}} +% TITLEPAGE +% +\def\titlepage{\setcounter{page}{1} + \typeout{^^JTitle Page.} + \thispagestyle{empty} + \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill} + \vskip 2\baselineskip + \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus + \vskip 2\baselineskip + \vspace*{10pt}\vfil + \begin{minipage}{\textwidth}\raggedleft + \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi + \vspace*{15pt} + {\Huge\bfseries\MakeUppercase\@title} \\ + \vskip 10\baselineskip + \Large \@author \\ + \ifemail{\Large \@email}\\\fi + \vskip 6\baselineskip + \Large \usdate\@date \\ + \end{minipage} + % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle + \vspace*{30pt} + \vfil + \newpage\baselineskip=\normalbaselineskip} + +\newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}% + {\vfill\newpage} +% **************************************** +% * CHAPTER DEFINITIONS * +% **************************************** +% +\renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi + \thispagestyle{gqtekspecplain}% + \global\@topnum\z@ + \@afterindentfalse + \secdef\@chapter\@schapter} +\renewcommand\@makechapterhead[1]{% + \hbox to \textwidth{\hfil{\Huge\bfseries \thechapter.}}\vskip 10\p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@ + \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +\renewcommand\@makeschapterhead[1]{% + \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +% **************************************** +% * INITIALIZATION * +% **************************************** +% +% Default initializations + +\ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos. +\onecolumn % Single-column. +\pagenumbering{roman} % the first chapter will change pagenumbering + % to arabic +\setcounter{page}{1} % in case a titlepage is not requested + % otherwise titlepage sets page to 1 since the + % flyleaf is not counted as a page +\widowpenalty 10000 % completely discourage widow lines +\clubpenalty 10000 % completely discourage club (orphan) lines +\raggedbottom % don't force alignment of bottom of pages + +\date{\today} +\newif\ifproject\projectfalse +\def\project#1{\projecttrue\gdef\@project{#1}} +\def\@project{} +\newif\ifemail\emailfalse +\def\email#1{\emailtrue\gdef\@email{#1}} +\def\@email{} +\def\revision#1{\gdef\r@vision{#1}} +\def\r@vision{} +\def\at{\makeatletter @\makeatother} +\newdateformat{theyear}{\THEYEAR} +\newenvironment{revisionhistory}{\clearpage\typeout{^^JRevision History.}% + \hbox to \textwidth{\hfil\scalebox{1.8}{\large\bfseries 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Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{wishboneds}{\begin{tabular}{|p{2.5in}|p{2.5in}|}\hline + \rowcolor[gray]{0.85} Description & Specification \\\hline\hline}% + {\end{tabular}} +\newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}} +\endinput Index: trunk/doc/src/spec.tex =================================================================== --- trunk/doc/src/spec.tex (nonexistent) +++ trunk/doc/src/spec.tex (revision 2) @@ -0,0 +1,473 @@ +\documentclass{gqtekspec} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Filename: spec.tex +%% +%% Project: wbuart32, a full featured UART with simulator +%% +%% Purpose: To describe, for LaTeX, how to build the specification file +%% for the wbuart32 core(s). This file is not nearly as +%% interesting as the file it creates, so I suggest you read spec.pdf +%% first, before deciding you are really interested in this file. +%% +%% Creator: Dan Gisselquist, Ph.D. +%% Gisselquist Technology, LLC +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Copyright (C) 2015-2016, Gisselquist Technology, LLC +%% +%% This program is free software (firmware): you can redistribute it and/or +%% modify it under the terms of the GNU General Public License as published +%% by the Free Software Foundation, either version 3 of the License, or (at +%% your option) any later version. +%% +%% This program is distributed in the hope that it will be useful, but WITHOUT +%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +%% for more details. +%% +%% You should have received a copy of the GNU General Public License along +%% with this program. (It's in the $(ROOT)/doc directory, run make with no +%% target there if the PDF file isn't present.) If not, see +%% for a copy. +%% +%% License: GPL, v3, as defined and found on www.gnu.org, +%% http://www.gnu.org/licenses/gpl.html +%% +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% +\usepackage{import} +\usepackage{bytefield} +\usepackage{amsmath} +\project{WBUART32} +\title{Specification} +\author{Dan Gisselquist, Ph.D.} +\email{dgisselq (at) opencores.org} +\revision{Rev.~0.1} +\begin{document} +\pagestyle{gqtekspecplain} +\titlepage +\begin{license} +Copyright (C) \theyear\today, Gisselquist Technology, LLC. + +This project is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy. +\end{license} +\begin{revisionhistory} +0.1 & 8/26/2016 & D. Gisselquist & Initial Draft Specification\\\hline +\end{revisionhistory} +% Revision History +% Table of Contents, named Contents +\tableofcontents +\listoffigures +\listoftables +\begin{preface} +It may be that building a UART is a mandatory coming of age task for any HDL +designer. The task is simple, easy, and there's not all that much to it. +This project comes out of some of my first experiences with Verilog. + +Since then, it has been augmented with a very useful capability for +simulating a UART connection when using Verilator. It is this, perhaps +unusual, addition to the core set that makes this core worth taking note of. + +I hope you find it useful. +\end{preface} + +\chapter{Introduction}\label{ch:intro} +\pagenumbering{arabic} +\setcounter{page}{1} +% +% Introduction +% +% This section contains the introduction to the core, describing both its +% use and its features. +% + +% What is old +The Universal Asynchronous Serial Transport, or UART, has become quite the +common protocol between devices. It is simple to wire up, easy to use, and +easy to process. This core provides one implementation of the logic necessary +to use such a communications scheme. + +% What does the old lack? +% What is new +% What does the new have that the old lacks +% What performance gain can be expected? + +While you are likely to find many UART examples out there, this particular +UART implementation offers something many of these other examples do not: a +Verilator simulation capability. This will allow the user to connect, via +a TCP/IP port or a telnet application, to the UART of their desired chip. As +a result, full two-way interaction can be had between a simulation and a +terminal or other port. Indeed, this may even be sufficient to connect a +CPU, capable of running Linux, to a terminal to verify that yes it can truly +run Linux--all within Verilator. + +\chapter{Architecture}\label{ch:arch} + +The HDL portion of the core itself consists of three files: {\tt rxuart.v}, +{\tt txuart.v}, and {\tt wbuart-insert.v}. These are, respectively, the +receive UART code, the transmit UART code, and an example of how the receiver +and transmitter may be connected to a Wishbone bus. + +Each of the core files, {\tt rxuart.v} and {\tt txuart.v}, are fully capable. +They each accept a 29--bit setup value specifying baud rate, the number of bits +per byte (between 5 and 8), whether or not parity is used, whether that parity +is even, odd, or fixed mark or fixed space. This setup register will be +discussed further in Chap.\ref{ch:registers}. + +A further note on the {\tt rxuart.v} module is in order. This module double +latches the input, in the proper two buffer fashion to avoid problems with +metastability. Then, upon the detection of the start bit (i.e. a high to low +transition), the port waits a half of a baud, and then starts its baud clock +so as to sample in the middle of every baud following. The result of this is +a timing requirement: after $N+2$ baud intervals ($N+3$ if parity is used), +where $N$ is the number of bits per byte, this calculated middle sample must +still lie within the associated bit period. This leaves us with the criteria +that, +\begin{eqnarray} +\left|\left(N+2\right) + \left(\frac{f_{\mbox{\tiny SYS}}}{f_{\mbox{\tiny BAUD}}} + -{\mbox{\tt CKS}}\right)\right| + &<& \frac{f_{\mbox{\tiny SYS}}}{2f_{\mbox{\tiny BAUD}}}, + \label{eqn:baudlimit}. +\end{eqnarray} +where $f_{\mbox{\tiny SYS}}$ is the system clock frequency, +$f_{\mbox{\tiny BAUD}}$ is the baud rate or frequency, +{\tt CKS} is the number of clocks per baud as set in the configuration +register, and $N$ is the number of bits per byte. What this means is that, +for transmission rates where $f_{\mbox{\tiny BAUD}}$ approaches +$f_{\mbox{\tiny SYS}}$, the number of data rates that can actually be +synthesized becomes limited. + +Connecting to either {\tt txuart.v} or {\tt rxuart.v} is quite simple. Both +files have a data port and a strobe. To transmit, set the data and strobe +lines. Drop the strobe line as soon as the strobe is asserted and the busy line +is not. Likewise, to connect to the {\tt rxuart.v} port, there is a data +and a strobe. This time, though, these two wires are outputs of the port as +opposed to inputs. +When the strobe is high, the data is valid. It will only be high for one +clock period. If you wish to connect this output to a bus, a register will be +needed to hold the strobe high until the data is read. Also, while the strobe +is high, the {\tt o\_break} line will indicate whether the receiver is in a +``break'' state, {\tt o\_frame\_err} will indicate whether or not there was a +framing error (i.e., no stop bit), and {\tt o\_parity\_err} will indicate +wheher or not the parity matched. + +The {\tt tx\_busy} line may be inverted and connected to a transmit interrupt +line. In a similar fashion, the {\tt rx\_stb} line, or the bus equivalent of +{\tt rx\_ready}, may be used for receive interrupt lines. + +An example of how to put this configuration together is found in +{\tt wbuart-insert.v}. In this example given, the {\tt rx\_data} register +will have only the lower eight bits set if the data is valid, higher bits will +be set upon error conditions, and cleared automatically upon the next byte read. +In a similar fashion, the {\tt tx\_data} register can be written to with a byte +in order to transmit that byte. Writing bit nine will place the transmitter +into a ``break'' condition, only cleared by writing a zero to that bit later. +Reading from the {\tt tx\_data} register can also be used to determine if the +transmitter is busy (via polling), whether it is currently in a break condition, +or even what bit is currently being placed to the output port. + +The C++ simulation portion of the code revolves around the file +{\tt bench/cpp/uartsim.cpp} and its associated header. This file defines a +class, {\tt UARTSIM}, which can be used to connect the UART to a TCP/IP stream. +When initialized, this class takes, as input, the TCP/IP port number that the +class is to connect with. Once connected, using this is as simple as +calculating the receive input bit from the transmit output bit when the +clock is low, and the core takes care of everything else. + +\chapter{Operation}\label{ch:ops} + +% This section describes the operation of the core. Specific sequences, such +% as startup sequences, as well as the modes and states of the block should be +% described. +% + +To use the core, a couple of steps are required. First, wire it up. The +{\tt wbuart-insert.v} file should provide a good example of how to wire it up. +Second, set the UART configuration register. This is ideally set in an +initial statement within the code somewhere, but can easily be set elsewhere +by writing to this register from the bus. + +From a simulation standpoint, it will also need to be wired up. Somewhere, +internal to the top--level Verilator C++ simulation file, you'll want to +have a line similar to, +\begin{tabbing} +{\tt if (!clk)} \= \\ +\> {\tt tb->i\_rx} {\tt = } {\tt uartsim(tb->o\_uart, setup);} +\end{tabbing} + +To use the transmitter, set the {\tt i\_stb} and {\tt i\_data} wires. Drop +the strobe line any time after {\tt (i\_stb)\&\&(!o\_busy)}. + +To use the receiver, grab the data any time {\tt o\_stb} is true. + +From the standpoint of the bus, there are two ways to handle receiving and +transmitting: polling and interrupt based, although both work one character at +a time. To poll, repeatedly read the receive data register until only no +bits but the bottom eight are set. This is an indication that the byte is +valid. Alternatively, you could wait until the an interrupt line is set and +then read. In the {\tt wbuart-insert.v} example, the {\tt rx\_int} line will +be set, and automatically cleared upon any read. To write, one can read from +the transmit data register until the eighth bit, the {\tt tx\_busy} bit, is +cleared, and then transmit. Alternatively, this negation of this bit may be +connected to an interrupt line. Writing to the port while idle will start +it transmitting. Writing to the port while it is busy will fill a one word +buffer that will get sent as soon as the port is idle for one clock. + + +\chapter{Registers}\label{ch:registers} +% This section specifies all internal registers. It should completely cover +% the interface between the CPU and the host as seen from the software point +% of view. + +% List of Registers + +% Register 1 Description +% +% You shall choose the style of register you prefer. Do not use both options +% in one and the same document. (Table of bits, vs. byetarray type of +% description). + +The core really only has one register associated with it, which is the setup +register. The format of this register is important, although not necessarily +trivial or obvious. We'll cover two other registers here, though, associated +with the example wishbone connections from {\tt wbuart-insert.v}. All three +of these registers are shown in Tbl.~\ref{tbl:reglist}. +\begin{table} +\begin{center} +\begin{reglist} +SETUP & & 30 & R/W & UART configuration/setup register.\\\hline +RX\_DATA & & 12 & R(/W) & Read data, reads from the UART.\\\hline +TX\_DATA & & 12 & (R/)W & Transmit data: writes send out the UART.\\\hline +\end{reglist}\caption{UART Registers}\label{tbl:reglist} +\end{center}\end{table} + +Since the connections presented are only examples, they are listed without +addresses, as their wishbone bus connectivity will be determined once they +are connected. + +\section{Setup Register} +The setup register is perhaps the most critical of all the registers. This +is shown in Fig.\ref{fig:SETUP}. +\begin{figure}\begin{center} +\begin{bytefield}[endianness=big]{32} +\bitheader{0-31}\\ +\bitbox{2}{00} +\bitbox{2}{N} +\bitbox{1}{S} +\bitbox{1}{P} +\bitbox{1}{F} +\bitbox{1}{T} +\bitbox{24}{Baud CLKS} +\end{bytefield} +\caption{SETUP Register fields}\label{fig:SETUP} +\end{center}\end{figure} +It is designed so that, for any 8N1 protocol (eight data bits, no parity, one +stop bit), only the number of clocks per baud interval needs to be set. The +top two bits are unused, making this a 30--bit number. The other fields +are: $N$ sets the number of bits per word. A value of zero corresponds +to 8--bit words, a value of one to seven bit words, and so forth up to a value +of three for five bit words. $S$ determines the number of stop bits. Set this +to one for two stop bits, or leave it clear for a single stop bit. $P$ +determines whether or not a parity bit exists (1 for parity, 0 for none), +while $F$ determines whether or not the parity is fixed. Tbl.~\ref{fig:parity} +lists out the various values possible here. +\begin{table}\begin{center} +\begin{tabular}{ccc|l} +P&F&T&Setting \\\hline\hline +1 & 0 & 0 & Odd parity \\\hline +1 & 0 & 1 & Even parity \\\hline +1 & 1 & 0 & Parity bit is a Space (1'b0)\\\hline +1 & 1 & 1 & Parity bit is a Mark (1'b1)\\\hline +0 & & & No parity \\\hline +\end{tabular}\caption{Parity setup}\label{tbl:parity} +\end{center}\end{table} + +\section{RX\_DATA Register} +Fig.~\ref{fig:RXDATA} +\begin{figure}\begin{center} +\begin{bytefield}[endianness=big]{32} +\bitheader{0-31}\\ +\bitbox{20}{20'h00} +\bitbox{1}{B} +\bitbox{1}{F} +\bitbox{1}{P} +\bitbox{1}{S} +\bitbox{8}{RWORD} +\end{bytefield} +\caption{RXDATA Register fields}\label{fig:RXDATA} +\end{center}\end{figure} +breaks out the various bit fields of the receive +data register used in the {\tt wbuart-insert.v} example of connecting it to +a bus. In particular, the $B$ field indicates that the receive line is in +a break condition. The $F$ and $P$ fields indicate that a frame error or +parity error were detected. These are valid like the data word: when the strobe +line is set. The $S$ field will be false when the {\tt RWORD} is valid. +Hence, if {\tt (RWORD \& ~0x0ff)} is zero there is a word ready to be received +without error. + +\section{TX\_DATA Register} +Fig.~\ref{fig:TXDATA} +\begin{figure}\begin{center} +\begin{bytefield}[endianness=big]{32} +\bitheader{0-31}\\ +\bitbox{20}{2'h00} +\bitbox{1}{C} +\bitbox{1}{O} +\bitbox{1}{B} +\bitbox{1}{S} +\bitbox{8}{TWORD} +\end{bytefield} +\caption{TXDATA Register fields}\label{fig:TXDATA} +\end{center}\end{figure} +breaks out the various bit fields of the transmit data register used in +{\tt wbuart-insert.v}. The $C$ field indicates whether or not the receive +data line is high or low, the $O$ field indicates the same for the transmit +line. These aren't particularly useful or valuable, but they don't fit in the +receive data register since they would violate the error condition detector. +They're thrown in here for whatever useful purpose one might find. The $B$ +field, when set, sends a break condition down the wire. Writing to the TXDATA +register, clearing the $B$ field, will clear the transmitter from the break +condition without transmitting anything. The $S$ field is similar to the RXDATA +strobe register. It will be true whenever the transmitter is busy or a byte +is waiting for it. It will be clear only when the transmitter is idle. + +To use the transmitter, simply write a byte to the TXDATA register with the +upper 24--bits clear to transmit. + +\chapter{Clocks}\label{ch:clocks} +The UART has been tested with a clock as fast as 200~MHz +(Tbl.~\ref{tbl:clocks}). +\begin{table}\begin{center} +\begin{clocklist} +{\tt i\_clk} & (System) & 200~MHz & & System clock\\\hline +\end{clocklist} +\caption{Clock Requirements}\label{tbl:clocks} +\end{center}\end{table} +It should be able to use slower clocks, but only subject to the ability to +properly set the baud rate as shown in Eqn.~\eqref{eqn:baudlimit} on +Page~\pageref{eqn:baudlimit}. + +I do not recommend using this core with a baud rate greater than a quarter +of the system clock rate. + +% This section specifies all of the clocks. All clocks, clock domain passes +% and the clock relations should be described. + +% Name | Source | Rates (MHz) | Remarks | Description +% | Max|Min|Resolution| +\chapter{Wishbone Datasheet}\label{ch:wishbone} + +Tbl.~\ref{tbl:wishbone} +\begin{table}[htbp] +\begin{center} +\begin{wishboneds} +Revision level of wishbone & WB B4 spec \\\hline +Type of interface & Slave, Read/Write, pipeline reads supported \\\hline +Port size & 32--bit \\\hline +Port granularity & 32--bit \\\hline +Maximum Operand Size & 32--bit \\\hline +Data transfer ordering & (Irrelevant) \\\hline +Clock constraints & None.\\\hline +Signal Names & \begin{tabular}{ll} + Signal Name & Wishbone Equivalent \\\hline + {\tt i\_wb\_clk} & {\tt CLK\_I} \\ + {\tt i\_wb\_cyc} & {\tt CYC\_I} \\ + {\tt i\_wb\_stb} & {\tt STB\_I} \\ + {\tt i\_wb\_we} & {\tt WE\_I} \\ + {\tt i\_wb\_addr} & {\tt ADR\_I} \\ + {\tt i\_wb\_data} & {\tt DAT\_I} \\ + {\tt o\_wb\_ack} & {\tt ACK\_O} \\ + {\tt o\_wb\_stall} & {\tt STALL\_O} \\ + {\tt o\_wb\_data} & {\tt DAT\_O} + \end{tabular}\\\hline +\end{wishboneds} +\caption{Wishbone Datasheet}\label{tbl:wishbone} +\end{center}\end{table} +is required by the wishbone specification in order to declare the core as +wishbone compliant, and so it is included here. It references the connections +exemplified by {\tt wbuart-insert.v}. The big thing to notice is that this core +acts as a wishbone slave, and that all accesses to the core +registers are 32--bit reads and writes to this interface. + +What this table doesn't show is that all accesses to the port take a single +clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the +{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall} +line is tied to zero. + +Also, this particular wishbone implementation assumes that if {\tt i\_wb\_stb}, +then {\tt i\_wb\_cyc} will be high as well. Hence it only checks whether or not +{\tt i\_wb\_stb} is true to determine if a transaction has taken place. If your +bus does not meet this requirement, you'll need to AND {\tt i\_wb\_stb} with +{\tt i\_wb\_cyc} before using the core. + +\chapter{I/O Ports}\label{ch:ioports} +% This section specifies all of the core IO ports + +In it's simplest form, the UART offers simply two I/O ports: the {\tt i\_rx} +line to receive, and the {\tt o\_tx} line to transmit. These lines need to be +brought to the outside of your design. Within verilator, they need to be +connected inside your verilator test bench, as in: +\begin{tabbing} +{\tt if (!clk)} \= \\ +\> {\tt tb->i\_rx} {\tt = } {\tt uartsim(tb->o\_uart, setup);} +\end{tabbing} + +A more detailed discussion of the connections associated with these modules +can begin with Tbl.~\ref{tbl:rxports}, detailing the I/O ports of the +UART receiver, and Tbl.~\ref{tbl:txports}, +\begin{table}\begin{center}\begin{portlist} +{\tt i\_clk} & 1 & Input & The system clock \\\hline +{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline +{\tt i\_setup} & 30 & Input & The 30--bit setup register \\\hline +{\tt i\_uart} & 1 & Input & The input wire from the outside world. \\\hline +{\tt o\_wr} & 1 & Output & True if a word was received. At this time, + {\tt o\_data}, {\tt o\_break}, {\tt o\_parity\_err}, and + {\tt o\_frame\_err} will also be valid. \\\hline +{\tt o\_data} & 8 & Output & The received data, valid if {\tt o\_wr} \\\hline +{\tt o\_break} & 1 & Output & True in the case of a break condition \\\hline +{\tt o\_parity\_err} & 1 & Output & True if a parity error was detected \\\hline +{\tt o\_frame\_err} & 1 & Output & True if a frame error was detected \\\hline +{\tt o\_ck\_uart} & 1 & Output & A synchronized copy of {\tt i\_uart} \\\hline +\end{portlist}\caption{RXUART port list}\label{tbl:rxports} +\end{center}\end{table} +detailing the I/O ports of the UART transmitter. +\begin{table}\begin{center}\begin{portlist} +{\tt i\_clk} & 1 & Input & The system clock \\\hline +{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline +{\tt i\_setup} & 30 & Input & The 30--bit setup register \\\hline +{\tt i\_break} & 1 & Input & Set to true to place the transmit channel into a break condition\\\hline +{\tt i\_wr} & 1 & Input & An input strobe. Set to one when you wish to transmit data, clear once it has been accepted\\\hline +{\tt i\_data} & 8 & Input & The data to be transmitted, ignored unless + {\tt (i\_wr)\&\&(!o\_busy)} \\\hline +{\tt o\_uart} & 1 & Output & The wire to be connected to the external port\\\hline +{\tt o\_busy} & 1 & Output & True if the transmitter is busy, false if it will receive data\\\hline +\end{portlist}\caption{TXUART port list}\label{tbl:txports} +\end{center}\end{table} + +The ``ports'' associated with the {\tt wbuart-insert.v} example may be +inferred from the wishbone data sheet. + +% Appendices +% A. May be added to outline different specifications. (??) + + +% Index +\end{document} + + Index: trunk/doc/gpl-3.0.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/gpl-3.0.pdf =================================================================== --- trunk/doc/gpl-3.0.pdf (nonexistent) +++ trunk/doc/gpl-3.0.pdf (revision 2)
trunk/doc/gpl-3.0.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Makefile =================================================================== --- trunk/doc/Makefile (nonexistent) +++ trunk/doc/Makefile (revision 2) @@ -0,0 +1,83 @@ +################################################################################ +## +## Filename: Makefile +## +## Project: wbuart32, a full featured UART with simulator +## +## Purpose: To coordinate the build of documentation PDFs from their +## LaTeX sources. +## +## Targets include: +## all Builds all documents +## +## gpl-3.0.pdf Builds the GPL license these files are released +## under. +## +## spec.pdf Builds the specification for the SDSPI +## controller. +## +## Creator: Dan Gisselquist, Ph.D. +## Gisselquist Technology, LLC +## +################################################################################ +## +## Copyright (C) 2015-2016, Gisselquist Technology, LLC +## +## This program is free software (firmware): you can redistribute it and/or +## modify it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or (at +## your option) any later version. +## +## This program is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with this program. (It's in the $(ROOT)/doc directory, run make with no +## target there if the PDF file isn't present.) If not, see +## for a copy. +## +## License: GPL, v3, as defined and found on www.gnu.org, +## http://www.gnu.org/licenses/gpl.html +## +## +################################################################################ +## +## +all: gpl spec +pdf: gpl spec +DSRC := src + +.PHONY: gpl +gpl: gpl-3.0.pdf + +gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi + ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf + rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps + +.PHONY: spec +spec: spec.pdf + +spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps + cd $(DSRC)/; latex spec.tex + cd $(DSRC)/; latex spec.tex + cd $(DSRC)/; dvips -q -z -t letter -P pdf -o ../spec.ps spec.dvi + ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf + -grep -i warning $(DSRC)/spec.log + @rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log + @rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc + @rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof + @rm -f $(DSRC)/spec.out spec.ps + +.PHONY: clean +clean: + rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log + rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc + rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof + rm -f $(DSRC)/spec.out spec.ps spec.pdf + rm -f gpl-3.0.pdf + Index: trunk/Makefile =================================================================== --- trunk/Makefile (nonexistent) +++ trunk/Makefile (revision 2) @@ -0,0 +1,67 @@ +################################################################################ +## +## Filename: Makefile +## +## Project: wbuart32, a full featured UART with simulator +## +## Purpose: This is the master Makefile for the project. It coordinates +## the build of a Verilator test, "proving" that this core works +## (to the extent that any simulated test "proves" anything). This +## make file depends upon the proper setup of Verilator. +## +## Creator: Dan Gisselquist, Ph.D. +## Gisselquist Technology, LLC +## +################################################################################ +## +## Copyright (C) 2015-2016, Gisselquist Technology, LLC +## +## This program is free software (firmware): you can redistribute it and/or +## modify it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or (at +## your option) any later version. +## +## This program is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with this program. (It's in the $(ROOT)/doc directory, run make with no +## target there if the PDF file isn't present.) If not, see +## for a copy. +## +## License: GPL, v3, as defined and found on www.gnu.org, +## http://www.gnu.org/licenses/gpl.html +## +## +################################################################################ +## +## +all: rtl bench test + +.PHONY: doc +doc: + cd doc ; $(MAKE) --no-print-directory + +.PHONY: rtl +rtl: + cd rtl ; $(MAKE) --no-print-directory + +.PHONY: bench +bench: rtl + cd bench/verilog ; $(MAKE) --no-print-directory + cd bench/cpp ; $(MAKE) --no-print-directory + +.PHONY: test +test: bench + bench/cpp/linetest + +.PHONY: clean +clean: + cd rtl ; $(MAKE) --no-print-directory clean + cd bench/verilog ; $(MAKE) --no-print-directory clean + cd bench/cpp ; $(MAKE) --no-print-directory clean + cd doc ; $(MAKE) --no-print-directory clean + +

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