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/verilog/minsoc/mc/mc_cs_rf.v
0,0 → 1,276
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller Chip Select Register File ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_cs_rf.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_cs_rf.v,v $
// Revision 1.6 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:42 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_cs_rf(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
wp_err, lmr_req, lmr_ack, init_req, init_ack );
 
input clk, rst;
input wb_we_i;
input [31:0] din;
input rf_we;
input [31:0] addr;
 
output [31:0] csc;
output [31:0] tms;
input [31:0] poc;
input [31:0] csc_mask;
output cs;
output wp_err;
 
output lmr_req;
input lmr_ack;
output init_req;
input init_ack;
 
parameter [2:0] this_cs = 0;
parameter [3:0] reg_select = this_cs + 2;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
 
reg [31:0] csc;
reg [31:0] tms;
wire sel;
wire cs_d;
wire wp;
reg inited;
reg init_req;
reg init_req_we;
reg lmr_req;
reg lmr_req_we;
 
////////////////////////////////////////////////////////////////////
//
// A kludge for cases where there is no clock during reset ...
//
 
reg rst_r1, rst_r2;
 
always @(posedge clk or posedge rst)
if(rst) rst_r1 <= #1 1'b1;
else rst_r1 <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) rst_r2 <= #1 1'b1;
else rst_r2 <= #1 rst_r1;
 
////////////////////////////////////////////////////////////////////
//
// Write Logic
//
 
reg [6:0] addr_r;
 
always @(posedge clk)
addr_r <= #1 addr[6:0];
 
assign sel = addr_r[6:3] == reg_select[3:0];
 
always @(posedge clk)
if(rst_r2) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;
else
if(rf_we & sel & !addr_r[2]) csc <= #1 din;
 
always @(posedge clk)
if(rst_r2) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
`MC_DEF_POR_TMS : 32'h0;
else
if(rf_we & sel & addr_r[2]) tms <= #1 din;
 
////////////////////////////////////////////////////////////////////
//
// Load Mode Register Request/Ack Logic
//
always @(posedge clk or posedge rst)
if(rst) lmr_req_we <= #1 1'b0;
else lmr_req_we <= #1 rf_we & sel & addr_r[2];
 
always @(posedge clk or posedge rst)
if(rst) lmr_req <= #1 1'b0;
else
if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))
lmr_req <= #1 inited;
else
if(lmr_ack) lmr_req <= #1 1'b0;
 
////////////////////////////////////////////////////////////////////
//
// Initialize SDRAM Request/Ack & tracking logic
//
always @(posedge clk or posedge rst)
if(rst) init_req_we <= #1 1'b0;
else init_req_we <= #1 rf_we & sel & !addr_r[2];
 
always @(posedge clk or posedge rst)
if(rst) init_req <= #1 1'b0;
else
if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)
init_req <= #1 1'b1;
else
if(init_ack) init_req <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) inited <= #1 1'b0;
else
if(init_ack) inited <= #1 1'b1;
 
////////////////////////////////////////////////////////////////////
//
// Chip Select Generation Logic
//
 
assign cs_d = ((csc[23:16] & csc_mask[7:0]) == (addr[28:21] & csc_mask[7:0])) & csc[0];
 
assign wp = wb_we_i & csc[8];
 
assign wp_err = cs_d & wp;
assign cs = cs_d & !wp;
 
endmodule
 
 
 
// This dummy is used to terminate the outputs for non existing Chip Selects
module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
wp_err, lmr_req, lmr_ack, init_req, init_ack );
 
parameter [2:0] this_cs = 0;
 
input clk, rst;
input wb_we_i;
input [31:0] din;
input rf_we;
input [31:0] addr;
 
output [31:0] csc;
output [31:0] tms;
input [31:0] poc;
input [31:0] csc_mask;
output cs;
output wp_err;
 
output lmr_req;
input lmr_ack;
output init_req;
input init_ack;
 
assign csc = 32'h0;
assign tms = 32'h0;
assign cs = 1'b0;
assign wp_err = 1'b0;
assign lmr_req = 1'b0;
assign init_req = 1'b0;
 
endmodule
/verilog/minsoc/mc/mc_mem_if.v
0,0 → 1,362
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Memory Bus Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_mem_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_mem_if.v,v $
// Revision 1.6 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.5 2001/12/21 05:09:29 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/09/02 02:28:28 rudi
//
// Many fixes for minor bugs that showed up in gate level simulations.
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/14 01:57:37 rudi
//
//
// Fixed a potential bug in a corner case situation where the TMS register
// does not propegate properly during initialisation.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:48 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,
mc_addr, mc_data_o, mc_dp_o, mc_data_oe,
mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,
mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d,
mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r,
we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack,
cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel,
suspended_o, oe_, wb_cyc_i, wb_stb_i, wb_sel_i, wb_cycle,
wr_cycle, mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i,
mc_zz_o
);
// Memory Interface
input clk;
input rst;
input mc_clk;
input mc_br;
output mc_bg;
output [23:0] mc_addr;
output [31:0] mc_data_o;
output [3:0] mc_dp_o;
output mc_data_oe;
output [3:0] mc_dqm;
output mc_oe_;
output mc_we_;
output mc_cas_;
output mc_ras_;
output mc_cke_;
output [7:0] mc_cs_;
output mc_adsc_;
output mc_adv_;
input mc_ack;
output mc_rp;
output mc_c_oe;
output [35:0] mc_data_ir;
output mc_sts_ir;
output mc_zz_o;
 
// Internal Interface
output mc_br_r;
input mc_bg_d;
input data_oe;
input susp_sel;
input suspended_o;
input [31:0] mc_data_od;
input [3:0] mc_dp_od;
input [23:0] mc_addr_d;
output mc_ack_r;
input wb_cyc_i;
input wb_stb_i;
input [3:0] wb_sel_i;
input wb_cycle;
input wr_cycle;
input oe_ ;
input we_;
input ras_;
input cas_;
input cke_;
input cs_en;
input rfr_ack;
input [7:0] cs_need_rfr;
input lmr_sel;
input [7:0] spec_req_cs;
input [7:0] cs;
input fs;
input mc_adsc_d;
input mc_adv_d;
input mc_c_oe_d;
input [31:0] mc_data_i;
input [3:0] mc_dp_i;
input mc_sts_i;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg mc_data_oe;
reg [31:0] mc_data_o;
reg [3:0] mc_dp_o;
reg [3:0] mc_dqm;
reg [3:0] mc_dqm_r;
reg [23:0] mc_addr;
reg mc_oe_;
reg mc_we_;
reg mc_cas_;
reg mc_ras_;
wire mc_cke_;
reg [7:0] mc_cs_;
reg mc_bg;
reg mc_adsc_;
reg mc_adv_;
reg mc_br_r;
reg mc_ack_r;
reg mc_rp;
reg mc_c_oe;
reg mc_zz_o;
 
reg [35:0] mc_data_ir;
reg mc_sts_ir;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge mc_clk)
mc_zz_o <= #1 suspended_o;
 
always @(posedge mc_clk)
mc_sts_ir <= #1 mc_sts_i;
 
always @(posedge mc_clk)
mc_data_ir <= #1 {mc_dp_i, mc_data_i};
 
always @(posedge mc_clk)
mc_c_oe <= #1 mc_c_oe_d;
 
always @(posedge mc_clk)
mc_rp <= #1 !suspended_o & !fs;
 
always @(posedge mc_clk)
mc_br_r <= #1 mc_br;
 
always @(posedge mc_clk)
mc_ack_r <= #1 mc_ack;
 
always @(posedge mc_clk)
mc_bg <= #1 mc_bg_d;
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_data_oe <= #1 1'b0;
else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d;
 
always @(posedge mc_clk)
mc_data_o <= #1 mc_data_od;
 
always @(posedge mc_clk)
mc_dp_o <= #1 mc_dp_od;
 
always @(posedge mc_clk)
mc_addr <= #1 mc_addr_d;
 
always @(posedge clk)
if(wb_cyc_i & wb_stb_i)
mc_dqm_r <= #1 wb_sel_i;
 
reg [3:0] mc_dqm_r2;
always @(posedge clk)
mc_dqm_r2 <= #1 mc_dqm_r;
 
always @(posedge mc_clk)
mc_dqm <= #1 susp_sel ? 4'hf :
data_oe ? ~mc_dqm_r2 :
(wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_oe_ <= #1 1'b1;
else mc_oe_ <= #1 oe_ | susp_sel;
 
always @(posedge mc_clk)
mc_we_ <= #1 we_;
 
always @(posedge mc_clk)
mc_cas_ <= #1 cas_;
 
always @(posedge mc_clk)
mc_ras_ <= #1 ras_;
 
assign mc_cke_ = cke_;
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[0] <= #1 1'b1;
else
mc_cs_[0] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[0] :
lmr_sel ? spec_req_cs[0] :
cs[0]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[1] <= #1 1'b1;
else
mc_cs_[1] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[1] :
lmr_sel ? spec_req_cs[1] :
cs[1]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[2] <= #1 1'b1;
else
mc_cs_[2] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[2] :
lmr_sel ? spec_req_cs[2] :
cs[2]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[3] <= #1 1'b1;
else
mc_cs_[3] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[3] :
lmr_sel ? spec_req_cs[3] :
cs[3]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[4] <= #1 1'b1;
else
mc_cs_[4] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[4] :
lmr_sel ? spec_req_cs[4] :
cs[4]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[5] <= #1 1'b1;
else
mc_cs_[5] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[5] :
lmr_sel ? spec_req_cs[5] :
cs[5]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[6] <= #1 1'b1;
else
mc_cs_[6] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[6] :
lmr_sel ? spec_req_cs[6] :
cs[6]
));
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[7] <= #1 1'b1;
else
mc_cs_[7] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[7] :
lmr_sel ? spec_req_cs[7] :
cs[7]
));
 
always @(posedge mc_clk)
mc_adsc_ <= #1 ~mc_adsc_d;
 
always @(posedge mc_clk)
mc_adv_ <= #1 ~mc_adv_d;
 
endmodule
/verilog/minsoc/mc/mc_defines.v
0,0 → 1,234
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller Definitions ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_defines.v,v 1.7 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_defines.v,v $
// Revision 1.7 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.6 2001/12/12 06:35:15 rudi
// *** empty log message ***
//
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.3 2001/09/10 13:44:17 rudi
// *** empty log message ***
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug
// fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:38 rudi
// Created Directory Structure
//
//
//
//
 
`timescale 1ns / 10ps
 
/////////////////////////////////////////////////////////////////////
//
// This define selects how the WISHBONE interface determines if
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_REG_SEL (wb_addr_i[27] == 1'b1)
 
// This define selects how the WISHBONE interface determines if
// the memory is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_MEM_SEL (wb_addr_i[27] == 1'b0)
 
/////////////////////////////////////////////////////////////////////
//
// This are the default Power-On Reset values for Chip Select
//
 
// This will be defined by the run script for my test bench ...
// Alternatively force here for synthesis ...
//`define RUDIS_TB 1
 
// Defines which chip select is used for Power On booting
 
// To run my default testbench default boot CS must be 3 !!!
`ifdef RUDIS_TB
`define MC_DEF_SEL 3'h3
`else
`define MC_DEF_SEL 3'h0
`endif
 
// Defines the default (reset) TMS value for the DEF_SEL chip select
`define MC_DEF_POR_TMS 32'hffff_ffff
 
 
/////////////////////////////////////////////////////////////////////
//
// Define how many Chip Selects to Implement
//
//`define MC_HAVE_CS1 1
//`define MC_HAVE_CS2 1
//`define MC_HAVE_CS3 1
//`define MC_HAVE_CS4 1
//`define MC_HAVE_CS5 1
//`define MC_HAVE_CS6 1
//`define MC_HAVE_CS7 1
 
 
// To run my default testbench those need to there !!!
`ifdef RUDIS_TB
`define MC_HAVE_CS2 1
`define MC_HAVE_CS3 1
`define MC_HAVE_CS4 1
`define MC_HAVE_CS5 1
`endif
 
/////////////////////////////////////////////////////////////////////
//
// Init Refresh
//
// Number of Refresh Cycles to perform during SDRAM initialization.
// This varies between SDRAM manufacturer. Typically this value is
// between 2 and 8. This number must be smaller than 16.
`define MC_INIT_RFRC_CNT 8
 
/////////////////////////////////////////////////////////////////////
//
// Power On Delay
//
// Most if SDRAMs require some time to initialize before they can be used
// after power on. If the Memory Controller shall stall after power on to
// allow SDRAMs to finish the initialization process uncomment the below
// define statement
`define MC_POR_DELAY 1
 
// This value defines how many MEM_CLK cycles the Memory Controller should
// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250
// cycles.
`define MC_POR_DELAY_VAL 8'd250
 
 
// ===============================================================
// ===============================================================
// Various internal defines (DO NOT MODIFY !)
// ===============================================================
// ===============================================================
 
// Register settings encodings
`define MC_BW_8 2'h0
`define MC_BW_16 2'h1
`define MC_BW_32 2'h2
 
`define MC_MEM_TYPE_SDRAM 3'h0
`define MC_MEM_TYPE_SRAM 3'h1
`define MC_MEM_TYPE_ACS 3'h2
`define MC_MEM_TYPE_SCS 3'h3
 
`define MC_MEM_SIZE_64 2'h0
`define MC_MEM_SIZE_128 2'h1
`define MC_MEM_SIZE_256 2'h2
 
// Command Valid, Ras_, Cas_, We_
`define MC_CMD_NOP 4'b0111
`define MC_CMD_PC 4'b1010
`define MC_CMD_ACT 4'b1011
`define MC_CMD_WR 4'b1100
`define MC_CMD_RD 4'b1101
`define MC_CMD_BT 4'b1110
`define MC_CMD_ARFR 4'b1001
`define MC_CMD_LMR 4'b1000
`define MC_CMD_XRD 4'b1111
`define MC_CMD_XWR 4'b1110
 
`define MC_SINGLE_BANK 1'b0
`define MC_ALL_BANKS 1'b1
 
`define MC_BA_MASK_VAL 11'h020
`define MC_POC_VAL 32'h00000002
/verilog/minsoc/mc/mc_refresh.v
0,0 → 1,210
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Refresh Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_refresh.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_refresh.v,v $
// Revision 1.4 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.3 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.2 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:47 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_refresh(clk, rst,
cs_need_rfr, ref_int, rfr_req, rfr_ack,
rfr_ps_val
);
 
input clk, rst;
input [7:0] cs_need_rfr;
input [2:0] ref_int;
output rfr_req;
input rfr_ack;
input [7:0] rfr_ps_val;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg rfr_en;
reg [7:0] ps_cnt;
wire ps_cnt_clr;
reg rfr_ce;
reg [7:0] rfr_cnt;
reg rfr_clr;
reg rfr_req;
reg rfr_early;
 
/*
Refresh generation
 
The prescaler generates a 0.48828 uS clock enable
 
The refresh counter generates the following refresh rates:
(Actual values are about 0.63% below the desired values).
This is for a 200 Mhz WISHBONE Bus.
0.970 uS,
1.940
3.880
7.760
15.520
32.040
62.080
124.160 uS
 
(desired values)
0.976 uS
1.953
3.906
7.812
15.625
31.250
62.500
125.000 uS
*/
 
////////////////////////////////////////////////////////////////////
//
// Prescaler
//
 
always @(posedge clk or posedge rst)
if(rst) rfr_en <= #1 1'b0;
else rfr_en <= #1 |cs_need_rfr;
 
always @(posedge clk or posedge rst)
if(rst) ps_cnt <= #1 8'h0;
else
if(ps_cnt_clr) ps_cnt <= #1 8'h0;
else
if(rfr_en) ps_cnt <= #1 ps_cnt + 8'h1;
 
assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0);
 
always @(posedge clk or posedge rst)
if(rst) rfr_early <= #1 1'b0;
else rfr_early <= #1 (ps_cnt == rfr_ps_val);
 
////////////////////////////////////////////////////////////////////
//
// Refresh Counter
//
 
always @(posedge clk or posedge rst)
if(rst) rfr_ce <= #1 1'b0;
else rfr_ce <= #1 ps_cnt_clr;
 
always @(posedge clk or posedge rst)
if(rst) rfr_cnt <= #1 8'h0;
else
if(rfr_ack) rfr_cnt <= #1 8'h0;
else
if(rfr_ce) rfr_cnt <= #1 rfr_cnt + 8'h1;
 
always @(posedge clk)
case(ref_int) // synopsys full_case parallel_case
3'h0: rfr_clr <= #1 rfr_cnt[0] & rfr_early;
3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early;
3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early;
3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early;
3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early;
3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early;
3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early;
3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early;
endcase
 
always @(posedge clk or posedge rst)
if(rst) rfr_req <= #1 1'b0;
else
if(rfr_ack) rfr_req <= #1 1'b0;
else
if(rfr_clr) rfr_req <= #1 1'b1;
 
endmodule
/verilog/minsoc/mc/mc_top.v
0,0 → 1,549
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller Top Level ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_top.v,v 1.7 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_top.v,v $
// Revision 1.7 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.6 2001/12/21 05:09:30 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.5 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.4 2001/09/10 13:44:17 rudi
// *** empty log message ***
//
// Revision 1.3 2001/09/02 02:28:28 rudi
//
// Many fixes for minor bugs that showed up in gate level simulations.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:39 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_top(clk_i, rst_i,
 
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
 
susp_req_i, resume_req_i, suspended_o, poc_o,
 
mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i,
mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i,
mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_,
mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_,
mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o,
mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o
);
 
input clk_i, rst_i;
 
// --------------------------------------
// WISHBONE SLAVE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
 
// --------------------------------------
// Suspend Resume Interface
input susp_req_i;
input resume_req_i;
output suspended_o;
 
// POC
output [31:0] poc_o;
 
// --------------------------------------
// Memory Bus Signals
input mc_clk_i;
input mc_br_pad_i;
output mc_bg_pad_o;
input mc_ack_pad_i;
output [23:0] mc_addr_pad_o;
input [31:0] mc_data_pad_i;
output [31:0] mc_data_pad_o;
input [3:0] mc_dp_pad_i;
output [3:0] mc_dp_pad_o;
output mc_doe_pad_doe_o;
output [3:0] mc_dqm_pad_o;
output mc_oe_pad_o_;
output mc_we_pad_o_;
output mc_cas_pad_o_;
output mc_ras_pad_o_;
output mc_cke_pad_o_;
output [7:0] mc_cs_pad_o_;
input mc_sts_pad_i;
output mc_rp_pad_o_;
output mc_vpen_pad_o;
output mc_adsc_pad_o_;
output mc_adv_pad_o_;
output mc_zz_pad_o;
output mc_coe_pad_coe_o;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
// WISHBONE Interface Interconnects
wire wb_read_go;
wire wb_write_go;
wire wb_first;
wire wb_wait;
wire mem_ack;
 
// Suspend Resume Interface
wire susp_sel;
 
// Register File Interconnects
wire [31:0] rf_dout;
wire [31:0] csc;
wire [31:0] tms;
wire [31:0] sp_csc;
wire [31:0] sp_tms;
wire [7:0] cs;
wire fs;
wire cs_le;
wire [7:0] cs_need_rfr;
wire [2:0] ref_int;
wire [31:0] mem_dout;
wire wp_err;
 
// Address Select Signals
wire [12:0] row_adr;
wire [1:0] bank_adr;
wire cmd_a10;
wire row_sel;
wire next_adr;
wire [10:0] page_size;
wire lmr_sel;
wire wr_hold;
 
// OBCT Signals
wire bank_set;
wire bank_clr;
wire bank_clr_all;
wire bank_open;
wire row_same;
wire [7:0] obct_cs;
wire any_bank_open;
 
// Data path Controller Signals
wire dv;
wire pack_le0, pack_le1, pack_le2; // Pack Latch Enable
wire par_err;
wire [31:0] mc_data_od;
wire [3:0] mc_dp_od;
wire [23:0] mc_addr_d;
wire [35:0] mc_data_ir;
 
// Refresh Counter Signals
wire rfr_req;
wire rfr_ack;
wire [7:0] rfr_ps_val;
 
// Memory Timing Block Signals
wire data_oe;
wire oe_;
wire we_;
wire cas_;
wire ras_;
wire cke_;
wire lmr_req;
wire lmr_ack;
wire init_req;
wire init_ack;
wire [7:0] spec_req_cs;
wire cs_en;
wire wb_cycle, wr_cycle;
wire [31:0] tms_s;
wire [31:0] csc_s;
wire mc_c_oe_d;
wire mc_br_r;
wire mc_bg_d;
wire mc_adsc_d;
wire mc_adv_d;
wire mc_ack_r;
wire err;
wire mc_sts_i;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
(lmr_ack | init_ack) ? spec_req_cs : cs;
 
assign lmr_sel = lmr_ack | init_ack;
 
assign tms_s = lmr_sel ? sp_tms : tms;
assign csc_s = lmr_sel ? sp_csc : csc;
 
 
wire not_mem_cyc;
 
assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL );
 
reg mem_ack_r;
 
always @(posedge clk_i)
mem_ack_r <= #1 mem_ack;
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
mc_rf u0(
.clk( clk_i ),
.rst( rst_i ),
.wb_data_i( wb_data_i ),
.rf_dout( rf_dout ),
.wb_addr_i( wb_addr_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( ),
.wp_err( wp_err ),
.csc( csc ),
.tms( tms ),
.poc( poc_o ),
.sp_csc( sp_csc ),
.sp_tms( sp_tms ),
.cs( cs ),
.mc_data_i( mc_data_ir[31:0]),
.mc_sts( mc_sts_ir ),
.mc_vpen( mc_vpen_pad_o ),
.fs( fs ),
.cs_le( cs_le ),
.cs_le_d( cs_le_d ),
.cs_need_rfr( cs_need_rfr ),
.ref_int( ref_int ),
.rfr_ps_val( rfr_ps_val ),
.spec_req_cs( spec_req_cs ),
.init_req( init_req ),
.init_ack( init_ack ),
.lmr_req( lmr_req ),
.lmr_ack( lmr_ack )
);
 
mc_adr_sel u1(
.clk( clk_i ),
.csc( csc_s ),
.tms( tms_s ),
.wb_stb_i( wb_stb_i ),
//.wb_ack_o( wb_ack_o ),
.wb_ack_o( mem_ack_r ),
.wb_addr_i( wb_addr_i ),
.wb_we_i( wb_we_i ),
.wb_write_go( wb_write_go ),
.wr_hold( wr_hold ),
.cas_( cas_ ),
.mc_addr( mc_addr_d ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.rfr_ack( rfr_ack ),
.cs_le( cs_le ),
.cmd_a10( cmd_a10 ),
.row_sel( row_sel ),
.lmr_sel( lmr_sel ),
.next_adr( next_adr ),
.wr_cycle( wr_cycle ),
.page_size( page_size )
);
 
mc_obct_top u2(
.clk( clk_i ),
.rst( rst_i ),
.cs( obct_cs ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set ),
.bank_clr( bank_clr ),
.bank_clr_all( bank_clr_all ),
.bank_open( bank_open ),
.any_bank_open( any_bank_open ),
.row_same( row_same ),
.rfr_ack( rfr_ack )
);
 
mc_dp u3(
.clk( clk_i ),
.rst( rst_i ),
.csc( csc ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.mem_ack( mem_ack ),
//.wb_ack_o( wb_ack_o ),
.wb_ack_o( mem_ack_r ),
.wb_we_i( wb_we_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( mem_dout ),
.wb_read_go( wb_read_go ),
.mc_clk( mc_clk_i ),
.mc_data_del( mc_data_ir ),
.mc_dp_i( mc_dp_pad_i ),
.mc_data_o( mc_data_od ),
.mc_dp_o( mc_dp_od ),
.dv( dv ),
.pack_le0( pack_le0 ),
.pack_le1( pack_le1 ),
.pack_le2( pack_le2 ),
.byte_en( wb_sel_i ),
.par_err( par_err )
);
 
mc_refresh u4(
.clk( clk_i ),
.rst( rst_i ),
.cs_need_rfr( cs_need_rfr ),
.ref_int( ref_int ),
.rfr_req( rfr_req ),
.rfr_ack( rfr_ack ),
.rfr_ps_val( rfr_ps_val )
);
mc_timing u5(
.clk( clk_i ),
.mc_clk( mc_clk_i ),
.rst( rst_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_we_i( wb_we_i ),
.wb_read_go( wb_read_go ),
.wb_write_go( wb_write_go ),
.wb_first( wb_first ),
.wb_wait( wb_wait ),
.mem_ack( mem_ack ),
.err( err ),
.susp_req( susp_req_i ),
.resume_req( resume_req_i ),
.suspended( suspended_o ),
.susp_sel( susp_sel ),
.mc_br( mc_br_r ),
.mc_bg( mc_bg_d ),
.mc_ack( mc_ack_r ),
.not_mem_cyc( not_mem_cyc ),
.data_oe( data_oe ),
.oe_( oe_ ),
.we_( we_ ),
.cas_( cas_ ),
.ras_( ras_ ),
.cke_( cke_ ),
.cs_en( cs_en ),
.mc_adsc( mc_adsc_d ),
.mc_adv( mc_adv_d ),
.mc_c_oe( mc_c_oe_d ),
.wb_cycle( wb_cycle ),
.wr_cycle( wr_cycle ),
.csc( csc_s ),
.tms( tms_s ),
.cs( obct_cs ),
.lmr_req( lmr_req ),
.lmr_ack( lmr_ack ),
.cs_le( cs_le ),
.cs_le_d( cs_le_d ),
.cmd_a10( cmd_a10 ),
.row_sel( row_sel ),
.next_adr( next_adr ),
.page_size( page_size ),
.bank_set( bank_set ),
.bank_clr( bank_clr ),
.bank_clr_all( bank_clr_all ),
.bank_open( bank_open ),
.any_bank_open( any_bank_open ),
.row_same( row_same ),
.dv( dv ),
.pack_le0( pack_le0 ),
.pack_le1( pack_le1 ),
.pack_le2( pack_le2 ),
.par_err( par_err ),
.rfr_req( rfr_req ),
.rfr_ack( rfr_ack ),
.init_req( init_req ),
.init_ack( init_ack )
);
 
mc_wb_if u6(
.clk( clk_i ),
.rst( rst_i ),
.wb_addr_i( wb_addr_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_we_i( wb_we_i ),
.wb_ack_o( wb_ack_o ),
.wb_err( wb_err_o ),
.wb_read_go( wb_read_go ),
.wb_write_go( wb_write_go ),
.wb_first( wb_first ),
.wb_wait( wb_wait ),
.mem_ack( mem_ack ),
.wr_hold( wr_hold ),
.err( err ),
.par_err( par_err ),
.wp_err( wp_err ),
.wb_data_o( wb_data_o ),
.mem_dout( mem_dout ),
.rf_dout( rf_dout )
);
 
mc_mem_if u7(
.clk( clk_i ),
.rst( rst_i ),
.mc_rp( mc_rp_pad_o_ ),
.mc_clk( mc_clk_i ),
.mc_br( mc_br_pad_i ),
.mc_bg( mc_bg_pad_o ),
.mc_addr( mc_addr_pad_o ),
.mc_data_o( mc_data_pad_o ),
.mc_dp_o( mc_dp_pad_o ),
.mc_data_oe( mc_doe_pad_doe_o),
.mc_dqm( mc_dqm_pad_o ),
.mc_oe_( mc_oe_pad_o_ ),
.mc_we_( mc_we_pad_o_ ),
.mc_cas_( mc_cas_pad_o_ ),
.mc_ras_( mc_ras_pad_o_ ),
.mc_cke_( mc_cke_pad_o_ ),
.mc_cs_( mc_cs_pad_o_ ),
.mc_adsc_( mc_adsc_pad_o_ ),
.mc_adv_( mc_adv_pad_o_ ),
.mc_br_r( mc_br_r ),
.mc_bg_d( mc_bg_d ),
.mc_data_od( mc_data_od ),
.mc_dp_od( mc_dp_od ),
.mc_addr_d( mc_addr_d ),
.mc_ack( mc_ack_pad_i ),
.mc_zz_o( mc_zz_pad_o ),
.we_( we_ ),
.ras_( ras_ ),
.cas_( cas_ ),
.cke_( cke_ ),
.mc_adsc_d( mc_adsc_d ),
.mc_adv_d( mc_adv_d ),
.cs_en( cs_en ),
.rfr_ack( rfr_ack ),
.cs_need_rfr( cs_need_rfr ),
.lmr_sel( lmr_sel ),
.spec_req_cs( spec_req_cs ),
.cs( cs ),
.fs( fs ),
.data_oe( data_oe ),
.susp_sel( susp_sel ),
.suspended_o( suspended_o ),
.mc_c_oe( mc_coe_pad_coe_o),
.mc_c_oe_d( mc_c_oe_d ),
.mc_ack_r( mc_ack_r ),
.oe_( oe_ ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_sel_i( wb_sel_i ),
.wb_cycle( wb_cycle ),
.wr_cycle( wr_cycle ),
.mc_data_i( mc_data_pad_i ),
.mc_dp_i( mc_dp_pad_i ),
.mc_data_ir( mc_data_ir ),
.mc_sts_i( mc_sts_pad_i ),
.mc_sts_ir( mc_sts_ir )
);
 
endmodule
/verilog/minsoc/mc/mc_dp.v
0,0 → 1,244
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Data Path Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_dp.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_dp.v,v $
// Revision 1.6 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:47 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_dp( clk, rst, csc,
wb_cyc_i, wb_stb_i, wb_ack_o, mem_ack, wb_data_i, wb_data_o,
wb_read_go, wb_we_i,
mc_clk, mc_data_del, mc_dp_i, mc_data_o, mc_dp_o,
 
dv, pack_le0, pack_le1, pack_le2,
byte_en, par_err
);
 
input clk, rst;
input [31:0] csc;
 
input wb_cyc_i;
input wb_stb_i;
input mem_ack;
input wb_ack_o;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input wb_read_go;
input wb_we_i;
 
input mc_clk;
input [35:0] mc_data_del;
input [3:0] mc_dp_i;
output [31:0] mc_data_o;
output [3:0] mc_dp_o;
 
input dv;
input pack_le0, pack_le1, pack_le2; // Pack Latch Enable
input [3:0] byte_en; // High Active byte enables
output par_err;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg [31:0] wb_data_o;
reg [31:0] mc_data_o;
wire [35:0] rd_fifo_out;
wire rd_fifo_clr;
reg [3:0] mc_dp_o;
reg par_err_r;
 
reg [7:0] byte0, byte1, byte2;
reg [31:0] mc_data_d;
 
wire [2:0] mem_type;
wire [1:0] bus_width;
wire pen;
wire re;
 
// Aliases
assign mem_type = csc[3:1];
assign bus_width = csc[5:4];
assign pen = csc[11];
 
////////////////////////////////////////////////////////////////////
//
// WB READ Data Path
//
 
always @(mem_type or rd_fifo_out or mc_data_d)
if( (mem_type == `MC_MEM_TYPE_SDRAM) |
(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0];
else wb_data_o = mc_data_d;
 
//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) );
assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i);
assign re = wb_ack_o & wb_read_go;
 
mc_rd_fifo u0(
.clk( clk ),
.rst( rst ),
.clr( rd_fifo_clr ),
.din( mc_data_del ),
.we( dv ),
.dout( rd_fifo_out ),
.re( re )
);
 
////////////////////////////////////////////////////////////////////
//
// WB WRITE Data Path
//
 
always @(posedge clk)
if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
mc_data_o <= #1 wb_data_i;
 
////////////////////////////////////////////////////////////////////
//
// Read Data Packing
//
 
always @(posedge clk)
if(pack_le0) byte0 <= #1 mc_data_del[7:0];
 
always @(posedge clk)
if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_del[7:0];
else
if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_del[15:8];
 
always @(posedge clk)
if(pack_le2) byte2 <= #1 mc_data_del[7:0];
 
always @(bus_width or mc_data_del or byte0 or byte1 or byte2)
if(bus_width == `MC_BW_8) mc_data_d = {mc_data_del[7:0], byte2, byte1, byte0};
else
if(bus_width == `MC_BW_16) mc_data_d = {mc_data_del[15:0], byte1, byte0};
else mc_data_d = mc_data_del[31:0];
 
////////////////////////////////////////////////////////////////////
//
// Parity Generation
//
 
always @(posedge clk)
if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16],
^wb_data_i[15:08], ^wb_data_i[07:00] };
 
////////////////////////////////////////////////////////////////////
//
// Parity Checking
//
 
assign par_err = !wb_we_i & mem_ack & pen & (
(( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) |
(( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) |
(( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) |
(( ^rd_fifo_out[07:00] ^ rd_fifo_out[32] ) & byte_en[0] )
);
 
endmodule
 
/verilog/minsoc/mc/mc_top_for_vhdl.v
0,0 → 1,125
/*
* Xiang Li, olivercamel@gmail.com
* Last Revised: 2008/08/01
*
* This file is created as the new top level entity of
* Memory Controller IP Core, which is nothing
* but a wrapper of mc_top with some port names changed.
* The reason of doing so is because identifiers in the
* format of "xxx_" are not supported in VHDL,
* but are valid in Verilog. So we have to use the wrapper
* to make MC can be used in higher level VHDL entities.
*/
 
module mc_top_for_vhdl(
clk_i, rst_i,
 
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
 
susp_req_i, resume_req_i, suspended_o, poc_o,
 
mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i,
mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i,
mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o,
mc_we_pad_o, mc_cas_pad_o, mc_ras_pad_o, mc_cke_pad_o,
mc_cs_pad_o, mc_sts_pad_i, mc_rp_pad_o, mc_vpen_pad_o,
mc_adsc_pad_o, mc_adv_pad_o, mc_zz_pad_o, mc_coe_pad_coe_o
);
 
input clk_i, rst_i;
 
// --------------------------------------
// WISHBONE SLAVE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
 
// --------------------------------------
// Suspend Resume Interface
input susp_req_i;
input resume_req_i;
output suspended_o;
 
// POC
output [31:0] poc_o;
 
// --------------------------------------
// Memory Bus Signals
input mc_clk_i;
input mc_br_pad_i;
output mc_bg_pad_o;
input mc_ack_pad_i;
output [23:0] mc_addr_pad_o;
input [31:0] mc_data_pad_i;
output [31:0] mc_data_pad_o;
input [3:0] mc_dp_pad_i;
output [3:0] mc_dp_pad_o;
output mc_doe_pad_doe_o;
output [3:0] mc_dqm_pad_o;
output mc_oe_pad_o;
output mc_we_pad_o;
output mc_cas_pad_o;
output mc_ras_pad_o;
output mc_cke_pad_o;
output [7:0] mc_cs_pad_o;
input mc_sts_pad_i;
output mc_rp_pad_o;
output mc_vpen_pad_o;
output mc_adsc_pad_o;
output mc_adv_pad_o;
output mc_zz_pad_o;
output mc_coe_pad_coe_o;
 
mc_top u0(
.clk_i (clk_i),
.rst_i (rst_i),
 
.wb_data_i (wb_data_i),
.wb_data_o (wb_data_o),
.wb_addr_i (wb_addr_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
 
.susp_req_i (susp_req_i),
.resume_req_i (resume_req_i),
.suspended_o (suspended_o),
.poc_o (poc_o),
 
.mc_clk_i (mc_clk_i),
.mc_br_pad_i (mc_br_pad_i),
.mc_bg_pad_o (mc_bg_pad_o),
.mc_ack_pad_i (mc_ack_pad_i),
.mc_addr_pad_o (mc_addr_pad_o),
.mc_data_pad_i (mc_data_pad_i),
.mc_data_pad_o (mc_data_pad_o),
.mc_dp_pad_i (mc_dp_pad_i),
.mc_dp_pad_o (mc_dp_pad_o),
.mc_doe_pad_doe_o (mc_doe_pad_doe_o),
.mc_dqm_pad_o (mc_dqm_pad_o),
.mc_oe_pad_o_ (mc_oe_pad_o),
.mc_we_pad_o_ (mc_we_pad_o),
.mc_cas_pad_o_ (mc_cas_pad_o),
.mc_ras_pad_o_ (mc_ras_pad_o),
.mc_cke_pad_o_ (mc_cke_pad_o),
.mc_cs_pad_o_ (mc_cs_pad_o),
.mc_sts_pad_i (mc_sts_pad_i),
.mc_rp_pad_o_ (mc_rp_pad_o),
.mc_vpen_pad_o (mc_vpen_pad_o),
.mc_adsc_pad_o_ (mc_adsc_pad_o),
.mc_adv_pad_o_ (mc_adv_pad_o),
.mc_zz_pad_o (mc_zz_pad_o),
.mc_coe_pad_coe_o (mc_coe_pad_coe_o)
);
 
endmodule
/verilog/minsoc/mc/mc_wb_if.v
0,0 → 1,252
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// WISHBONE Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_wb_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_wb_if.v,v $
// Revision 1.6 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug
// fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:47 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_wb_if(clk, rst,
wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
wb_read_go, wb_write_go,
wb_first, wb_wait, mem_ack, wr_hold,
err, par_err, wp_err,
wb_data_o, mem_dout, rf_dout);
 
input clk, rst;
input [31:0] wb_addr_i;
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
output wb_err;
output wb_ack_o;
output wb_read_go;
output wb_write_go;
output wb_first;
output wb_wait;
input mem_ack;
output wr_hold;
input err, par_err, wp_err;
output [31:0] wb_data_o;
input [31:0] mem_dout, rf_dout;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
wire mem_sel;
reg read_go_r;
reg read_go_r1;
reg write_go_r;
reg write_go_r1;
reg wb_first_r;
wire wb_first_set;
reg wr_hold;
wire rmw;
reg rmw_r;
reg rmw_en;
reg wb_ack_o;
reg wb_err;
reg [31:0] wb_data_o;
 
////////////////////////////////////////////////////////////////////
//
// Memory Go Logic
//
 
assign mem_sel = `MC_MEM_SEL;
 
always @(posedge clk or posedge rst)
if(rst) rmw_en <= #1 1'b0;
else
if(wb_ack_o) rmw_en <= #1 1'b1;
else
if(!wb_cyc_i) rmw_en <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) rmw_r <= #1 1'b0;
else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
 
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
 
always @(posedge clk or posedge rst)
if(rst) read_go_r1 <= #1 1'b0;
else read_go_r1 <= #1 !rmw & wb_cyc_i &
((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
 
always @(posedge clk or posedge rst)
if(rst) read_go_r <= #1 1'b0;
else read_go_r <= #1 read_go_r1 & wb_cyc_i;
 
assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
 
always @(posedge clk or posedge rst)
if(rst) write_go_r1 <= #1 1'b0;
else write_go_r1 <= #1 wb_cyc_i &
((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
 
always @(posedge clk or posedge rst)
if(rst) write_go_r <= #1 1'b0;
else write_go_r <= #1 write_go_r1 & wb_cyc_i &
((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
 
always @(posedge clk or posedge rst)
if(rst) wb_first_r <= #1 1'b0;
else
if(wb_first_set) wb_first_r <= #1 1'b1;
else
if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) wr_hold <= #1 1'b0;
else
if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
 
////////////////////////////////////////////////////////////////////
//
// WB Ack
//
 
wire wb_err_d;
 
// Ack no longer asserted when wb_err is asserted
always @(posedge clk or posedge rst)
if(rst) wb_ack_o <= #1 1'b0;
else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err);
 
always @(posedge clk or posedge rst)
if(rst) wb_err <= #1 1'b0;
else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
 
////////////////////////////////////////////////////////////////////
//
// Memory Wait Logic
//
 
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Data Output
//
 
always @(posedge clk)
wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
 
endmodule
/verilog/minsoc/mc/mc_timing.v
0,0 → 1,1735
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller Main Timing Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_timing.v,v 1.8 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.8 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_timing.v,v $
// Revision 1.8 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.7 2001/12/21 05:09:30 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.6 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.5 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.4 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.3 2001/09/02 02:28:28 rudi
//
// Many fixes for minor bugs that showed up in gate level simulations.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.4 2001/06/14 01:57:37 rudi
//
//
// Fixed a potential bug in a corner case situation where the TMS register
// does not propegate properly during initialisation.
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:44 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_timing(clk, rst,
 
// Wishbone Interface
wb_cyc_i, wb_stb_i, wb_we_i,
wb_read_go, wb_write_go, wb_first, wb_wait, mem_ack,
err,
 
// Suspend/Resume Interface
susp_req, resume_req, suspended, susp_sel,
 
// Memory Interface
mc_clk, data_oe, oe_, we_, cas_, ras_, cke_,
cs_en, wb_cycle, wr_cycle,
mc_br, mc_bg, mc_adsc, mc_adv,
mc_c_oe, mc_ack,
not_mem_cyc,
 
// Register File Interface
csc, tms, cs, lmr_req, lmr_ack, cs_le_d, cs_le,
 
// Address Select Signals
cmd_a10, row_sel, next_adr, page_size,
 
// OBCT Signals
bank_set, bank_clr, bank_clr_all, bank_open, any_bank_open, row_same,
 
// Data path Controller Signals
dv, pack_le0, pack_le1, pack_le2, par_err,
 
// Refresh Counter Signals
rfr_req, rfr_ack,
 
// Initialize Request & Ack
init_req, init_ack
);
 
input clk;
input rst;
 
// Wishbone Interface
input wb_cyc_i, wb_stb_i, wb_we_i;
input wb_read_go;
input wb_write_go;
input wb_first;
input wb_wait;
output mem_ack;
output err;
 
// Suspend/Resume Interface
input susp_req;
input resume_req;
output suspended;
output susp_sel;
 
// Memory Interface
input mc_clk;
output data_oe;
output oe_;
output we_;
output cas_;
output ras_;
output cke_;
output cs_en;
output wb_cycle;
output wr_cycle;
input mc_br;
output mc_bg;
output mc_adsc;
output mc_adv;
output mc_c_oe;
input mc_ack;
input not_mem_cyc;
 
// Register File Interface
input [31:0] csc;
input [31:0] tms;
input [7:0] cs;
input lmr_req;
output lmr_ack;
output cs_le;
output cs_le_d;
 
// Address Select Signals
input [10:0] page_size;
output cmd_a10;
output row_sel;
output next_adr;
 
// OBCT Signals
output bank_set;
output bank_clr;
output bank_clr_all;
input bank_open;
input any_bank_open;
input row_same;
 
// Data path Controller Signals
output dv;
output pack_le0, pack_le1, pack_le2; // Pack Latch Enable
input par_err;
 
// Refresh Counter Signals
input rfr_req;
output rfr_ack;
 
// Initialize Request & Ack
input init_req;
output init_ack;
 
////////////////////////////////////////////////////////////////////
//
// Defines & Parameters
//
 
// Number of states: 66
parameter [65:0] // synopsys enum state
// 6666666555555555544444444443333333333222222222211111111110000000000
// 6543210987654321098765432109876543210987654321098765432109876543210
POR = 66'b000000000000000000000000000000000000000000000000000000000000000001,
IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010,
IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100,
IDLE_T2 = 66'b000000000000000000000000000000000000000000000000000000000000001000,
PRECHARGE = 66'b000000000000000000000000000000000000000000000000000000000000010000,
PRECHARGE_W = 66'b000000000000000000000000000000000000000000000000000000000000100000,
ACTIVATE = 66'b000000000000000000000000000000000000000000000000000000000001000000,
ACTIVATE_W = 66'b000000000000000000000000000000000000000000000000000000000010000000,
SD_RD_WR = 66'b000000000000000000000000000000000000000000000000000000000100000000,
SD_RD = 66'b000000000000000000000000000000000000000000000000000000001000000000,
SD_RD_W = 66'b000000000000000000000000000000000000000000000000000000010000000000,
SD_RD_LOOP = 66'b000000000000000000000000000000000000000000000000000000100000000000,
SD_RD_W2 = 66'b000000000000000000000000000000000000000000000000000001000000000000,
SD_WR = 66'b000000000000000000000000000000000000000000000000000010000000000000,
SD_WR_W = 66'b000000000000000000000000000000000000000000000000000100000000000000,
BT = 66'b000000000000000000000000000000000000000000000000001000000000000000,
BT_W = 66'b000000000000000000000000000000000000000000000000010000000000000000,
REFR = 66'b000000000000000000000000000000000000000000000000100000000000000000,
LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000,
LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000,
LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000,
// 6666666555555555544444444443333333333222222222211111111110000000000
// 6543210987654321098765432109876543210987654321098765432109876543210
INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000,
INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000,
INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000,
INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000,
INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000,
// 6666666555555555544444444443333333333222222222211111111110000000000
// 6543210987654321098765432109876543210987654321098765432109876543210
INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000,
SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000,
SUSP2 = 66'b000000000000000000000000000000000000010000000000000000000000000000,
SUSP3 = 66'b000000000000000000000000000000000000100000000000000000000000000000,
SUSP4 = 66'b000000000000000000000000000000000001000000000000000000000000000000,
RESUME1 = 66'b000000000000000000000000000000000010000000000000000000000000000000,
RESUME2 = 66'b000000000000000000000000000000000100000000000000000000000000000000,
BG0 = 66'b000000000000000000000000000000001000000000000000000000000000000000,
BG1 = 66'b000000000000000000000000000000010000000000000000000000000000000000,
BG2 = 66'b000000000000000000000000000000100000000000000000000000000000000000,
ACS_RD = 66'b000000000000000000000000000001000000000000000000000000000000000000,
ACS_RD1 = 66'b000000000000000000000000000010000000000000000000000000000000000000,
ACS_RD2A = 66'b000000000000000000000000000100000000000000000000000000000000000000,
ACS_RD2 = 66'b000000000000000000000000001000000000000000000000000000000000000000,
ACS_RD3 = 66'b000000000000000000000000010000000000000000000000000000000000000000,
ACS_RD_8_1 = 66'b000000000000000000000000100000000000000000000000000000000000000000,
ACS_RD_8_2 = 66'b000000000000000000000001000000000000000000000000000000000000000000,
ACS_RD_8_3 = 66'b000000000000000000000010000000000000000000000000000000000000000000,
ACS_RD_8_4 = 66'b000000000000000000000100000000000000000000000000000000000000000000,
ACS_RD_8_5 = 66'b000000000000000000001000000000000000000000000000000000000000000000,
ACS_RD_8_6 = 66'b000000000000000000010000000000000000000000000000000000000000000000,
ACS_WR = 66'b000000000000000000100000000000000000000000000000000000000000000000,
ACS_WR1 = 66'b000000000000000001000000000000000000000000000000000000000000000000,
ACS_WR2 = 66'b000000000000000010000000000000000000000000000000000000000000000000,
ACS_WR3 = 66'b000000000000000100000000000000000000000000000000000000000000000000,
ACS_WR4 = 66'b000000000000001000000000000000000000000000000000000000000000000000,
SRAM_RD = 66'b000000000000010000000000000000000000000000000000000000000000000000,
SRAM_RD0 = 66'b000000000000100000000000000000000000000000000000000000000000000000,
SRAM_RD1 = 66'b000000000001000000000000000000000000000000000000000000000000000000,
SRAM_RD2 = 66'b000000000010000000000000000000000000000000000000000000000000000000,
SRAM_RD3 = 66'b000000000100000000000000000000000000000000000000000000000000000000,
SRAM_RD4 = 66'b000000001000000000000000000000000000000000000000000000000000000000,
SRAM_WR = 66'b000000010000000000000000000000000000000000000000000000000000000000,
SRAM_WR0 = 66'b000000100000000000000000000000000000000000000000000000000000000000,
SCS_RD = 66'b000001000000000000000000000000000000000000000000000000000000000000,
SCS_RD1 = 66'b000010000000000000000000000000000000000000000000000000000000000000,
SCS_RD2 = 66'b000100000000000000000000000000000000000000000000000000000000000000,
SCS_WR = 66'b001000000000000000000000000000000000000000000000000000000000000000,
SCS_WR1 = 66'b010000000000000000000000000000000000000000000000000000000000000000,
SCS_ERR = 66'b100000000000000000000000000000000000000000000000000000000000000000;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg [65:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
 
reg mc_bg;
 
wire [2:0] mem_type;
wire [1:0] bus_width;
wire kro;
 
wire cs_a;
reg [3:0] cmd;
 
wire mem_ack;
wire mem_ack_s;
reg mem_ack_d;
reg err_d;
wire err;
reg cmd_a10;
reg lmr_ack;
reg lmr_ack_d;
reg row_sel;
reg oe_;
reg oe_d;
reg data_oe;
reg data_oe_d;
reg cke_d;
reg cke_;
reg init_ack;
reg dv;
reg rfr_ack_d;
reg mc_adsc;
reg mc_adv;
 
reg bank_set;
reg bank_clr;
reg bank_clr_all;
 
reg wr_set, wr_clr;
reg wr_cycle;
 
reg cmd_asserted;
reg cmd_asserted2;
 
reg [10:0] burst_val;
reg [10:0] burst_cnt;
wire burst_act;
reg burst_act_rd;
wire single_write;
 
reg cs_le_d;
reg cs_le;
reg cs_le_r;
 
reg susp_req_r;
reg resume_req_r;
reg suspended;
reg suspended_d;
reg susp_sel_set, susp_sel_clr, susp_sel_r;
 
reg [3:0] cmd_del;
reg [3:0] cmd_r;
reg data_oe_r;
reg data_oe_r2;
reg cke_r;
reg cke_rd;
reg cke_o_del;
reg cke_o_r1;
reg cke_o_r2;
reg wb_cycle_set, wb_cycle;
reg [3:0] ack_cnt;
wire ack_cnt_is_0;
reg cnt, cnt_next;
reg [7:0] timer;
reg tmr_ld_trp, tmr_ld_trcd, tmr_ld_tcl, tmr_ld_trfc;
reg tmr_ld_twr, tmr_ld_txsr;
reg tmr2_ld_tscsto;
reg tmr_ld_trdv;
reg tmr_ld_trdz;
reg tmr_ld_twr2;
wire timer_is_zero;
reg tmr_done;
reg tmr2_ld_trdv, tmr2_ld_trdz;
reg tmr2_ld_twpw, tmr2_ld_twd, tmr2_ld_twwd;
reg tmr2_ld_tsrdv;
reg [8:0] timer2;
reg tmr2_done;
wire timer2_is_zero;
reg [3:0] ir_cnt;
reg ir_cnt_ld;
reg ir_cnt_dec;
reg ir_cnt_done;
reg rfr_ack_r;
reg burst_cnt_ld;
reg burst_fp;
reg wb_wait_r, wb_wait_r2;
reg lookup_ready1, lookup_ready2;
reg burst_cnt_ld_4;
reg dv_r;
reg mc_adv_r1, mc_adv_r;
 
reg next_adr;
reg pack_le0, pack_le1, pack_le2;
reg pack_le0_d, pack_le1_d, pack_le2_d;
wire bw8, bw16;
 
reg mc_c_oe_d;
reg mc_c_oe;
 
reg mc_le;
reg mem_ack_r;
 
reg rsts, rsts1;
reg no_wb_cycle;
 
wire bc_dec;
reg ap_en; // Auto Precharge Enable
reg cmd_a10_r;
reg wb_stb_first;
reg tmr_ld_tavav;
 
////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign mem_type = csc[3:1];
assign bus_width = csc[5:4];
assign kro = csc[10];
assign single_write = tms[9] | (tms[2:0] == 3'h0);
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
reg cs_le_r1;
 
always @(posedge clk)
lmr_ack <= #1 lmr_ack_d;
 
assign rfr_ack = rfr_ack_r;
 
always @(posedge clk)
cs_le_r <= #1 cs_le_r1;
 
always @(posedge clk)
cs_le_r1 <= #1 cs_le;
 
always @(posedge clk)
cs_le <= #1 cs_le_d;
 
always @(posedge mc_clk or posedge rst)
if(rst) rsts1 <= #1 1'b1;
else rsts1 <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) rsts <= #1 1'b1;
else rsts <= #1 rsts1;
 
// Control Signals Output Enable
always @(posedge clk or posedge rst)
if(rst) mc_c_oe <= #1 1'b0;
else mc_c_oe <= #1 mc_c_oe_d;
 
always @(posedge clk or posedge rsts)
if(rsts) mc_le <= #1 1'b0;
else mc_le <= #1 ~mc_le;
 
always @(posedge clk)
pack_le0 <= #1 pack_le0_d;
 
always @(posedge clk)
pack_le1 <= #1 pack_le1_d;
 
always @(posedge clk)
pack_le2 <= #1 pack_le2_d;
 
always @(posedge clk or posedge rst)
if(rst) mc_adv_r1 <= #1 1'b0;
else
if(!mc_le) mc_adv_r1 <= #1 mc_adv;
 
always @(posedge clk or posedge rst)
if(rst) mc_adv_r <= #1 1'b0;
else
if(!mc_le) mc_adv_r <= #1 mc_adv_r1;
 
// Bus Width decoder
assign bw8 = (bus_width == `MC_BW_8);
assign bw16 = (bus_width == `MC_BW_16);
 
// Any Chip Select
assign cs_a = |cs;
 
// Memory to Wishbone Ack
assign mem_ack = (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go);
 
always @(posedge clk or posedge rst)
if(rst) mem_ack_r <= #1 1'b0;
else mem_ack_r <= #1 mem_ack;
 
assign err = err_d;
 
// SDRAM Command, either delayed (for writes) or straight through
always @(posedge clk or posedge rst)
if(rst) cmd_r <= #1 `MC_CMD_NOP;
else cmd_r <= #1 cmd;
 
always @(posedge clk or posedge rst)
if(rst) cmd_del <= #1 `MC_CMD_NOP;
else cmd_del <= #1 cmd_r;
 
assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd;
 
// Track Timing of Asserting a command
always @(posedge clk or posedge rst)
if(rst) cmd_asserted <= #1 1'b0;
else
if(!mc_le) cmd_asserted <= #1 cmd[3];
 
always @(posedge clk or posedge rst)
if(rst) cmd_asserted2 <= #1 1'b0;
else
if(!mc_le) cmd_asserted2 <= #1 cmd_asserted;
 
// Output Enable
always @(posedge clk or posedge rst)
if(rst) oe_ <= #1 1'b1;
else oe_ <= #1 ~oe_d;
 
// Memory Bus Data lines Output Enable
always @(posedge clk or posedge rst)
if(rst) data_oe_r <= #1 1'b0;
else data_oe_r <= #1 data_oe_d;
 
always @(posedge clk or posedge rst)
if(rst) data_oe_r2 <= #1 1'b0;
else data_oe_r2 <= #1 data_oe_r;
 
always @(posedge clk or posedge rst)
if(rst) data_oe <= #1 1'b0;
else data_oe <= #1 wr_cycle ? data_oe_r2 : data_oe_d;
 
// Clock Enable
always @(posedge clk)
cke_r <= #1 cke_d;
 
always @(posedge clk)
cke_ <= #1 cke_r & cke_rd;
 
// CKE output delay line to time DV for reads
always @(posedge clk)
cke_o_r1 <= #1 cke_;
 
always @(posedge clk)
cke_o_r2 <= #1 cke_o_r1;
 
always @(posedge clk)
cke_o_del <= #1 cke_o_r2;
 
// Delayed version of the wb_wait input
always @(posedge clk)
wb_wait_r2 <= #1 wb_wait;
 
always @(posedge clk)
wb_wait_r <= #1 wb_wait_r2;
 
// Indicates when the row_same and bank_open lookups are done
reg lookup_ready1a;
 
always @(posedge clk or posedge rst)
if(rst) lookup_ready1 <= #1 1'b0;
else lookup_ready1 <= #1 cs_le & wb_cyc_i & wb_stb_i;
 
always @(posedge clk or posedge rst)
if(rst) lookup_ready2 <= #1 1'b0;
else lookup_ready2 <= #1 lookup_ready1 & wb_cyc_i & wb_stb_i;
 
// Keep Track if it is a SDRAM write cycle
always @(posedge clk or posedge rst)
if(rst) wr_cycle <= #1 1'b0;
else
if(wr_set) wr_cycle <= #1 1'b1;
else
if(wr_clr) wr_cycle <= #1 1'b0;
 
// Track when a cycle is *still* active
always @(posedge clk or posedge rst)
if(rst) wb_cycle <= #1 1'b0;
else
if(wb_cycle_set) wb_cycle <= #1 1'b1;
else
if(!wb_cyc_i | not_mem_cyc) wb_cycle <= #1 1'b0;
 
// Thses two signals are used to signal that no wishbone cycle is in
// progress. Need to register them to avoid a very long combinatorial
// path ....
always @(posedge clk or posedge rst)
if(rst) no_wb_cycle <= #1 1'b0;
else no_wb_cycle <= #1 !wb_read_go & !wb_write_go;
 
// Track ack's for read cycles
always @(posedge clk or posedge rst)
if(rst) ack_cnt <= #1 4'h0;
else
if(no_wb_cycle) ack_cnt <= #1 4'h0;
else
if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1;
else
if(!dv & mem_ack_s) ack_cnt <= #1 ack_cnt - 4'h1;
 
assign ack_cnt_is_0 = (ack_cnt==4'h0);
 
assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack_r & wb_read_go & !(wb_we_i & wb_stb_i);
 
// Internal Cycle Tracker
always @(posedge clk)
cnt <= #1 cnt_next;
 
// Suspend/resume Logic
always @(posedge clk or posedge rst)
if(rst) susp_req_r <= #1 1'b0;
else susp_req_r <= #1 susp_req;
 
always @(posedge clk or posedge rst)
if(rst) resume_req_r <= #1 1'b0;
else resume_req_r <= #1 resume_req;
 
always @(posedge clk or posedge rst)
if(rst) suspended <= #1 1'b0;
else suspended <= #1 suspended_d;
 
always @(posedge clk or posedge rst)
if(rst) rfr_ack_r <= #1 1'b0;
else rfr_ack_r <= #1 rfr_ack_d;
 
// Suspend Select Logic
assign susp_sel = susp_sel_r;
 
always @(posedge clk or posedge rst)
if(rst) susp_sel_r <= #1 1'b0;
else
if(susp_sel_set) susp_sel_r <= #1 1'b1;
else
if(susp_sel_clr) susp_sel_r <= #1 1'b0;
 
////////////////////////////////////////////////////////////////////
//
// Timing Logic
//
wire [3:0] twrp;
wire twd_is_zero;
wire [31:0] tms_x;
 
// FIX_ME
// Hard wire worst case or make it programmable ???
assign tms_x = (rfr_ack_d | rfr_ack_r | susp_sel | !mc_c_oe) ? 32'hffff_ffff : tms;
 
always @(posedge clk)
if(tmr2_ld_tscsto) timer2 <= #1 tms_x[24:16];
else
if(tmr2_ld_tsrdv) timer2 <= #1 9'd4; // SSRAM RD->1st DATA VALID
else
if(tmr2_ld_twpw) timer2 <= #1 { 5'h0, tms_x[15:12]};
else
if(tmr2_ld_twd) timer2 <= #1 { 4'h0, tms_x[19:16],1'b0};
else
if(tmr2_ld_twwd) timer2 <= #1 { 3'h0, tms_x[25:20]};
else
if(tmr2_ld_trdz) timer2 <= #1 { 4'h0, tms_x[11:8], 1'b1};
else
if(tmr2_ld_trdv) timer2 <= #1 { tms_x[7:0], 1'b1};
else
if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1;
 
assign twd_is_zero = (tms_x[19:16] == 4'h0);
 
assign timer2_is_zero = (timer2 == 9'h0);
 
always @(posedge clk or posedge rst)
if(rst) tmr2_done <= #1 1'b0;
else tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &
!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;
 
assign twrp = {2'h0,tms_x[16:15]} + tms_x[23:20];
 
// SDRAM Memories timing tracker
always @(posedge clk or posedge rst)
`ifdef MC_POR_DELAY
if(rst) timer <= #1 `MC_POR_DELAY_VAL ;
else
`endif
if(tmr_ld_twr2) timer <= #1 { 4'h0, tms_x[15:12] };
else
if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] };
else
if(tmr_ld_trdv) timer <= #1 tms_x[7:0];
else
if(tmr_ld_twr) timer <= #1 { 4'h0, twrp};
else
if(tmr_ld_trp) timer <= #1 { 4'h0, tms_x[23:20]};
else
if(tmr_ld_trcd) timer <= #1 { 5'h0, tms_x[19:17]};
else
if(tmr_ld_tcl) timer <= #1 { 6'h0, tms_x[05:04]};
else
if(tmr_ld_trfc) timer <= #1 { 4'h0, tms_x[27:24]};
else
if(tmr_ld_tavav) timer <= #1 8'h3;
else
if(tmr_ld_txsr) timer <= #1 8'h7;
else
if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1;
 
assign timer_is_zero = (timer == 8'h0);
 
always @(posedge clk or posedge rst)
if(rst) tmr_done <= #1 1'b0;
else tmr_done <= #1 timer_is_zero;
 
// Init Refresh Cycles Counter
always @(posedge clk)
if(ir_cnt_ld) ir_cnt <= #1 `MC_INIT_RFRC_CNT;
else
if(ir_cnt_dec) ir_cnt <= #1 ir_cnt - 4'b1;
 
always @(posedge clk)
ir_cnt_done <= #1 (ir_cnt == 4'h0);
 
// Burst Counter
always @(tms_x or page_size)
case(tms_x[2:0]) // synopsys full_case parallel_case
3'h0: burst_val = 11'h1;
3'h1: burst_val = 11'h2;
3'h2: burst_val = 11'h4;
3'h3: burst_val = 11'h8;
3'h7: burst_val = page_size;
endcase
 
assign bc_dec = wr_cycle ? mem_ack_d : dv;
 
always @(posedge clk)
if(burst_cnt_ld_4) burst_cnt <= #1 11'h4; // for SSRAM only
else
if(burst_cnt_ld) burst_cnt <= #1 burst_val;
else
if(bc_dec) burst_cnt <= #1 burst_cnt - 11'h1;
 
always @(posedge clk or posedge rst)
if(rst) burst_fp <= #1 1'b0;
else
if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7);
 
// Auto Precharge Enable
always @(posedge clk or posedge rst)
if(rst) ap_en <= #1 1'b0;
else
if(burst_cnt_ld) ap_en <= #1 (tms_x[2:0] == 3'h0) & !kro;
 
assign burst_act = |burst_cnt & ( |tms_x[2:0] );
 
always @(posedge clk)
burst_act_rd <= #1 |burst_cnt;
 
always @(posedge clk or posedge rst)
if(rst) dv_r <= #1 1'b0;
else dv_r <= #1 dv;
 
always @(posedge clk) // Auto Precharge Holding Register
cmd_a10_r <= #1 cmd_a10;
 
////////////////////////////////////////////////////////////////////
//
// Main State Machine
//
reg wb_write_go_r;
 
always @(posedge clk)
wb_write_go_r <= #1 wb_write_go;
 
always @(posedge clk or posedge rst)
if(rst) wb_stb_first <= #1 1'b0;
else
if(mem_ack) wb_stb_first <= #1 1'b0;
else
if(wb_first & wb_stb_i) wb_stb_first <= #1 1'b1;
 
always @(posedge clk or posedge rst)
`ifdef MC_POR_DELAY
if(rst) state <= #1 POR;
`else
if(rst) state <= #1 IDLE;
`endif
else state <= #1 next_state;
 
always @(state or cs_a or cs_le or cs_le_r or
twd_is_zero or wb_stb_i or wb_write_go_r or
wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack_r or wb_we_i or
ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or wr_cycle or
mem_type or kro or lookup_ready2 or row_same or cmd_a10_r or
bank_open or single_write or
cmd_asserted or tmr_done or tmr2_done or ir_cnt_done or cmd_asserted2 or
burst_act or burst_act_rd or burst_fp or cke_ or cke_r or cke_o_del or
rfr_req or lmr_req or init_req or rfr_ack_r or susp_req_r or resume_req_r or
mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack or wb_stb_first or ap_en
)
begin
next_state = state; // Default keep current state
cnt_next = 1'b0;
 
cmd = `MC_CMD_NOP;
cmd_a10 = ap_en;
oe_d = 1'b0;
data_oe_d = 1'b0;
cke_d = 1'b1;
cke_rd = 1'b1;
mc_adsc = 1'b0;
mc_adv = 1'b0;
 
bank_set = 1'b0;
bank_clr = 1'b0;
bank_clr_all = 1'b0;
 
burst_cnt_ld = 1'b0;
burst_cnt_ld_4 = 1'b0;
tmr_ld_trp = 1'b0;
tmr_ld_trcd = 1'b0;
tmr_ld_tcl = 1'b0;
tmr_ld_trfc = 1'b0;
tmr_ld_twr = 1'b0;
tmr_ld_txsr = 1'b0;
tmr_ld_trdv = 1'b0;
tmr_ld_trdz = 1'b0;
tmr_ld_twr2 = 1'b0;
tmr_ld_tavav = 1'b0;
 
tmr2_ld_trdv = 1'b0;
tmr2_ld_trdz = 1'b0;
tmr2_ld_twpw = 1'b0;
tmr2_ld_twd = 1'b0;
tmr2_ld_twwd = 1'b0;
tmr2_ld_tsrdv = 1'b0;
tmr2_ld_tscsto = 1'b0;
 
mem_ack_d = 1'b0;
err_d = 1'b0;
rfr_ack_d = 1'b0;
lmr_ack_d = 1'b0;
init_ack = 1'b0;
 
ir_cnt_dec = 1'b0;
ir_cnt_ld = 1'b0;
 
row_sel = 1'b0;
cs_le_d = 1'b0;
wr_clr = 1'b0;
wr_set = 1'b0;
wb_cycle_set = 1'b0;
dv = 1'b0;
 
suspended_d = 1'b0;
susp_sel_set = 1'b0;
susp_sel_clr = 1'b0;
mc_bg = 1'b0;
 
next_adr = 1'b0;
pack_le0_d = 1'b0;
pack_le1_d = 1'b0;
pack_le2_d = 1'b0;
 
mc_c_oe_d = 1'b1;
 
case(state) // synopsys full_case parallel_case
`ifdef MC_POR_DELAY
POR:
begin
if(tmr_done) next_state = IDLE;
end
`endif
IDLE:
begin
//cs_le_d = wb_stb_first | lmr_req;
cs_le_d = wb_stb_first;
 
burst_cnt_ld = 1'b1;
wr_clr = 1'b1;
 
if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1;
if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1;
 
if(rfr_req)
begin
rfr_ack_d = 1'b1;
next_state = PRECHARGE;
end
else
if(init_req)
begin
cs_le_d = 1'b1;
next_state = INIT0;
end
else
if(lmr_req & lookup_ready2)
begin
lmr_ack_d = 1'b1;
cs_le_d = 1'b1;
next_state = LMR0;
end
else
if(susp_req_r & !wb_cycle)
begin
cs_le_d = 1'b1;
susp_sel_set = 1'b1;
next_state = SUSP1;
end
else
if(cs_a & (wb_read_go | wb_write_go) & lookup_ready2)
begin
wb_cycle_set = 1'b1;
case(mem_type) // synopsys full_case parallel_case
`MC_MEM_TYPE_SDRAM: // SDRAM
if((lookup_ready2) & !wb_wait)
begin
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
if(kro & bank_open & row_same) next_state = SD_RD_WR;
else
if(kro & bank_open) next_state = PRECHARGE;
else next_state = ACTIVATE;
end
`MC_MEM_TYPE_ACS:
begin // Async Chip Select
if(!wb_wait)
begin
cs_le_d = 1'b1;
if(wb_write_go)
begin
data_oe_d = 1'b1;
next_state = ACS_WR;
end
else next_state = ACS_RD;
end
end
`MC_MEM_TYPE_SCS:
begin // Sync Chip Select
if(!wb_wait)
begin
cs_le_d = 1'b1;
if(wb_write_go)
begin
cmd = `MC_CMD_XWR;
data_oe_d = 1'b1;
tmr_ld_twr2 = 1'b1;
next_state = SCS_WR;
end
else
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
tmr_ld_trdv = 1'b1;
next_state = SCS_RD;
end
end
end
`MC_MEM_TYPE_SRAM:
begin // SRAM
if(!wb_wait)
begin
cs_le_d = 1'b1;
if(wb_write_go)
begin
data_oe_d = 1'b1;
mem_ack_d = 1'b1;
next_state = SRAM_WR;
end
else
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
mc_adsc = 1'b1;
next_state = SRAM_RD;
end
end
end
endcase
end
else
if(mc_br)
begin
if(!cmd_asserted2)
begin
next_state = BG0;
mc_c_oe_d = 1'b0;
end
end
end
 
IDLE_T:
begin
cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes
if(tmr_done & wb_cycle & !wb_wait) cs_le_d = 1'b1;
if(tmr_done) next_state = IDLE;
end
 
IDLE_T2:
begin
if(tmr2_done & (!wb_wait | !wb_cycle) )
begin
cs_le_d = wb_cycle;
if(cs_le_r | !wb_cycle) next_state = IDLE;
end
end
 
/////////////////////////////////////////
// SCS STATES ....
/////////////////////////////////////////
SCS_RD:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
tmr_ld_trdv = 1'b1;
if(mc_ack) next_state = SCS_RD1;
else
if(tmr2_done) next_state = SCS_ERR;
end
 
SCS_RD1:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
if(tmr_done)
begin
mem_ack_d = 1'b1;
tmr_ld_trdz = 1'b1;
next_state = SCS_RD2;
end
end
 
SCS_RD2:
begin
tmr_ld_trdz = 1'b1;
next_state = IDLE_T;
end
 
SCS_WR:
begin
tmr_ld_twr2 = 1'b1;
cmd = `MC_CMD_XWR;
data_oe_d = 1'b1;
if(mc_ack) next_state = SCS_WR1;
else
if(tmr2_done) next_state = SCS_ERR;
end
 
SCS_WR1:
begin
data_oe_d = 1'b1;
if(tmr_done)
begin
mem_ack_d = 1'b1;
next_state = IDLE_T;
end
else cmd = `MC_CMD_XWR;
end
 
SCS_ERR:
begin
mem_ack_d = 1'b1;
err_d = 1'b1;
next_state = IDLE_T2;
end
 
/////////////////////////////////////////
// SSRAM STATES ....
/////////////////////////////////////////
SRAM_RD:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
mc_adsc = 1'b1;
tmr2_ld_tsrdv = 1'b1;
burst_cnt_ld_4 = 1'b1;
if(cmd_asserted) next_state = SRAM_RD0;
end
 
SRAM_RD0:
begin
mc_adv = 1'b1;
oe_d = 1'b1;
if(tmr2_done)
begin
mc_adv = !wb_wait;
next_state = SRAM_RD1;
end
end
 
SRAM_RD1:
begin
if(mc_adv_r) dv = ~dv_r;
mc_adv = !wb_wait;
 
if(!burst_act | !wb_read_go) next_state = SRAM_RD2;
else oe_d = 1'b1;
end
 
SRAM_RD2:
begin
if(ack_cnt_is_0 & wb_read_go) next_state = SRAM_RD3;
else
if(!wb_read_go)
begin
mc_adsc = 1'b1;
next_state = SRAM_RD4;
end
end
 
SRAM_RD3:
begin
if(!wb_read_go)
begin
mc_adsc = 1'b1;
next_state = SRAM_RD4;
end
else
if(!wb_wait)
begin
cs_le_d = 1'b1;
next_state = SRAM_RD;
end
end
 
SRAM_RD4: // DESELECT
begin
if(wb_cycle) cs_le_d = 1'b1; // For RMW
mc_adsc = 1'b1;
next_state = IDLE;
end
 
SRAM_WR:
begin
cmd = `MC_CMD_XWR;
mc_adsc = 1'b1;
data_oe_d = 1'b1;
if(cmd_asserted)
begin
if(wb_wait) next_state = SRAM_WR0;
else
if(!wb_write_go)
begin
mc_adsc = 1'b1;
next_state = SRAM_RD4;
end
else
begin
data_oe_d = 1'b1;
mem_ack_d = ~mem_ack_r;
end
end
end
 
SRAM_WR0:
begin
if(wb_wait) next_state = SRAM_WR0;
else
if(!wb_write_go)
begin
mc_adsc = 1'b1;
next_state = SRAM_RD4;
end
else
begin
data_oe_d = 1'b1;
next_state = SRAM_WR;
end
end
 
/////////////////////////////////////////
// Async Devices STATES ....
/////////////////////////////////////////
ACS_RD:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
tmr2_ld_trdv = 1'b1;
next_state = ACS_RD1;
end
 
ACS_RD1:
begin // 32 bit, 8 bit - first; 16 bit - first
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
if(tmr2_done)
begin
if(bw8 | bw16) next_adr = 1'b1;
if(bw8) next_state = ACS_RD_8_1;
else
if(bw16) next_state = ACS_RD_8_5;
else next_state = ACS_RD2A;
end
end
 
ACS_RD_8_1:
begin // 8 bit 2nd byte
pack_le0_d = 1'b1;
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
tmr2_ld_trdv = 1'b1;
next_state = ACS_RD_8_2;
end
 
ACS_RD_8_2:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
if(tmr2_done)
begin
next_adr = 1'b1;
next_state = ACS_RD_8_3;
end
end
 
ACS_RD_8_3:
begin // 8 bit 3rd byte
pack_le1_d = 1'b1;
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
tmr2_ld_trdv = 1'b1;
next_state = ACS_RD_8_4;
end
 
ACS_RD_8_4:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
if(tmr2_done)
begin
next_adr = 1'b1;
next_state = ACS_RD_8_5;
end
end
 
ACS_RD_8_5:
begin // 8 bit 4th byte; 16 bit 2nd word
if(bw8) pack_le2_d = 1'b1;
if(bw16) pack_le0_d = 1'b1;
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
tmr2_ld_trdv = 1'b1;
next_state = ACS_RD_8_6;
end
 
ACS_RD_8_6:
begin
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
if(tmr2_done)
begin
next_state = ACS_RD2;
end
end
 
ACS_RD2A:
begin
oe_d = 1'b1;
cmd = `MC_CMD_XRD;
next_state = ACS_RD2;
end
 
ACS_RD2:
begin
cmd = `MC_CMD_XRD;
next_state = ACS_RD3;
end
 
ACS_RD3:
begin
mem_ack_d = 1'b1;
tmr2_ld_trdz = 1'b1;
next_state = IDLE_T2;
end
 
ACS_WR:
begin
tmr2_ld_twpw = 1'b1;
cmd = `MC_CMD_XWR;
data_oe_d = 1'b1;
next_state = ACS_WR1;
end
 
ACS_WR1:
begin
if(!cmd_asserted) tmr2_ld_twpw = 1'b1;
cmd = `MC_CMD_XWR;
data_oe_d = 1'b1;
if(tmr2_done)
begin
tmr2_ld_twd = 1'b1;
next_state = ACS_WR2;
end
end
 
ACS_WR2:
begin
if(twd_is_zero) next_state = ACS_WR3;
else
begin
cmd = `MC_CMD_XRD;
data_oe_d = 1'b1;
next_state = ACS_WR3;
end
end
 
ACS_WR3:
begin
if(tmr2_done) next_state = ACS_WR4;
else cmd = `MC_CMD_XRD;
end
 
ACS_WR4:
begin
tmr2_ld_twwd = 1'b1;
mem_ack_d = 1'b1;
next_state = IDLE_T2;
end
 
/////////////////////////////////////////
// SDRAM STATES ....
/////////////////////////////////////////
 
PRECHARGE:
begin
cmd = `MC_CMD_PC;
if(rfr_ack_r)
begin
rfr_ack_d = 1'b1;
cmd_a10 = `MC_ALL_BANKS;
bank_clr_all = 1'b1;
end
else
begin
bank_clr = 1'b1;
cmd_a10 = `MC_SINGLE_BANK;
end
tmr_ld_trp = 1'b1;
if(cmd_asserted) next_state = PRECHARGE_W;
end
 
PRECHARGE_W:
begin
rfr_ack_d = rfr_ack_r;
if(tmr_done)
begin
if(rfr_ack_r) next_state = REFR;
else next_state = ACTIVATE;
end
end
 
ACTIVATE:
begin
if(!wb_wait_r)
begin
row_sel = 1'b1;
tmr_ld_trcd = 1'b1;
cmd = `MC_CMD_ACT;
end
if(cmd_asserted) next_state = ACTIVATE_W;
end
 
ACTIVATE_W:
begin
row_sel = 1'b1;
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
 
if(kro) bank_set = 1'b1;
 
if(tmr_done)
begin
if(wb_write_go)
begin
mem_ack_d = ~mem_ack_r;
cmd_a10 = ap_en | (single_write & !kro);
next_state = SD_WR;
end
else
if(!wb_wait_r) next_state = SD_RD;
end
end
 
SD_RD_WR:
begin
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
 
if(wb_write_go & !wb_wait)
begin // Write
data_oe_d = 1'b1;
mem_ack_d = ~mem_ack_r;
cmd_a10 = ap_en | (single_write & !kro);
next_state = SD_WR;
end
else
if(!wb_wait)
begin // Read
if(kro)
begin
if(!wb_wait_r) next_state = SD_RD;
end
else next_state = SD_RD;
end
end
 
SD_WR: // Write Command
begin // Does the first single write
data_oe_d = 1'b1;
tmr_ld_twr = 1'b1;
cnt_next = ~cnt;
cmd = `MC_CMD_WR;
 
cmd_a10 = ap_en | (single_write & !kro);
 
if(!cnt & wb_cycle & burst_act) cke_d = ~wb_wait;
else cke_d = cke_r;
 
if(cmd_asserted)
begin
mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wb_cycle & burst_act;
 
if(wb_cycle & !burst_act) next_state = IDLE_T;
else
if(wb_write_go) next_state = SD_WR_W;
else
if(burst_act & !single_write) next_state = BT;
else
if(!ap_en) next_state = BT_W;
else next_state = IDLE_T;
end
 
end
 
SD_WR_W:
begin // Does additional Writes or Times them
tmr_ld_twr = 1'b1;
cnt_next = ~cnt;
 
if(single_write & wb_cycle)
begin
cmd = `MC_CMD_WR;
end
cmd_a10 = ap_en | (single_write & !kro);
 
data_oe_d = 1'b1;
mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wr_cycle & burst_act;
 
if(!cnt) cke_d = ~wb_wait;
else cke_d = cke_r;
 
if( (single_write & cke_r) | (!single_write & !cnt & !wb_wait) | (!single_write & cnt & cke_r) )
begin
if(single_write & !wb_cycle) next_state = IDLE_T;
else
if(burst_act & !single_write & !wb_write_go_r)
begin
cmd = `MC_CMD_BT;
next_state = BT;
end
else
if(!burst_act & !ap_en) next_state = BT_W;
else
if(!burst_act) next_state = IDLE_T;
else
if(!wb_write_go_r & wb_read_go) next_state = IDLE_T; // Added for WMR
end
end
 
SD_RD: // Read Command
begin
cmd = `MC_CMD_RD;
cmd_a10 = ap_en;
tmr_ld_tcl = 1'b1;
if(cmd_asserted) next_state = SD_RD_W;
end
 
SD_RD_W:
begin
if(tmr_done) next_state = SD_RD_LOOP;
end
 
SD_RD_LOOP:
begin
cnt_next = ~cnt;
 
if(cnt & !(burst_act & !wb_cycle) & burst_act ) cke_rd = !wb_wait;
else cke_rd = cke_;
 
if(wb_cycle & !cnt & burst_act_rd & cke_o_del) dv = 1'b1;
 
if(wb_cycle & wb_write_go) next_state = BT;
else
if(burst_act & !wb_cycle) next_state = BT;
else
if(!burst_act) next_state = SD_RD_W2;
end
 
SD_RD_W2:
begin
if(wb_write_go | ack_cnt_is_0)
begin
if(!ap_en & !kro) next_state = BT_W;
else
if(!wb_wait & !mem_ack_r) next_state = IDLE_T;
end
end
 
BT:
begin
cmd = `MC_CMD_BT;
tmr_ld_trp = 1'b1;
if(cmd_asserted) next_state = BT_W;
end
 
BT_W:
begin
cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes
 
if(kro & tmr_done)
begin
if(kro & !wb_wait & (wb_read_go | wb_write_go) ) cs_le_d = 1'b1;
next_state = IDLE;
end
else
if(!kro & tmr_done) // Must do a PRECHARGE after Burst Terminate
begin
bank_clr = 1'b1;
cmd = `MC_CMD_PC;
cmd_a10 = `MC_SINGLE_BANK;
tmr_ld_trp = 1'b1;
if(cmd_asserted) next_state = IDLE_T;
end
end
 
REFR: // Refresh Cycle
begin
cs_le_d = 1'b1;
cmd = `MC_CMD_ARFR;
tmr_ld_trfc = 1'b1;
rfr_ack_d = 1'b1;
if(cmd_asserted)
begin
susp_sel_clr = 1'b1;
next_state = IDLE_T;
end
end
 
LMR0:
begin
lmr_ack_d = 1'b1;
cmd = `MC_CMD_PC;
cmd_a10 = `MC_ALL_BANKS;
bank_clr_all = 1'b1;
tmr_ld_trp = 1'b1;
if(cmd_asserted) next_state = LMR1;
end
 
LMR1:
begin
lmr_ack_d = 1'b1;
if(tmr_done) next_state = LMR2;
end
 
LMR2:
begin
bank_clr_all = 1'b1;
cmd = `MC_CMD_LMR;
tmr_ld_trfc = 1'b1;
lmr_ack_d = 1'b1;
if(cmd_asserted) next_state = IDLE_T;
end
 
INIT0:
begin
cs_le_d = 1'b1;
next_state = INIT;
end
 
INIT: // Initialize SDRAMS
begin // PRECHARGE
init_ack = 1'b1;
cmd = `MC_CMD_PC;
cmd_a10 = `MC_ALL_BANKS;
bank_clr_all = 1'b1;
tmr_ld_trp = 1'b1;
ir_cnt_ld = 1'b1;
if(cmd_asserted) next_state = INIT_W;
end
 
INIT_W:
begin
init_ack = 1'b1;
if(tmr_done) next_state = INIT_REFR1;
end
 
INIT_REFR1: // Init Refresh Cycle 1
begin
init_ack = 1'b1;
cmd = `MC_CMD_ARFR;
tmr_ld_trfc = 1'b1;
if(cmd_asserted)
begin
ir_cnt_dec = 1'b1;
next_state = INIT_REFR1_W;
end
end
 
INIT_REFR1_W:
begin
init_ack = 1'b1;
if(tmr_done)
begin
if(ir_cnt_done) next_state = INIT_LMR;
else next_state = INIT_REFR1;
end
end
 
INIT_LMR:
begin
init_ack = 1'b1;
cmd = `MC_CMD_LMR;
bank_clr_all = 1'b1;
tmr_ld_trfc = 1'b1;
if(cmd_asserted) next_state = IDLE_T;
end
 
/////////////////////////////////////////
// Bus Arbitration STATES ....
/////////////////////////////////////////
BG0:
begin // Bus Grant
mc_bg = 1'b1;
mc_c_oe_d = 1'b0;
next_state = BG1;
end
BG1:
begin // Bus Grant
mc_bg = 1'b1;
cs_le_d = 1'b1;
mc_c_oe_d = 1'b0;
next_state = BG2;
end
BG2:
begin // Bus Grant
cs_le_d = 1'b1;
mc_bg = !wb_read_go & !wb_write_go &
!rfr_req & !init_req & !lmr_req &
!susp_req_r;
tmr_ld_tavav = 1'b1;
mc_c_oe_d = mc_br;
if(!mc_br) next_state = IDLE_T;
end
 
/////////////////////////////////////////
// SUSPEND/RESUME STATES ....
/////////////////////////////////////////
SUSP1:
begin // Precharge All
cmd = `MC_CMD_PC;
cmd_a10 = `MC_ALL_BANKS;
bank_clr_all = 1'b1;
tmr_ld_trp = 1'b1;
if(cmd_asserted) next_state = SUSP2;
end
 
SUSP2:
begin
if(tmr_done) next_state = SUSP3;
end
 
SUSP3:
begin // Enter Self refresh Mode
cke_d = 1'b0;
cmd = `MC_CMD_ARFR;
rfr_ack_d = 1'b1;
if(cmd_asserted)
begin
next_state = SUSP4;
end
end
 
SUSP4:
begin // Now we are suspended
cke_rd = 1'b0;
suspended_d = 1'b1;
tmr_ld_txsr = 1'b1;
if(resume_req_r) next_state = RESUME1;
end
 
RESUME1:
begin
suspended_d = 1'b1;
tmr_ld_txsr = 1'b1;
next_state = RESUME2;
end
 
RESUME2:
begin
suspended_d = 1'b1;
if(tmr_done) next_state = REFR;
end
 
// synopsys translate_off
default:
$display("MC_TIMING SM: Entered non existing state ... (%t)",$time);
// synopsys translate_on
 
endcase
end
 
endmodule
/verilog/minsoc/mc/mc_rf.v
0,0 → 1,836
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller Register File ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_rf.v,v 1.8 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.8 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_rf.v,v $
// Revision 1.8 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.7 2001/12/21 05:09:29 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.6 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.5 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.4 2001/10/04 03:19:37 rudi
//
// Fixed Register reads
// Tightened up timing for register rd/wr
//
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:42 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_rf(clk, rst,
 
wb_data_i, rf_dout, wb_addr_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wp_err,
 
csc, tms, poc,
sp_csc, sp_tms, cs,
mc_data_i, mc_sts, mc_vpen, fs,
 
cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,
init_ack, lmr_req, lmr_ack,
spec_req_cs
);
 
input clk, rst;
 
// --------------------------------------
// WISHBONE INTERFACE
 
// Slave Interface
input [31:0] wb_data_i;
output [31:0] rf_dout;
input [31:0] wb_addr_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wp_err;
 
// --------------------------------------
// Misc Signals
output [31:0] csc;
output [31:0] tms;
output [31:0] poc;
output [31:0] sp_csc;
output [31:0] sp_tms;
output [7:0] cs;
 
input [31:0] mc_data_i;
input mc_sts;
output mc_vpen;
output fs;
 
input cs_le_d;
input cs_le;
 
output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM
// attached and need to be refreshed
output [2:0] ref_int; // Refresh Interval
output [7:0] rfr_ps_val;
 
output init_req;
input init_ack;
output lmr_req;
input lmr_ack;
 
output [7:0] spec_req_cs;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg wb_ack_o;
 
reg [31:0] csc;
reg [31:0] tms;
reg [31:0] sp_csc;
reg [31:0] sp_tms;
reg [31:0] rf_dout;
reg [7:0] cs;
 
reg rf_we;
wire [31:0] csr;
reg [10:0] csr_r;
reg [7:0] csr_r2;
reg [31:0] poc;
 
wire [31:0] csc_mask;
reg [10:0] csc_mask_r;
 
wire [31:0] csc0, tms0;
wire [31:0] csc1, tms1;
wire [31:0] csc2, tms2;
wire [31:0] csc3, tms3;
wire [31:0] csc4, tms4;
wire [31:0] csc5, tms5;
wire [31:0] csc6, tms6;
wire [31:0] csc7, tms7;
 
wire cs0, cs1, cs2, cs3;
wire cs4, cs5, cs6, cs7;
wire wp_err0, wp_err1, wp_err2, wp_err3;
wire wp_err4, wp_err5, wp_err6, wp_err7;
reg wp_err;
 
wire lmr_req7, lmr_req6, lmr_req5, lmr_req4;
wire lmr_req3, lmr_req2, lmr_req1, lmr_req0;
wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4;
wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0;
 
wire init_req7, init_req6, init_req5, init_req4;
wire init_req3, init_req2, init_req1, init_req0;
wire init_ack7, init_ack6, init_ack5, init_ack4;
wire init_ack3, init_ack2, init_ack1, init_ack0;
 
reg init_ack_r;
wire init_ack_fe;
reg lmr_ack_r;
wire lmr_ack_fe;
wire [7:0] spec_req_cs_t;
wire [7:0] spec_req_cs_d;
reg [7:0] spec_req_cs;
reg init_req, lmr_req;
reg sreq_cs_le;
 
// Aliases
assign csr = {csr_r2, 8'h0, 5'h0, csr_r};
assign csc_mask = {21'h0, csc_mask_r};
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Register Read logic
//
 
always @(wb_addr_i or csr or poc or csc_mask or csc0 or tms0 or csc1 or
tms1 or csc2 or tms2 or csc3 or tms3 or csc4 or tms4 or csc5 or
tms5 or csc6 or tms6 or csc7 or tms7)
case(wb_addr_i[6:2]) // synopsys full_case parallel_case
5'h00: rf_dout <= #1 csr;
5'h01: rf_dout <= #1 poc;
5'h02: rf_dout <= #1 csc_mask;
 
5'h04: rf_dout <= #1 csc0;
5'h05: rf_dout <= #1 tms0;
5'h06: rf_dout <= #1 csc1;
5'h07: rf_dout <= #1 tms1;
5'h08: rf_dout <= #1 csc2;
5'h09: rf_dout <= #1 tms2;
5'h0a: rf_dout <= #1 csc3;
5'h0b: rf_dout <= #1 tms3;
5'h0c: rf_dout <= #1 csc4;
5'h0d: rf_dout <= #1 tms4;
5'h0e: rf_dout <= #1 csc5;
5'h0f: rf_dout <= #1 tms5;
5'h10: rf_dout <= #1 csc6;
5'h11: rf_dout <= #1 tms6;
5'h12: rf_dout <= #1 csc7;
5'h13: rf_dout <= #1 tms7;
endcase
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Register Write logic
//
 
reg [6:0] wb_addr_r;
 
always @(posedge clk)
wb_addr_r <= #1 wb_addr_i[6:0];
 
always @(posedge clk or posedge rst)
if(rst) rf_we <= #1 1'b0;
else rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we;
 
always @(posedge clk or posedge rst)
if(rst) csr_r2 <= #1 8'h0;
else
if(rf_we & (wb_addr_r[6:2] == 5'h0) )
csr_r2 <= #1 wb_data_i[31:24];
 
always @(posedge clk or posedge rst)
if(rst) csr_r[10:1] <= #1 10'h0;
else
if(rf_we & (wb_addr_r[6:2] == 5'h0) )
csr_r[10:1] <= #1 wb_data_i[10:1];
 
always @(posedge clk)
csr_r[0] <= #1 mc_sts;
 
assign mc_vpen = csr_r[1];
assign fs = csr_r[2];
assign rfr_ps_val = csr_r2[7:0];
 
always @(posedge clk or posedge rst)
if(rst) csc_mask_r <= #1 `MC_BA_MASK_VAL;
else
if(rf_we & (wb_addr_r[6:2] == 5'h2) )
csc_mask_r <= #1 wb_data_i[10:0];
 
////////////////////////////////////////////////////////////////////
//
// A kludge for cases where there is no clock during reset ...
//
 
reg rst_r1, rst_r2, rst_r3;
 
always @(posedge clk or posedge rst)
if(rst) rst_r1 <= #1 1'b1;
else rst_r1 <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) rst_r2 <= #1 1'b1;
else rst_r2 <= #1 rst_r1;
 
always @(posedge clk or posedge rst)
if(rst) rst_r3 <= #1 1'b1;
else rst_r3 <= #1 rst_r2;
 
always @(posedge clk)
if(rst_r3) poc <= #1 `MC_POC_VAL;
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Register Ack logic
//
 
always @(posedge clk)
wb_ack_o <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
////////////////////////////////////////////////////////////////////
//
// Select CSC and TMS Registers
//
 
always @(posedge clk or posedge rst)
if(rst) cs <= #1 8'h0;
else
if(cs_le) cs <= #1 {cs7, cs6, cs5, cs4, cs3, cs2, cs1, cs0};
 
always @(posedge clk or posedge rst)
if(rst) wp_err <= #1 1'b0;
else
if(cs_le & wb_cyc_i & wb_stb_i)
wp_err <= #1 wp_err7 | wp_err6 | wp_err5 | wp_err4 |
wp_err3 | wp_err2 | wp_err1 | wp_err0;
else
if(!wb_cyc_i) wp_err <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) csc <= #1 32'h0;
else
if(cs_le_d & wb_cyc_i & wb_stb_i)
begin
if(cs0) csc <= #1 csc0;
else
if(cs1) csc <= #1 csc1;
else
if(cs2) csc <= #1 csc2;
else
if(cs3) csc <= #1 csc3;
else
if(cs4) csc <= #1 csc4;
else
if(cs5) csc <= #1 csc5;
else
if(cs6) csc <= #1 csc6;
else csc <= #1 csc7;
end
 
always @(posedge clk or posedge rst)
if(rst) tms <= #1 32'hffff_ffff;
else
if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)
begin
if(cs0) tms <= #1 tms0;
else
if(cs1) tms <= #1 tms1;
else
if(cs2) tms <= #1 tms2;
else
if(cs3) tms <= #1 tms3;
else
if(cs4) tms <= #1 tms4;
else
if(cs5) tms <= #1 tms5;
else
if(cs6) tms <= #1 tms6;
else tms <= #1 tms7;
end
 
always @(posedge clk or posedge rst)
if(rst) sp_csc <= #1 32'h0;
else
if(cs_le_d & wb_cyc_i & wb_stb_i)
begin
if(spec_req_cs[0]) sp_csc <= #1 csc0;
else
if(spec_req_cs[1]) sp_csc <= #1 csc1;
else
if(spec_req_cs[2]) sp_csc <= #1 csc2;
else
if(spec_req_cs[3]) sp_csc <= #1 csc3;
else
if(spec_req_cs[4]) sp_csc <= #1 csc4;
else
if(spec_req_cs[5]) sp_csc <= #1 csc5;
else
if(spec_req_cs[6]) sp_csc <= #1 csc6;
else sp_csc <= #1 csc7;
end
 
always @(posedge clk or posedge rst)
if(rst) sp_tms <= #1 32'hffff_ffff;
else
if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)
begin
if(spec_req_cs[0]) sp_tms <= #1 tms0;
else
if(spec_req_cs[1]) sp_tms <= #1 tms1;
else
if(spec_req_cs[2]) sp_tms <= #1 tms2;
else
if(spec_req_cs[3]) sp_tms <= #1 tms3;
else
if(spec_req_cs[4]) sp_tms <= #1 tms4;
else
if(spec_req_cs[5]) sp_tms <= #1 tms5;
else
if(spec_req_cs[6]) sp_tms <= #1 tms6;
else sp_tms <= #1 tms7;
end
 
assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MC_MEM_TYPE_SDRAM);
 
assign ref_int = csr_r[10:8];
 
////////////////////////////////////////////////////////////////////
//
// Init & Lmr Logic
//
 
// Init Ack falling edge detector
always @(posedge clk)
init_ack_r <= #1 init_ack;
 
assign init_ack_fe = init_ack_r & !init_ack;
 
// LMR Ack falling edge detector
always @(posedge clk)
lmr_ack_r <= #1 lmr_ack;
 
assign lmr_ack_fe = lmr_ack_r & !lmr_ack;
 
// Chip Select Output
always @(posedge clk or posedge rst)
if(rst) spec_req_cs <= #1 8'h0;
else
if(sreq_cs_le) spec_req_cs <= #1 spec_req_cs_d;
 
always @(posedge clk or posedge rst)
if(rst) sreq_cs_le <= #1 1'b0;
else sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe;
 
// Make sure only one is serviced at a time
assign spec_req_cs_d[0] = spec_req_cs_t[0];
assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0];
assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] );
assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] );
assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] );
assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] );
assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] );
assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] );
 
// Request Tracking
always @(posedge clk or posedge rst)
if(rst) init_req <= #1 1'b0;
else init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 |
init_req4 | init_req5 | init_req6 | init_req7;
 
always @(posedge clk or posedge rst)
if(rst) lmr_req <= #1 1'b0;
else lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 |
lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7;
 
assign spec_req_cs_t = !init_req ? // Load Mode Register Requests
{lmr_req7, lmr_req6, lmr_req5, lmr_req4,
lmr_req3, lmr_req2, lmr_req1, lmr_req0 } :
// Initialize SDRAM Requests
{init_req7, init_req6, init_req5, init_req4,
init_req3, init_req2, init_req1, init_req0 };
 
// Ack distribution
assign lmr_ack0 = spec_req_cs[0] & lmr_ack_fe;
assign lmr_ack1 = spec_req_cs[1] & lmr_ack_fe;
assign lmr_ack2 = spec_req_cs[2] & lmr_ack_fe;
assign lmr_ack3 = spec_req_cs[3] & lmr_ack_fe;
assign lmr_ack4 = spec_req_cs[4] & lmr_ack_fe;
assign lmr_ack5 = spec_req_cs[5] & lmr_ack_fe;
assign lmr_ack6 = spec_req_cs[6] & lmr_ack_fe;
assign lmr_ack7 = spec_req_cs[7] & lmr_ack_fe;
 
assign init_ack0 = spec_req_cs[0] & init_ack_fe;
assign init_ack1 = spec_req_cs[1] & init_ack_fe;
assign init_ack2 = spec_req_cs[2] & init_ack_fe;
assign init_ack3 = spec_req_cs[3] & init_ack_fe;
assign init_ack4 = spec_req_cs[4] & init_ack_fe;
assign init_ack5 = spec_req_cs[5] & init_ack_fe;
assign init_ack6 = spec_req_cs[6] & init_ack_fe;
assign init_ack7 = spec_req_cs[7] & init_ack_fe;
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
mc_cs_rf #(3'h0) u0(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc0 ),
.tms( tms0 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs0 ),
.wp_err( wp_err0 ),
.lmr_req( lmr_req0 ),
.lmr_ack( lmr_ack0 ),
.init_req( init_req0 ),
.init_ack( init_ack0 )
);
 
`ifdef MC_HAVE_CS1
mc_cs_rf #(3'h1) u1(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc1 ),
.tms( tms1 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs1 ),
.wp_err( wp_err1 ),
.lmr_req( lmr_req1 ),
.lmr_ack( lmr_ack1 ),
.init_req( init_req1 ),
.init_ack( init_ack1 )
);
`else
mc_cs_rf_dummy #(3'h1) u1(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc1 ),
.tms( tms1 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs1 ),
.wp_err( wp_err1 ),
.lmr_req( lmr_req1 ),
.lmr_ack( lmr_ack1 ),
.init_req( init_req1 ),
.init_ack( init_ack1 )
);
`endif
 
`ifdef MC_HAVE_CS2
mc_cs_rf #(3'h2) u2(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc2 ),
.tms( tms2 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs2 ),
.wp_err( wp_err2 ),
.lmr_req( lmr_req2 ),
.lmr_ack( lmr_ack2 ),
.init_req( init_req2 ),
.init_ack( init_ack2 )
);
`else
mc_cs_rf_dummy #(3'h2) u2(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc2 ),
.tms( tms2 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs2 ),
.wp_err( wp_err2 ),
.lmr_req( lmr_req2 ),
.lmr_ack( lmr_ack2 ),
.init_req( init_req2 ),
.init_ack( init_ack2 )
);
`endif
 
`ifdef MC_HAVE_CS3
mc_cs_rf #(3'h3) u3(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc3 ),
.tms( tms3 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs3 ),
.wp_err( wp_err3 ),
.lmr_req( lmr_req3 ),
.lmr_ack( lmr_ack3 ),
.init_req( init_req3 ),
.init_ack( init_ack3 )
);
`else
mc_cs_rf_dummy #(3'h3) u3(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc3 ),
.tms( tms3 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs3 ),
.wp_err( wp_err3 ),
.lmr_req( lmr_req3 ),
.lmr_ack( lmr_ack3 ),
.init_req( init_req3 ),
.init_ack( init_ack3 )
);
`endif
 
`ifdef MC_HAVE_CS4
mc_cs_rf #(3'h4) u4(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc4 ),
.tms( tms4 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs4 ),
.wp_err( wp_err4 ),
.lmr_req( lmr_req4 ),
.lmr_ack( lmr_ack4 ),
.init_req( init_req4 ),
.init_ack( init_ack4 )
);
`else
mc_cs_rf_dummy #(3'h4) u4(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc4 ),
.tms( tms4 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs4 ),
.wp_err( wp_err4 ),
.lmr_req( lmr_req4 ),
.lmr_ack( lmr_ack4 ),
.init_req( init_req4 ),
.init_ack( init_ack4 )
);
`endif
 
`ifdef MC_HAVE_CS5
mc_cs_rf #(3'h5) u5(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc5 ),
.tms( tms5 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs5 ),
.wp_err( wp_err5 ),
.lmr_req( lmr_req5 ),
.lmr_ack( lmr_ack5 ),
.init_req( init_req5 ),
.init_ack( init_ack5 )
);
`else
mc_cs_rf_dummy #(3'h5) u5(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc5 ),
.tms( tms5 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs5 ),
.wp_err( wp_err5 ),
.lmr_req( lmr_req5 ),
.lmr_ack( lmr_ack5 ),
.init_req( init_req5 ),
.init_ack( init_ack5 )
);
`endif
 
`ifdef MC_HAVE_CS6
mc_cs_rf #(3'h6) u6(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc6 ),
.tms( tms6 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs6 ),
.wp_err( wp_err6 ),
.lmr_req( lmr_req6 ),
.lmr_ack( lmr_ack6 ),
.init_req( init_req6 ),
.init_ack( init_ack6 )
);
`else
mc_cs_rf_dummy #(3'h6) u6(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc6 ),
.tms( tms6 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs6 ),
.wp_err( wp_err6 ),
.lmr_req( lmr_req6 ),
.lmr_ack( lmr_ack6 ),
.init_req( init_req6 ),
.init_ack( init_ack6 )
);
`endif
 
`ifdef MC_HAVE_CS7
mc_cs_rf #(3'h7) u7(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc7 ),
.tms( tms7 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs7 ),
.wp_err( wp_err7 ),
.lmr_req( lmr_req7 ),
.lmr_ack( lmr_ack7 ),
.init_req( init_req7 ),
.init_ack( init_ack7 )
);
`else
mc_cs_rf_dummy #(3'h7) u7(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc7 ),
.tms( tms7 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs7 ),
.wp_err( wp_err7 ),
.lmr_req( lmr_req7 ),
.lmr_ack( lmr_ack7 ),
.init_req( init_req7 ),
.init_ack( init_ack7 )
);
`endif
 
endmodule
 
/verilog/minsoc/mc/mc_obct.v
0,0 → 1,236
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Open Bank & Row Tracking Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_obct.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_obct.v,v $
// Revision 1.4 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.3 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.2 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
//
// 1) Fixed Chip Select Mask Register
// - Power On Value is now all ones
// - Comparison Logic is now correct
//
// 2) All resets are now asynchronous
//
// 3) Converted Power On Delay to an configurable item
//
// 4) Added reset to Chip Select Output Registers
//
// 5) Forcing all outputs to Hi-Z state during reset
//
// Revision 1.1.1.1 2001/05/13 09:39:45 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
bank_open, any_bank_open, row_same);
input clk, rst;
input [12:0] row_adr;
input [1:0] bank_adr;
input bank_set;
input bank_clr;
input bank_clr_all;
output bank_open;
output any_bank_open;
output row_same;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg bank0_open, bank1_open, bank2_open, bank3_open;
reg bank_open;
reg [12:0] b0_last_row;
reg [12:0] b1_last_row;
reg [12:0] b2_last_row;
reg [12:0] b3_last_row;
wire row0_same, row1_same, row2_same, row3_same;
reg row_same;
 
////////////////////////////////////////////////////////////////////
//
// Bank Open/Closed Tracking
//
 
always @(posedge clk or posedge rst)
if(rst) bank0_open <= #1 1'b0;
else
if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1;
else
if((bank_adr == 2'h0) & bank_clr) bank0_open <= #1 1'b0;
else
if(bank_clr_all) bank0_open <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) bank1_open <= #1 1'b0;
else
if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1;
else
if((bank_adr == 2'h1) & bank_clr) bank1_open <= #1 1'b0;
else
if(bank_clr_all) bank1_open <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) bank2_open <= #1 1'b0;
else
if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1;
else
if((bank_adr == 2'h2) & bank_clr) bank2_open <= #1 1'b0;
else
if(bank_clr_all) bank2_open <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) bank3_open <= #1 1'b0;
else
if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1;
else
if((bank_adr == 2'h3) & bank_clr) bank3_open <= #1 1'b0;
else
if(bank_clr_all) bank3_open <= #1 1'b0;
 
always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open)
case(bank_adr) // synopsys full_case parallel_case
2'h0: bank_open = bank0_open;
2'h1: bank_open = bank1_open;
2'h2: bank_open = bank2_open;
2'h3: bank_open = bank3_open;
endcase
 
assign any_bank_open = bank0_open | bank1_open | bank2_open | bank3_open;
 
////////////////////////////////////////////////////////////////////
//
// Raw Address Tracking
//
 
always @(posedge clk)
if((bank_adr == 2'h0) & bank_set) b0_last_row <= #1 row_adr;
 
always @(posedge clk)
if((bank_adr == 2'h1) & bank_set) b1_last_row <= #1 row_adr;
 
always @(posedge clk)
if((bank_adr == 2'h2) & bank_set) b2_last_row <= #1 row_adr;
 
always @(posedge clk)
if((bank_adr == 2'h3) & bank_set) b3_last_row <= #1 row_adr;
 
////////////////////////////////////////////////////////////////////
//
// Raw address checking
//
 
assign row0_same = (b0_last_row == row_adr);
assign row1_same = (b1_last_row == row_adr);
assign row2_same = (b2_last_row == row_adr);
assign row3_same = (b3_last_row == row_adr);
 
always @(bank_adr or row0_same or row1_same or row2_same or row3_same)
case(bank_adr) // synopsys full_case parallel_case
2'h0: row_same = row0_same;
2'h1: row_same = row1_same;
2'h2: row_same = row2_same;
2'h3: row_same = row3_same;
endcase
 
endmodule
 
 
// This is used for unused Chip Selects
module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
bank_open, any_bank_open, row_same);
input clk, rst;
input [12:0] row_adr;
input [1:0] bank_adr;
input bank_set;
input bank_clr;
input bank_clr_all;
output bank_open;
output any_bank_open;
output row_same;
 
assign bank_open = 1'b0;
assign any_bank_open = 1'b0;
assign row_same = 1'b0;
 
endmodule
/verilog/minsoc/mc/mc_incn_r.v
0,0 → 1,102
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Parametarized, Pipelined Incrementer ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_incn_r.v,v 1.2 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_incn_r.v,v $
// Revision 1.2 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1 2001/06/12 15:18:47 rudi
//
//
// This is a pipelined primitive incrementor.
//
//
//
//
//
 
`include "mc_defines.v"
 
//
// USAGE: incN_r #(<WIDTH>) uN(clk, input, output);
//
module mc_incn_r(clk, inc_in, inc_out);
 
parameter incN_width = 32;
 
input clk;
input [incN_width-1:0] inc_in;
output [incN_width-1:0] inc_out;
 
parameter incN_center = incN_width / 2;
 
reg [incN_center:0] out_r;
wire [31:0] tmp_zeros = 32'h0;
wire [incN_center-1:0] inc_next;
 
always @(posedge clk)
out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1};
 
assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next;
 
assign inc_next = out_r[incN_center] ?
{tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0];
 
assign inc_out[incN_center-1:0] = out_r;
 
endmodule
 
/verilog/minsoc/mc/mc_rd_fifo.v
0,0 → 1,130
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Read FIFO ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_rd_fifo.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_rd_fifo.v,v $
// Revision 1.4 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.3 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.2 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1.1.1 2001/05/13 09:39:44 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_rd_fifo(clk, rst, clr, din, we, dout, re);
 
input clk, rst, clr;
input [35:0] din;
input we;
output [35:0] dout;
input re;
 
reg [3:0] rd_adr, wr_adr;
reg [35:0] r0, r1, r2, r3;
reg [35:0] dout;
 
always @(posedge clk or posedge rst)
if(rst) rd_adr <= #1 4'h1;
else
if(clr) rd_adr <= #1 4'h1;
else
if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
 
always @(posedge clk or posedge rst)
if(rst) wr_adr <= #1 4'h1;
else
if(clr) wr_adr <= #1 4'h1;
else
if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
 
always @(posedge clk)
if(we & wr_adr[0]) r0 <= #1 din;
 
always @(posedge clk)
if(we & wr_adr[1]) r1 <= #1 din;
 
always @(posedge clk)
if(we & wr_adr[2]) r2 <= #1 din;
 
always @(posedge clk)
if(we & wr_adr[3]) r3 <= #1 din;
 
always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)
case(rd_adr) // synopsys full_case parallel_case
4'h1: dout = r0;
4'h2: dout = r1;
4'h4: dout = r2;
4'h8: dout = r3;
endcase
 
endmodule
/verilog/minsoc/mc/mc_adr_sel.v
0,0 → 1,290
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller Address Select Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_adr_sel.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_adr_sel.v,v $
// Revision 1.4 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.3 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.2 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
// Revision 1.1.1.1 2001/05/13 09:39:40 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i,
wb_write_go, wr_hold, cas_,
mc_addr, row_adr, bank_adr, rfr_ack,
cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,
page_size);
 
input clk;
input [31:0] csc;
input [31:0] tms;
input wb_ack_o, wb_stb_i;
input [31:0] wb_addr_i;
input wb_we_i;
input wb_write_go;
input wr_hold;
input cas_;
output [23:0] mc_addr;
output [12:0] row_adr;
output [1:0] bank_adr;
input rfr_ack;
input cs_le;
input cmd_a10;
input row_sel;
input lmr_sel;
input next_adr;
input wr_cycle;
output [10:0] page_size;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg [23:0] mc_addr_d;
reg [23:0] acs_addr;
wire [23:0] acs_addr_pl1;
reg [23:0] sram_addr;
wire [14:0] sdram_adr;
reg [12:0] row_adr;
reg [9:0] col_adr;
reg [1:0] bank_adr;
reg [10:0] page_size;
 
wire [2:0] mem_type;
wire [1:0] bus_width;
wire [1:0] mem_size;
wire bas;
 
// Aliases
assign mem_type = csc[3:1];
assign bus_width = csc[5:4];
assign mem_size = csc[7:6];
assign bas = csc[9];
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i)
if(mem_type == `MC_MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr};
else
if(mem_type == `MC_MEM_TYPE_ACS) mc_addr_d = acs_addr;
else
if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr;
else mc_addr_d = wb_addr_i[25:2];
 
assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d;
 
////////////////////////////////////////////////////////////////////
//
// Async Devices Address Latch & Counter
//
 
mc_incn_r #(24) u0( .clk( clk ),
.inc_in( acs_addr ),
.inc_out( acs_addr_pl1 ) );
 
always @(posedge clk)
if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2];
 
always @(posedge clk)
if(cs_le | wb_we_i)
case(bus_width) // synopsys full_case parallel_case
`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];
`MC_BW_32: acs_addr <= #1 wb_addr_i[25:2];
endcase
else
if(next_adr) acs_addr <= #1 acs_addr_pl1;
 
////////////////////////////////////////////////////////////////////
//
// SDRAM Address Mux
//
 
assign sdram_adr[12:0] = (lmr_sel & !cas_) ? tms[12:0] :
row_sel ? row_adr :
{2'h0, cmd_a10, col_adr};
 
assign sdram_adr[14:13] = bank_adr;
 
always @(posedge clk)
if(wr_cycle ? wb_ack_o : wb_stb_i)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
{`MC_BW_8, `MC_MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2];
{`MC_BW_8, `MC_MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2];
 
{`MC_BW_16, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
{`MC_BW_16, `MC_MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
{`MC_BW_16, `MC_MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
 
{`MC_BW_32, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
{`MC_BW_32, `MC_MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
{`MC_BW_32, `MC_MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
endcase
 
always @(posedge clk)
if(cs_le)
begin
if(!bas)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]};
{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14];
{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13];
{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]};
{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
endcase
else
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11];
{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]};
{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10];
endcase
end
 
 
always @(posedge clk)
if(cs_le)
begin
if(!bas)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11];
{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12];
{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12];
{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11];
{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11];
{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10];
{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10];
endcase
else
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23];
{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24];
{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25];
{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22];
{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23];
{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24];
{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21];
{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22];
{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23];
endcase
end
 
always @(bus_width or mem_size)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: page_size = 11'd512;
{`MC_BW_8, `MC_MEM_SIZE_128}: page_size = 11'd1024;
{`MC_BW_8, `MC_MEM_SIZE_256}: page_size = 11'd1024;
 
{`MC_BW_16, `MC_MEM_SIZE_64}: page_size = 11'd256;
{`MC_BW_16, `MC_MEM_SIZE_128}: page_size = 11'd512;
{`MC_BW_16, `MC_MEM_SIZE_256}: page_size = 11'd512;
 
{`MC_BW_32, `MC_MEM_SIZE_64}: page_size = 11'd256;
{`MC_BW_32, `MC_MEM_SIZE_128}: page_size = 11'd256;
{`MC_BW_32, `MC_MEM_SIZE_256}: page_size = 11'd256;
endcase
 
endmodule
 
/verilog/minsoc/mc/mc_obct_top.v
0,0 → 1,426
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Memory Controller ////
//// Open Bank & Row Tracking Block Top Level ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: mc_obct_top.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
// $Date: 2002/01/21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: mc_obct_top.v,v $
// Revision 1.4 2002/01/21 13:08:52 rudi
//
// Fixed several minor bugs, cleaned up the code further ...
//
// Revision 1.3 2001/12/21 05:09:29 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1.1.1 2001/05/13 09:39:47 rudi
// Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
bank_open, any_bank_open, row_same, rfr_ack);
input clk, rst;
input [7:0] cs;
input [12:0] row_adr;
input [1:0] bank_adr;
input bank_set;
input bank_clr;
input bank_clr_all;
output bank_open;
output any_bank_open;
output row_same;
input rfr_ack;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg bank_open;
reg row_same;
reg any_bank_open;
 
wire bank_set_0;
wire bank_clr_0;
wire bank_clr_all_0;
wire bank_open_0;
wire row_same_0;
wire any_bank_open_0;
 
wire bank_set_1;
wire bank_clr_1;
wire bank_clr_all_1;
wire bank_open_1;
wire row_same_1;
wire any_bank_open_1;
 
wire bank_set_2;
wire bank_clr_2;
wire bank_clr_all_2;
wire bank_open_2;
wire row_same_2;
wire any_bank_open_2;
 
wire bank_set_3;
wire bank_clr_3;
wire bank_clr_all_3;
wire bank_open_3;
wire row_same_3;
wire any_bank_open_3;
 
wire bank_set_4;
wire bank_clr_4;
wire bank_clr_all_4;
wire bank_open_4;
wire row_same_4;
wire any_bank_open_4;
 
wire bank_set_5;
wire bank_clr_5;
wire bank_clr_all_5;
wire bank_open_5;
wire row_same_5;
wire any_bank_open_5;
 
wire bank_set_6;
wire bank_clr_6;
wire bank_clr_all_6;
wire bank_open_6;
wire row_same_6;
wire any_bank_open_6;
 
wire bank_set_7;
wire bank_clr_7;
wire bank_clr_all_7;
wire bank_open_7;
wire row_same_7;
wire any_bank_open_7;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign bank_set_0 = cs[0] & bank_set;
assign bank_set_1 = cs[1] & bank_set;
assign bank_set_2 = cs[2] & bank_set;
assign bank_set_3 = cs[3] & bank_set;
assign bank_set_4 = cs[4] & bank_set;
assign bank_set_5 = cs[5] & bank_set;
assign bank_set_6 = cs[6] & bank_set;
assign bank_set_7 = cs[7] & bank_set;
 
assign bank_clr_0 = cs[0] & bank_clr;
assign bank_clr_1 = cs[1] & bank_clr;
assign bank_clr_2 = cs[2] & bank_clr;
assign bank_clr_3 = cs[3] & bank_clr;
assign bank_clr_4 = cs[4] & bank_clr;
assign bank_clr_5 = cs[5] & bank_clr;
assign bank_clr_6 = cs[6] & bank_clr;
assign bank_clr_7 = cs[7] & bank_clr;
 
assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack;
assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack;
assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack;
assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack;
assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack;
assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack;
assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack;
assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack;
 
always @(posedge clk)
bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) |
(cs[2] & bank_open_2) | (cs[3] & bank_open_3) |
(cs[4] & bank_open_4) | (cs[5] & bank_open_5) |
(cs[6] & bank_open_6) | (cs[7] & bank_open_7);
 
always @(posedge clk)
row_same <= #1 (cs[0] & row_same_0) | (cs[1] & row_same_1) |
(cs[2] & row_same_2) | (cs[3] & row_same_3) |
(cs[4] & row_same_4) | (cs[5] & row_same_5) |
(cs[6] & row_same_6) | (cs[7] & row_same_7);
 
always @(posedge clk)
any_bank_open <= #1 (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) |
(cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) |
(cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) |
(cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7);
 
 
////////////////////////////////////////////////////////////////////
//
// OBCT Modules for each Chip Select
//
 
mc_obct u0(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_0 ),
.bank_clr( bank_clr_0 ),
.bank_clr_all( bank_clr_all_0 ),
.bank_open( bank_open_0 ),
.any_bank_open( any_bank_open_0 ),
.row_same( row_same_0 )
);
 
`ifdef MC_HAVE_CS1
mc_obct u1(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_1 ),
.bank_clr( bank_clr_1 ),
.bank_clr_all( bank_clr_all_1 ),
.bank_open( bank_open_1 ),
.any_bank_open( any_bank_open_1 ),
.row_same( row_same_1 )
);
`else
mc_obct_dummy u1(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_1 ),
.bank_clr( bank_clr_1 ),
.bank_clr_all( bank_clr_all_1 ),
.bank_open( bank_open_1 ),
.any_bank_open( any_bank_open_1 ),
.row_same( row_same_1 )
);
`endif
 
`ifdef MC_HAVE_CS2
mc_obct u2(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_2 ),
.bank_clr( bank_clr_2 ),
.bank_clr_all( bank_clr_all_2 ),
.bank_open( bank_open_2 ),
.any_bank_open( any_bank_open_2 ),
.row_same( row_same_2 )
);
`else
mc_obct_dummy u2(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_2 ),
.bank_clr( bank_clr_2 ),
.bank_clr_all( bank_clr_all_2 ),
.bank_open( bank_open_2 ),
.any_bank_open( any_bank_open_2 ),
.row_same( row_same_2 )
);
`endif
 
`ifdef MC_HAVE_CS3
mc_obct u3(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_3 ),
.bank_clr( bank_clr_3 ),
.bank_clr_all( bank_clr_all_3 ),
.bank_open( bank_open_3 ),
.any_bank_open( any_bank_open_3 ),
.row_same( row_same_3 )
);
`else
mc_obct_dummy u3(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_3 ),
.bank_clr( bank_clr_3 ),
.bank_clr_all( bank_clr_all_3 ),
.bank_open( bank_open_3 ),
.any_bank_open( any_bank_open_3 ),
.row_same( row_same_3 )
);
`endif
 
`ifdef MC_HAVE_CS4
mc_obct u4(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_4 ),
.bank_clr( bank_clr_4 ),
.bank_clr_all( bank_clr_all_4 ),
.bank_open( bank_open_4 ),
.any_bank_open( any_bank_open_4 ),
.row_same( row_same_4 )
);
`else
mc_obct_dummy u4(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_4 ),
.bank_clr( bank_clr_4 ),
.bank_clr_all( bank_clr_all_4 ),
.bank_open( bank_open_4 ),
.any_bank_open( any_bank_open_4 ),
.row_same( row_same_4 )
);
`endif
 
`ifdef MC_HAVE_CS5
mc_obct u5(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_5 ),
.bank_clr( bank_clr_5 ),
.bank_clr_all( bank_clr_all_5 ),
.bank_open( bank_open_5 ),
.any_bank_open( any_bank_open_5 ),
.row_same( row_same_5 )
);
`else
mc_obct_dummy u5(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_5 ),
.bank_clr( bank_clr_5 ),
.bank_clr_all( bank_clr_all_5 ),
.bank_open( bank_open_5 ),
.any_bank_open( any_bank_open_5 ),
.row_same( row_same_5 )
);
`endif
 
`ifdef MC_HAVE_CS6
mc_obct u6(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_6 ),
.bank_clr( bank_clr_6 ),
.bank_clr_all( bank_clr_all_6 ),
.bank_open( bank_open_6 ),
.any_bank_open( any_bank_open_6 ),
.row_same( row_same_6 )
);
`else
mc_obct_dummy u6(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_6 ),
.bank_clr( bank_clr_6 ),
.bank_clr_all( bank_clr_all_6 ),
.bank_open( bank_open_6 ),
.any_bank_open( any_bank_open_6 ),
.row_same( row_same_6 )
);
`endif
 
`ifdef MC_HAVE_CS7
mc_obct u7(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_7 ),
.bank_clr( bank_clr_7 ),
.bank_clr_all( bank_clr_all_7 ),
.bank_open( bank_open_7 ),
.any_bank_open( any_bank_open_7 ),
.row_same( row_same_7 )
);
`else
mc_obct_dummy u7(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_7 ),
.bank_clr( bank_clr_7 ),
.bank_clr_all( bank_clr_all_7 ),
.bank_open( bank_open_7 ),
.any_bank_open( any_bank_open_7 ),
.row_same( row_same_7 )
);
`endif
 
endmodule
/verilog/minsoc/minsoc_onchip_ram.v
0,0 → 1,458
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, rfajardo@gmail.com ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
//
// Revision 2.1 2009/08/23 16:41:00 fajardo
// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY
// This actually models appropriately the behavior of the FPGA internal RAMs
//
// Revision 2.0 2009/09/10 11:30:00 fajardo
// Added tri-state buffering for altera output
// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY
//
// Revision 1.9 2009/08/18 15:15:00 fajardo
// Added tri-state buffering for xilinx and generic memory output
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "minsoc_defines.v"
module minsoc_onchip_ram(
`ifdef BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
`ifdef BIST
//
// RAM BIST
//
input mbist_si_i;
input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Decide memory implementation for Xilinx FPGAs
//
`ifdef SPARTAN2
`define MINSOC_XILINX_RAMB4
`elsif VIRTEX
`define MINSOC_XILINX_RAMB4
`endif // !SPARTAN2/VIRTEX
`ifdef SPARTAN3
`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3E
`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3A
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX2
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
`define MINSOC_XILINX_RAMB16
`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5
//
// Internal wires and registers
//
`ifdef ARTISAN_SSP
`else
`ifdef VIRTUALSILICON_SSP
`else
`ifdef BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef GENERIC_MEMORY
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`elsif ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`elsif AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`elsif VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`elsif VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`elsif MINSOC_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// SPARTAN2/VIRTEX
//
wire [dw-1:0] doq_internal; // output data bus
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq_internal[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq_internal[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq_internal[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq_internal[7:6])
);
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
`elsif MINSOC_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// SPARTAN3/SPARTAN3E/VIRTEX2
// SPARTAN3A/VIRTEX4/VIRTEX5 are automatically reallocated by ISE
//
// Added By Nir Mor
//
wire [dw-1:0] doq_internal; // output data bus
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq_internal),
.DOP()
);
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
`elsif ALTERA_FPGA
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
wire [dw-1:0] doq_internal; // output data bus
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.data(di),
.we(wr),
.q(doq_internal)
);
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`endif // !ALTERA_FPGA/MINCON_XILINX_RAMB16/MINCON_XILINX_RAMB4/VIRTUALSILICON_SSP/VIRAGE_SSP/AVANT_ATP/ARTISAN_SSP/GENERIC_MEMORY
endmodule
/vhdl/WISHBONE_IIR/.vhd
0,0 → 1,26
--Second Order Sections (SOS) automatically generated VHDL package file
--M.Eng. Alexander López Parrado
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
package coefs_sos is
 
 
--The number of sections
constant NSECT:integer:=6;
 
--Number of bits in fractional part of coeffcients
--Fixed point format with 16 bits ([3].[13])
constant Q: integer:=13;
 
--Gain on each stage
constant GAIN: std_logic_vector(15 downto 0):= std_logic_vector(to_signed(169,16));
 
--Filter Coefficients ...(b0,b1,b2,a0,a1,a2)_stage1,(b0,b1,b2,a0,a1,a2)_stage0
constant COEFFS: std_logic_vector(575 downto 0):="001000000000000011000000000000000010000000000000001000000000000011000011110101000001111110110000001000000000000011000000000111010001111111100011001000000000000011000100110001100001111110011101001000000000000010111111111000110010000000011101001000000000000011000100011001010001111100101000001000000000000000111111111011100001111111101110001000000000000011000101000110010001111100011001001000000000000001000000000000000010000000000000001000000000000011000101010011000001111010111110001000000000000001000000000100100010000000010010001000000000000011000101001000010001111010011100";
 
end coefs_sos;
/vhdl/WISHBONE_IIR/SOS.vhd
0,0 → 1,168
library ieee;
--library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Structure SOS
entity SOS is
generic (WordWidth:integer;--width signal of in/out
Bit_growth:integer;
NSECT:integer;--Cant of sections
M:integer;--width word of coefs
Q:integer--Q--Quantifer
);
port(
 
signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);
h0: in std_logic_vector((NSECT*M*6)-1 downto 0);
gain: in std_logic_vector(M-1 downto 0);
signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);
en_out : in std_logic_vector(3 downto 0);
enable_out:out std_logic;
clk,reset,clear,enable:in std_logic
 
);
end entity;
 
architecture RTL of SOS is
--Filter Tworder component
component Tworder is
generic (WordWidth:integer;--:=16;--width signal of in/out
Bit_growth:integer;
M:integer;--:=16;--width word of coefs
Q:integer--:=15--Quantifer
);
port(
 
signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);
a0,a1,a2,b0,b1,b2: in std_logic_vector(M-1 downto 0);
signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);
clk,reset,clear,enable:in std_logic
 
);
end component;
 
--The fullregister component
component fullregister is
 
generic
(
N: integer
);
 
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
clear : in std_logic;
d : in std_logic_vector(N-1 downto 0);
q : out std_logic_vector(N-1 downto 0)
);
end component;
--
type output_aux is array(NSECT downto 0) of std_logic_vector(WordWidth+Bit_growth-1 downto 0);
signal output,out_reg: output_aux;
 
type gain_out_t is array(NSECT downto 0) of std_logic_vector(M+WordWidth+Bit_growth-1 downto 0);
 
signal gain_out: gain_out_t;
 
 
constant Nh: integer :=(NSECT*M*6);
 
signal filter_coef:std_logic_vector(Nh-1 downto 0);
signal signal_output_aux:std_logic_vector(WordWidth+Bit_growth-1 downto 0);
--type aux_enable is array (0 to NSECT) of std_logic_vector(0 downto 0);
type aux_enable is array (0 to 2*NSECT) of std_logic_vector(0 downto 0);
signal enable_aux:aux_enable;
begin
 
filter_coef<=h0;
myfilter:
for k in NSECT-1 downto 0 generate
filter:Tworder
generic map(
WordWidth=>WordWidth,
Bit_growth=>Bit_growth,
M=>M,
Q=>Q
)
port map(
signal_input => out_reg(k),
a2=>filter_coef((1*(M)+(k*(M)*6))-1 downto (k*(M)*6)),
a1=>filter_coef((2*(M)+(k*(M)*6))-1 downto (1*(M)+(k*(M)*6))),
a0=>filter_coef((3*(M)+(k*(M)*6))-1 downto (2*(M)+(k*(M)*6))),
b2=>filter_coef((4*(M)+(k*(M)*6))-1 downto (3*(M)+(k*(M)*6))),
b1=>filter_coef((5*(M)+(k*(M)*6))-1 downto (4*(M)+(k*(M)*6))),
b0=>filter_coef((6*(M)+(k*(M)*6))-1 downto (5*(M)+(k*(M)*6))),
signal_output => output(k),
clk=>clk,
reset=>reset,
clear=>clear,
enable=>enable_aux(k*2)(0)
);
gain_out(k)<=std_logic_vector(signed(gain)*signed(output(k)));
Reg_seg:fullregister
generic map(
N=>WordWidth+Bit_growth
)
port map (
clk=>clk,
reset_n=>reset,
enable=>'1',
clear=>clear,
d=>gain_out(k)(WordWidth+Bit_growth-1+Q downto Q),
q=>out_reg(k+1)
);
 
end generate;
myenables:
for k in 0 to 2*NSECT-1 generate
Reg_enables:fullregister
generic map(
N=>1
)
port map (
clk=>clk,
reset_n=>reset,
enable=>'1',
clear=>clear,
d=>enable_aux(k),
q=>enable_aux(k+1)
);
end generate;
 
out_reg(0)<=signal_input;
enable_aux(0)(0)<=enable;
enable_out<=enable_aux(to_integer((2*(unsigned(en_out))+2)))(0);
signal_output_aux <= gain_out(to_integer(unsigned(en_out)))(WordWidth+Bit_growth-1+Q downto Q);
Reg_out:fullregister
generic map(
N=>WordWidth+Bit_growth
)
port map (
clk=>clk,
reset_n=>reset,
enable=>'1',
clear=>clear,
d=>signal_output_aux,
q=>signal_output
);
end architecture;
vhdl/WISHBONE_IIR/SOS.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_IIR/Tworder.vhd =================================================================== --- vhdl/WISHBONE_IIR/Tworder.vhd (nonexistent) +++ vhdl/WISHBONE_IIR/Tworder.vhd (revision 5) @@ -0,0 +1,108 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Tworder is +generic (WordWidth:integer;--:=16;--width signal of in/out + Bit_growth:integer;--:=8; + M:integer;--:=16;--width word of coefs + Q:integer--:=15--Quantifer + ); + +port( + +signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0); +a0,a1,a2,b0,b1,b2: in std_logic_vector(M-1 downto 0); +signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0); +clk,reset,clear,enable:in std_logic + +); +end entity; + +architecture RTL of Tworder is +--The fullregister component +component fullregister is + + generic + ( + N: integer + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + clear : in std_logic; + d : in std_logic_vector(N-1 downto 0); + q : out std_logic_vector(N-1 downto 0) + + ); +end component; + +signal signal_output_aux,signal_input_aux: std_logic_vector(M+Bit_growth+WordWidth-1 downto 0); +signal sum_in,sum_out_aux,sum_out: std_logic_vector((M+WordWidth+Bit_growth)-1 downto 0); +signal RegOut1,RegOut2,RegOut1_aux: std_logic_vector(WordWidth+Bit_growth-1 downto 0); +signal signal1_in,signal2_in,signal3_in,signal1_out,signal2_out,signal3_out : std_logic_vector(M+WordWidth+Bit_growth-1 downto 0); + +begin + +--EXTENSION DE SIGNO +signal_input_aux(WordWidth+Bit_growth+Q-1 downto Q)<=signal_input; +signal_input_aux(Q-1 downto 0)<=(others=>'0'); +signal_input_aux(M+WordWidth+Bit_growth-1 downto WordWidth+Bit_growth+Q)<=(others=>signal_input(WordWidth+Bit_growth-1)); + + + +signal1_in<=std_logic_vector(signed(RegOut1)*signed(a1)); +signal2_in<=std_logic_vector(signed(RegOut2)*signed(a2)); +signal3_in<=signal_input_aux; +signal1_out<=std_logic_vector(signed(RegOut1)*signed(b1)); +signal2_out<=std_logic_vector(signed(RegOut2)*signed(b2)); +--signal3_out<=std_logic_vector(signed(sum_in_aux((WordWidth+Bit_growth-1)+Q downto Q))*signed(b0)); +signal3_out<=std_logic_vector(signed(sum_in((WordWidth+Bit_growth-1)+Q downto Q))*signed(b0)); + +sum_in<=std_logic_vector(-(signed(signal1_in)) - (signed( signal2_in)) + signed(signal3_in)); +sum_out<=std_logic_vector(signed(signal1_out)+ signed( signal2_out) + signed(signal3_out)); +REG1:fullregister +generic map( + N=>WordWidth+Bit_growth +) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enable, + clear=>clear, + d=>sum_in(WordWidth+Bit_growth+Q-1 downto Q), + q=>RegOut1 + ); +REG2:fullregister +generic map( + N=>WordWidth+Bit_growth +) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enable, + clear=>clear, + d=>RegOut1, + q=>RegOut2 + ); + +Reg_seg:fullregister +generic map( + N=>M+WordWidth+Bit_growth +) + port map ( + clk=>clk, + reset_n=>reset, + enable=>'1', + clear=>clear, + d=>sum_out, + q=>sum_out_aux + ); + + +signal_output<=sum_out_aux((WordWidth+Bit_growth-1)+Q downto Q);-----OJO + +end architecture; \ No newline at end of file
vhdl/WISHBONE_IIR/Tworder.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_IIR/fullregister.vhd =================================================================== --- vhdl/WISHBONE_IIR/fullregister.vhd (nonexistent) +++ vhdl/WISHBONE_IIR/fullregister.vhd (revision 5) @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity fullregister is + + generic + ( + N: integer + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + clear : in std_logic; + d : in std_logic_vector(N-1 downto 0); + q : out std_logic_vector(N-1 downto 0) + + ); + +end entity; + +architecture rtl of fullregister is +begin + + process (clk,reset_n,d,clear,enable) + + begin + if reset_n = '0' then + q <= (others=>'0'); + elsif (rising_edge(clk)) then + + if enable = '1' then + if clear='1' then + + q <= (others=>'0'); + + else + + q<=d; + + end if; + + + end if; + + end if; + + + end process; + +end rtl; \ No newline at end of file
vhdl/WISHBONE_IIR/fullregister.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_IIR/.vhd.bak =================================================================== --- vhdl/WISHBONE_IIR/.vhd.bak (nonexistent) +++ vhdl/WISHBONE_IIR/.vhd.bak (revision 5) @@ -0,0 +1,17 @@ +library ieee; +use ieee.math_real.all; + +package coeff_pkg is + constant Nb : integer := 16; + constant Q : integer := 14; + + type coeff is array (Nb-1 downto 0) of integer range -(2**(Nb-1)) to (2**(Nb-1)-1); + constant h0 : coeff := ( + 1579, + -3067, + 1579, + 16384, + -31076, + 14784 + ); +end coeff_pkg; Index: vhdl/WISHBONE_IIR/WB_SOS.vhd =================================================================== --- vhdl/WISHBONE_IIR/WB_SOS.vhd (nonexistent) +++ vhdl/WISHBONE_IIR/WB_SOS.vhd (revision 5) @@ -0,0 +1,171 @@ +library ieee; +--library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity WB_SOS is +generic (Filter_Width:integer:=16;--Filter width signals of in/out + WB_Width:integer:=32;--WishBone width signal of in/out + Bit_Growth:integer:=8; + NSECT:integer:=6;--Cant of sections + M:integer:=16;--width word of coefs + Q:integer:=13;--Q--Quantifer + Adress_wordwidth:integer:=32 ; + Adr_bas:integer:=9; + Reg_control:integer:=0; + Reg_data:integer:=4; + Reg_status:integer:=8; + Reg_Nsec:integer:=12; + Reg_gain: integer:=16; + Reg_coef:integer:=20 + + --Reg_coef:integer:=20 + --N_coef:integer:=42 + + ); + +port( + +DAT_I: in std_logic_vector(WB_Width-1 downto 0); +DAT_O:out std_logic_vector(WB_Width-1 downto 0); +ADR_I :in std_logic_vector(Adress_wordwidth-1 downto 0); +STB_I,RST_I,CLK_I,WE_I: in std_logic; +ACK_O: out std_logic; +clear:in std_logic +); +end entity; + +architecture RTL of WB_SOS is +--Structure SOS +component SOS is +generic (WordWidth:integer;--width signal of in/out + Bit_growth:integer; + NSECT:integer;--Cant of sections + M:integer;--width word of coefs + Q:integer--Q--Quantifer + + ); + +port( + +signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0); +h0: in std_logic_vector((NSECT*M*6)-1 downto 0); +gain: in std_logic_vector(M-1 downto 0); +signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0); +en_out : in std_logic_vector(3 downto 0); +enable_out:out std_logic; +clk,reset,clear,enable:in std_logic + +); end component; + +-- +component interface_slave_iir is +generic( + +Data_wordwidth: integer; +Adress_wordwidth: integer; +Adr_bas:integer; +Reg_control:integer; +Reg_data:integer; +Reg_status:integer; +Reg_coef:integer; +Reg_gain:integer; +Reg_Nsec:integer; +NSECT:integer; +--Offset_coef:integer; +M:integer + +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( Adress_wordwidth-1 downto 0 ); + DAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE + en_out: out std_logic_vector( 3 downto 0 );--to slave + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + Start: out std_logic;--to SLAVE + h0: out std_logic_vector( (NSECT*M*6)-1 downto 0 );--to SLAVE + gain: out std_logic_vector(M-1 downto 0); + enable_in: in std_logic; + clear,reset,clk: in std_logic + ); +end component; +signal h0_aux:std_logic_vector((NSECT*M*6)-1 downto 0); +signal gain_aux:std_logic_vector(M-1 downto 0); +signal iir_data_in, iir_data_out:std_logic_vector(Filter_Width+Bit_Growth-1 downto 0); +signal en_out_aux:std_logic_vector(3 downto 0); +signal Start_aux, WE_O_aux,enable_aux:std_logic; +signal sext:std_logic_vector(bit_growth-1 downto 0); +begin +sext<=(others=>iir_data_out(Filter_Width-1)); + +sos_1:SOS +generic map(WordWidth=>Filter_Width,--width signal of in/out + Bit_growth=>Bit_Growth, + NSECT=>NSECT,--Cant of sections + M=>M,--width word of coefs + Q=>Q--Quantifer + + ) + +port map( + +signal_input=>iir_data_in((Filter_Width+Bit_Growth)-1 downto 0), +--signal_input((WordWidth-(8*2))-1 downto 0)<=(others=>'0'), +h0=>h0_aux, +gain=>gain_aux, +signal_output=>iir_data_out, +en_out=>en_out_aux, +enable_out=>enable_aux, +clk=>CLK_I, +reset=>RST_I, +clear=>clear, +enable=>start_aux + +); + +inteface:interface_slave_iir +generic map( + +Data_wordwidth=>WB_Width, +Adress_wordwidth=>Adress_wordwidth, +Adr_bas=>Adr_bas, +Reg_control=>Reg_control, +Reg_data=>Reg_data, +Reg_status=>Reg_status, +Reg_coef=>Reg_coef, +Reg_gain=>Reg_gain, +Reg_Nsec=>Reg_Nsec, +NSECT=>NSECT, +--Offset_coef=>Offset_coef, +M=>M + +) +port map( + + + ACK_O=>ACK_O, + ADR_I=>ADR_I, + DAT_I=>DAT_I, + sDAT_I=>sext&iir_data_out, + DAT_O=>DAT_O, + sDAT_O((Filter_Width+Bit_Growth)-1 downto 0)=>iir_data_in, + en_out=>en_out_aux, + enable_in=>enable_aux, + STB_I=>STB_I, + WE_I=>WE_I, + Start=>Start_aux, + h0=>h0_aux, + gain=>gain_aux, + clear=>clear, + reset=>RST_I, + clk=>CLK_I + ); + + +end architecture; \ No newline at end of file
vhdl/WISHBONE_IIR/WB_SOS.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_IIR/interface_slave_iir.vhd =================================================================== --- vhdl/WISHBONE_IIR/interface_slave_iir.vhd (nonexistent) +++ vhdl/WISHBONE_IIR/interface_slave_iir.vhd (revision 5) @@ -0,0 +1,231 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity interface_slave_iir is +generic( + +Data_wordwidth: integer; +Adress_wordwidth: integer; +Adr_bas:integer; +Reg_control:integer; +Reg_data:integer; +Reg_status:integer; +Reg_coef:integer; +Reg_gain:integer; +Reg_Nsec:integer; +NSECT:integer; +M:integer + +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( Adress_wordwidth-1 downto 0 ); + DAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE + en_out: out std_logic_vector( 3 downto 0 );--to slave + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + Start: out std_logic;--to SLAVE + h0: out std_logic_vector( (NSECT*M*6)-1 downto 0 );--to SLAVE + gain: out std_logic_vector(M-1 downto 0); + enable_in: in std_logic; + clear,reset,clk: in std_logic + ); +end entity; + +architecture RTL of interface_slave_iir is + +--The fullregister component +component fullregister is + + generic + ( + N: integer + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + clear : in std_logic; + d : in std_logic_vector(N-1 downto 0); + q : out std_logic_vector(N-1 downto 0) + + ); +end component; + +signal OUT_AUX, ZERO,ssDAT_O,RegsDAT_O: std_logic_vector( Data_wordwidth-1 downto 0 ); +signal rSTATUS_O,enable_in_aux:std_logic_vector( 0 downto 0 ); +signal Clear_Status:std_logic; +signal enable_gain:std_logic; +signal EN_ZERO: std_logic_vector(3 downto 0); + +type array_aux is array(6*NSECT downto 0) of std_logic_vector(M-1 downto 0); +signal h0_aux:array_aux; + +signal gains: std_logic_vector(M-1 downto 0); + +type array_aux1 is array(6*NSECT downto 0) of std_logic; +signal enables:array_aux1; + +begin + ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth)); + + EN_ZERO<=std_logic_vector(to_unsigned(0,4)); + OUT_AUX<=DAT_I; + ACK_O<=STB_I; + enable_in_aux(0)<=enable_in; + --DAT_O<=sDAT_I; + coefficients: + for k in 6*NSECT-1 downto 0 generate + + enables(k)<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned((4*k)+Reg_coef,8))) else + '0'; + + coefs:fullregister + generic map( + N=>M + ) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enables(k), + clear=>clear, + d=>OUT_AUX(M-1 downto 0), + q=>h0_aux(k) + ); + h0((k+1)*M-1 downto k*M)<=std_logic_vector(h0_aux(k)); + + end generate; + + + + process(ADR_I,STB_I,WE_I,ZERO,EN_ZERO,OUT_AUX,rSTATUS_O) + begin + + if (WE_I='1' and STB_I='1') then--ESCRIBIR EN EL FILTRO + case ADR_I(7 downto 0) is + + when std_logic_vector(to_unsigned(Reg_control,8)) => start<='1'; + DAT_O<=ZERO; + Clear_Status<='0'; + + when std_logic_vector(to_unsigned(Reg_status,8))=> Clear_Status<='1'; + DAT_O<=ZERO; + start<='0'; + when OTHERS => start<='0'; + DAT_O<=ZERO; + Clear_Status<='0'; + end case; + elsif (WE_I='0' and STB_I='1') then + case ADR_I(7 downto 0) is --LEER EL FILTRO + when std_logic_vector(to_unsigned(Reg_data,8)) => + + DAT_O<=RegsDAT_O; + start<='0'; + + Clear_Status<='0'; + + when std_logic_vector(to_unsigned(Reg_status,8)) => DAT_O(0)<=rSTATUS_O(0); + DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1); + start<='0'; + + Clear_Status<='0'; + when OTHERS => start<='0'; + + --DAT_O(M-1 downto 0)<= h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4); + --DAT_O(Data_wordwidth-1 downto M)<=(others => h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4)(M-1) ); + + --DAT_O<=ssDAT_O; + + DAT_O(M-1 downto 0)<= gains; + DAT_O(Data_wordwidth-1 downto M)<=(others => gains(M-1) ); + + + + Clear_Status<='0'; + end case; + + + else + start<='0'; + DAT_O<=ZERO; + Clear_Status<='0'; + end if; + + end process; + + process(ADR_I,STB_I,WE_I,OUT_AUX) + begin + if rising_edge(clk) then + + if (WE_I='1' and STB_I='1') then + if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(reg_data,8)) then + ssDAT_O<=OUT_AUX; + end if; + if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_Nsec,8)) then + en_out<=OUT_AUX(3 downto 0); + end if; + + end if; + end if; + + + end process; + + Reg_Stat:fullregister + generic map( + N=>1 + ) + port map ( + clk=>clk, + reset_n=>reset, + enable=>(enable_in or Clear_Status), + clear=>Clear_Status, + d=>enable_in_aux, + q=>rSTATUS_O + ); + Reg_sDat_O:fullregister + generic map( + N=>Data_wordwidth + ) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enable_in , + clear=>clear, + d=>sDAT_I, + q=>RegsDAT_O + ); + + sDAT_O<=ssDAT_O; + + --Registro para gain + + enable_gain<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_gain,8))) else + '0'; + gainreg:fullregister + generic map( + N=>M + ) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enable_gain, + clear=>clear, + d=>DAT_I(M-1 downto 0), + q=>gains + ); + + gain<=gains; + +end architecture; + + +
vhdl/WISHBONE_IIR/interface_slave_iir.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/comp_mult.vhd =================================================================== --- vhdl/WISHBONE_FFT/comp_mult.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/comp_mult.vhd (revision 5) @@ -0,0 +1,97 @@ +--Since both the real and imaginary values have the same number of fractio nal bits, +-- there is no need to truncate. + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity comp_mult is + +generic ( inst_width1 : INTEGER := 14; + inst_width2 : INTEGER := 14 + ); + +port ( Re1 : in std_logic_vector(inst_width1-1 downto 0); + Im1 : in std_logic_vector(inst_width1-1 downto 0); + Re2 : in std_logic_vector(inst_width2-1 downto 0); + Im2 : in std_logic_vector(inst_width2-1 downto 0); + Re : out std_logic_vector(inst_width1 + inst_width2 downto 0); + Im : out std_logic_vector(inst_width1 + inst_width2 downto 0) + +); +end comp_mult; + +architecture behavior of comp_mult is +--multiplier outputs +signal product1 :std_logic_vector(inst_width1+inst_width2-1 downto 0);--re1*re2 +signal product2 :std_logic_vector(inst_width1+inst_width2-1 downto 0);--i m1*im2 +signal product3 :std_logic_vector(inst_width1+inst_width2-1 downto 0); +signal product4 :std_logic_vector(inst_width1+inst_width2-1 downto 0); + + + +component adder + generic (inst_width:integer); + port ( + inst_A : in std_logic_vector(inst_width-1 downto 0); + inst_B : in std_logic_vector(inst_width-1 downto 0); + SUM : out std_logic_vector(inst_width downto 0) + ); + +end component; + + +component subtract + generic (inst_width:integer); + port ( + inst_A : in std_logic_vector(inst_width-1 downto 0); + inst_B : in std_logic_vector(inst_width-1 downto 0); + DIFF : out std_logic_vector(inst_width downto 0) + ); +end component; + +component multiplier + generic (inst_width1:integer ; + inst_width2:integer + ); + port ( + inst_A : in std_logic_vector(inst_width1-1 downto 0); + inst_B : in std_logic_vector(inst_width2-1 downto 0); + PRODUCT_inst : out +std_logic_vector(inst_width1+inst_width2-1 downto 0) + ); +end component; + + +begin + + U1 : multiplier + generic map( inst_width1=> inst_width1, +inst_width2=>inst_width2) + port map ( inst_A => Re1, inst_B => Re2, PRODUCT_inst => +product1 ); + + U2 : multiplier + generic map( inst_width1=>inst_width1, +inst_width2=>inst_width2) + port map ( inst_A => Im1, inst_B => Im2, PRODUCT_inst => +product2 ); + + U3 : multiplier + generic map( inst_width1=>inst_width1, +inst_width2=>inst_width2) + port map( inst_A => Re1, inst_B => Im2, PRODUCT_inst =>product3 ); + + U4 : multiplier + generic map( inst_width1=>inst_width2, inst_width2=>inst_width1) + port map ( inst_A => Re2, inst_B => Im1, PRODUCT_inst =>product4); + + U5 : subtract + generic map ( inst_width=>inst_width1+inst_width2) + port map(inst_A => product1, inst_B => product2, DIFF => Re ); + + U6 : adder + generic map ( inst_width=>inst_width1+inst_width2) + port map ( inst_A => product3, inst_B => product4, SUM =>Im ); + +end;
vhdl/WISHBONE_FFT/comp_mult.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/FFT_WB.vhd =================================================================== --- vhdl/WISHBONE_FFT/FFT_WB.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/FFT_WB.vhd (revision 5) @@ -0,0 +1,143 @@ +library ieee; +library work; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + + +entity FFT_WB is +generic (WB_Width:integer:=32;--Filter width signals of in/out + Adress_wordwidth:integer:=32 ; + N:integer:=1024;--width word of coefs + reg_control:integer:=0; + reg_data:integer:=4; + reg_status:integer:=8; + reg_memory:integer:=12 + + ); + +port( +DAT_I: in std_logic_vector(WB_Width-1 downto 0); +DAT_O:out std_logic_vector(WB_Width-1 downto 0); +ADR_I :in std_logic_vector(Adress_wordwidth-1 downto 0); +STB_I,RST_I,CLK_I,WE_I: in std_logic; +ACK_O: out std_logic +); +end entity; + + +architecture RTL of FFT_WB is + + +component fft_core_pipeline1 is + generic ( + input_width : integer :=16; + twiddle_width : integer :=16; + N : integer :=1024; + add_g : integer:=0;--1; --Either 0 or 1 only. + mult_g : integer:=0--9 --Can be any number from 0 to twiddle_width+1 + ); + port ( clock : in std_logic; + resetn : in std_logic; + enable : in std_logic; + clear : in std_logic; + enable_out: out std_logic; + frame_ready: out std_logic; + index : out std_logic_vector(integer(ceil(log2(real((N)))))-1 downto 0); + xin_r : in std_logic_vector(input_width-1 downto 0); + xin_i : in std_logic_vector(input_width-1 downto 0); + Xout_r : out std_logic_vector (input_width+((integer(ceil(log2(real((N)))))-1)/2)*mult_g+integer(ceil(log2(real((N)))))*add_g-1 downto 0); + Xout_i : out std_logic_vector (input_width+((integer(ceil(log2(real((N)))))-1)/2)*mult_g+integer(ceil(log2(real((N)))))*add_g-1 downto 0) + ); +end component; + +component interface_slave_fft is +generic( +N: integer; +data_wordwidth: integer; +adress_wordwidth: integer; +reg_control:integer; +reg_data:integer; +reg_status:integer; +reg_memory:integer + + +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( adress_wordwidth-1 downto 0 ); + ADR_FFT: in std_logic_vector( integer(ceil(log2(real(N))))-1 downto 0 ); + DAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + FFT_finish_in: in std_logic;--from SLAVE + FFT_enable: out std_logic;--to SLAVE + enable_in: in std_logic;--from SLAVE + clear_out: out std_logic;--to SLAVE + clk: in std_logic + ); +end component; + +signal index_aux: std_logic_vector(integer(ceil(log2(real(N))))-1 downto 0); +signal frame_ready_aux,enable_out_aux,FFT_enable_aux,clear_aux:std_logic; +signal Data1_aux,Data2_aux: std_logic_vector(WB_Width-1 downto 0); +begin + +--Instancia del FFT-Core +FFT: fft_core_pipeline1 + generic map( + input_width=>WB_Width/2, + twiddle_width=>WB_Width/2, + N=>N, + add_g=>0, + mult_g=>0 + ) + port map( + clock=>CLK_I, + resetn=>RST_I, + enable=>FFT_enable_aux, + clear=>clear_aux, + enable_out=>enable_out_aux, + frame_ready=>frame_ready_aux, + index=>index_aux, + xin_r=>Data1_aux(WB_Width-1 downto WB_Width/2), + xin_i=>Data1_aux((WB_Width/2)-1 downto 0), + Xout_r=>Data2_aux(WB_Width-1 downto WB_Width/2), + Xout_i=>Data2_aux((WB_Width/2)-1 downto 0) + ); + + --Instancia de interfaz con arbitro Wishbone + Interface: interface_slave_fft +generic map( +N=>N, +data_wordwidth=>WB_Width, +adress_wordwidth=>Adress_wordwidth, +reg_control=>reg_control, +reg_data=>reg_data, +reg_status=>reg_status, +reg_memory=>reg_memory +) +port map( + ACK_O=>ACK_O, + ADR_I=>ADR_I, + ADR_FFT=>index_aux, + DAT_I=>DAT_I, + sDAT_I=>Data2_aux, + DAT_O=>DAT_O, + sDAT_O=>Data1_aux, + STB_I=>STB_I, + WE_I=>WE_I, + FFT_finish_in=>frame_ready_aux, + FFT_enable=>FFT_enable_aux, + enable_in=>enable_out_aux, + clear_out=>clear_aux, + clk=>CLK_I + ); + + end architecture; \ No newline at end of file
vhdl/WISHBONE_FFT/FFT_WB.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/stage_II_last.vhd =================================================================== --- vhdl/WISHBONE_FFT/stage_II_last.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/stage_II_last.vhd (revision 5) @@ -0,0 +1,149 @@ +--Component for Stages using BF2II (last stage only) +--When BF2II is the last butterfly, there is no multiplier after it +--Input is a standar d logic vector of data_width -add_g +--data_width - wid th of the internal busses +--add_g - Add growth variable - if 1, data_width grows by 1, if 0 then - 0 + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity stage_II_last is +generic ( + data_width : INTEGER :=14; + add_g : INTEGER := 1 + ); + +port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + t :in std_logic; + s :in std_logic; + clock : in std_logic; + enable : in std_logic; + resetn : in std_logic ; + tonext_r :out std_logic_vector(data_width -1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); + +end stage_II_last; + +architecture structure of stage_II_last is +signal toreg_r : std_logic_vector(data_width-1 downto 0); +signal toreg_i : std_logic_vector(data_width-1 downto 0); +signal fromreg_r : std_logic_vector( data_width-1 downto 0); +signal fromreg_i : std_logic_vector( data_width-1 downto 0); + +signal tonext_r_aux : std_logic_vector(data_width-1 downto 0); +signal tonext_i_aux : std_logic_vector(data_width-1 downto 0); + + +component shiftreg1 + generic ( + data_width : integer + ); + port ( + clock : IN std_logic; + enable : in std_logic; + clear : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0 ); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); +end component; + +component BF2II + generic ( + data_width : INTEGER; + add_g: INTEGER + ); + port ( + fromreg_r :in std_logic_vector(data_width-1 downto 0); + fromreg_i :in std_logic_vector(data_width-1 downto 0); + prvs_r :in std_logic_vector(data_width-add_g-1 downto 0); + prvs_i :in std_logic_vector(data_width-add_g-1 downto 0); + t : in std_logic; + s : in std_logic; + toreg_r :out std_logic_vector(data_width-1 downto 0); + toreg_i : out std_logic_vector(data_width-1 downto 0); + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); +end component; + +begin +regr : shiftreg1 + generic map ( + data_width=>data_width + ) + port map ( + clock=>clock, + enable=>enable, + clear =>'0', + read_data=>fromreg_r, + write_data=>toreg_r, + resetn=>resetn + ); + +regi : shiftreg1 + generic map ( + data_width=>data_width + ) + port map ( + clock=>clock, + enable=>enable, + clear =>'0', + read_data=>fromreg_i, + write_data=>toreg_i, + resetn=>resetn + ); + +btrfly : BF2II + generic map ( + data_width=>data_width, + add_g=>add_g + ) + port map ( + fromreg_r=>fromreg_r, + fromreg_i=>fromreg_i, + prvs_r=>prvs_r, + prvs_i=>prvs_i, + t=>t, + s=>s, + toreg_r=>toreg_r, + toreg_i=>toreg_i, + tonext_r=>tonext_r_aux, + tonext_i=>tonext_i_aux + ); + + + +regsegr : shiftreg1 + generic map ( + data_width=>data_width + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_r, + write_data=>tonext_r_aux, + resetn=>resetn + ); + +regsegi : shiftreg1 + generic map ( + data_width=>data_width + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_i, + write_data=>tonext_i_aux, + resetn=>resetn + ); + +end;
vhdl/WISHBONE_FFT/stage_II_last.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/RAM_Memory.vhd =================================================================== --- vhdl/WISHBONE_FFT/RAM_Memory.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/RAM_Memory.vhd (revision 5) @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity RAM_Memory is +generic( + +Add_WordWidth: integer:=10; +Data_WordWidth: integer:=32 +); +port( + DATi: in std_logic_vector( Data_WordWidth-1 downto 0 ); + DATo: out std_logic_vector( Data_WordWidth-1 downto 0 ); + ADR_WB: in std_logic_vector( Add_WordWidth-1 downto 0 ); + ADR_FFT: in std_logic_vector( Add_WordWidth-1 downto 0 ); + W_R: in std_logic; + clk: in std_logic + ); +end entity; + +architecture RTL of RAM_Memory is + +type array_aux is array((2**Add_WordWidth)-1 downto 0) of std_logic_vector(Data_WordWidth-1 downto 0); +signal mem:array_aux; +signal reg0: std_logic_vector(Data_WordWidth-1 downto 0); +begin +process(clk) +begin + if rising_edge(clk) then + + if ( W_R='1') then + mem(to_integer(unsigned(ADR_FFT)))<=DATi ; + end if; + + + --DATo<=reg0; + DATo <= mem(to_integer(unsigned(ADR_WB))); + + end if; + + + + +end process; +end architecture; \ No newline at end of file
vhdl/WISHBONE_FFT/RAM_Memory.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/FFT_WBtest.vhd =================================================================== --- vhdl/WISHBONE_FFT/FFT_WBtest.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/FFT_WBtest.vhd (revision 5) @@ -0,0 +1,120 @@ +library ieee; +library work; +--use work.fft_pkg.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + + +entity FFT_WBtest is +generic (WB_Width:integer:=32;--Filter width signals of in/out + Adress_wordwidth:integer:=32 ; + N:integer:=1024;--width word of coefs + reg_control:integer:=0; + reg_data:integer:=4; + reg_status:integer:=8; + reg_memory:integer:=12 + + ); + +port( +DAT_I: in std_logic_vector(WB_Width-1 downto 0); +DAT_O:out std_logic_vector(WB_Width-1 downto 0); +ADR_I :in std_logic_vector(Adress_wordwidth-1 downto 0); +STB_I,RST_I,CLK_I,WE_I: in std_logic; +ACK_O: out std_logic +); +end entity; + + +architecture RTL of FFT_WBtest is + + +component fft_core_pipeline1 is + generic ( + input_width : integer :=16; + twiddle_width : integer :=16; + N : integer :=1024; + add_g : integer:=0;--1; --Either 0 or 1 only. + mult_g : integer:=0--9 --Can be any number from 0 to twiddle_width+1 + ); + port ( clock : in std_logic; + resetn : in std_logic; + enable : in std_logic; + clear : in std_logic; + enable_out: out std_logic; + frame_ready: out std_logic; + index : out std_logic_vector(integer(ceil(log2(real((N)))))-1 downto 0); + xin_r : in std_logic_vector(input_width-1 downto 0); + xin_i : in std_logic_vector(input_width-1 downto 0); + Xout_r : out std_logic_vector (input_width+((integer(ceil(log2(real((N)))))-1)/2)*mult_g+integer(ceil(log2(real((N)))))*add_g-1 downto 0); + Xout_i : out std_logic_vector (input_width+((integer(ceil(log2(real((N)))))-1)/2)*mult_g+integer(ceil(log2(real((N)))))*add_g-1 downto 0) + ); +end component; + +component interface_slave_fft is +generic( +N: integer; +data_wordwidth: integer; +adress_wordwidth: integer; +reg_control:integer; +reg_data:integer; +reg_status:integer; +reg_memory:integer + + +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( adress_wordwidth-1 downto 0 ); + ADR_FFT: in std_logic_vector( integer(ceil(log2(real((N)))))-1 downto 0 ); + DAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + FFT_finish_in: in std_logic;--from SLAVE + FFT_enable: out std_logic;--to SLAVE + enable_in: in std_logic;--from SLAVE + clear_out: out std_logic;--to SLAVE + clk: in std_logic + ); +end component; + +signal index_aux: std_logic_vector(integer(ceil(log2(real(N))))-1 downto 0); +signal frame_ready_aux,enable_out_aux,FFT_enable_aux,clear_aux:std_logic; +signal Data1_aux,Data2_aux: std_logic_vector(WB_Width-1 downto 0); +begin + + + Interface: interface_slave_fft +generic map( +N=>N, +data_wordwidth=>WB_Width, +adress_wordwidth=>Adress_wordwidth, +reg_control=>reg_control, +reg_data=>reg_data, +reg_status=>reg_status, +reg_memory=>reg_memory +) +port map( + ACK_O=>ACK_O, + ADR_I=>ADR_I, + ADR_FFT=>std_logic_vector(unsigned(ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0))-(reg_memory))(integer(ceil(log2(real((N)))))+1 downto 2), + DAT_I=>DAT_I, + sDAT_I=>DAT_I, + DAT_O=>DAT_O, + sDAT_O=>Data1_aux, + STB_I=>STB_I, + WE_I=>WE_I, + FFT_finish_in=>frame_ready_aux, + FFT_enable=>FFT_enable_aux, + enable_in=>WE_I, + clear_out=>clear_aux, + clk=>CLK_I + ); + + end architecture; \ No newline at end of file Index: vhdl/WISHBONE_FFT/counterhle.vhd =================================================================== --- vhdl/WISHBONE_FFT/counterhle.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/counterhle.vhd (revision 5) @@ -0,0 +1,46 @@ +--Counter with resetn and load enable +--When load enable is high, it counts. +--When load enable is low, it stops counting. +--When a reset is triggered, it resets to zero. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + +entity counterhle is + generic ( + width: integer :=3 + ); + port ( + clock : in std_logic; + resetn : in std_logic; + enable : in std_logic; + clear : in std_logic; + countout : out std_logic_vector(width-1 downto 0) + + ); +end counterhle; + +architecture behavior of counterhle is +signal count : std_logic_vector(width-1 downto 0); + +begin +process(clock,resetn,enable) +begin + if (resetn='0')then + count <= (others => '0'); + + elsif (clock'event and clock='1') then + if (enable = '1' ) then + if (clear = '1') then + count <= (others => '0'); + else + count <= unsigned(count) + '1'; + end if; + end if; + + end if ; +end process; +countout <= count; + +end;
vhdl/WISHBONE_FFT/counterhle.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/mux2_mmw.vhd =================================================================== --- vhdl/WISHBONE_FFT/mux2_mmw.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/mux2_mmw.vhd (revision 5) @@ -0,0 +1,34 @@ + +--Special 2 to 1 mux (mismatched width) +--7/17/02 +-- First input is data_width bits +--Second input is data_width+1 bits +--Ign ores highest bit of second input +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY mux2_mmw IS + GENERIC( data_width : integer := 35 + ); + PORT ( s : in std_logic; + in0 : in std_logic_vector(data_width-1 downto 0); + in1: in std_logic_vector(data_width downto 0); + data: out std_logic_vector(data_width-1 downto 0) + ); +END mux2_mmw ; + +-- hds interface_end +ARCHITECTURE behavior OF mux2_mmw IS +BEGIN +process(in0,in1,s) +begin + if s='0' then + data<=in0; + else + data<=in1(data_width-1 downto 0); + end if; +end process; +END behavior; +
vhdl/WISHBONE_FFT/mux2_mmw.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/stage_I.vhd =================================================================== --- vhdl/WISHBONE_FFT/stage_I.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/stage_I.vhd (revision 5) @@ -0,0 +1,162 @@ +--Component for Stages using BF2I (first and every odd stage) +--Doesn't handle last stage +--Input is a standard logic vector of data_width-add_g +--data_width - width of the internal busses +--add_g - Add growth variable - if 1, data _width grows by 1, if 0 then 0 +-- t_stages number of shift -shif register stages + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity stage_I is +generic ( + data_width : INTEGER :=13; + add_g : INTEGER := 1; + shift_stages : INTEGER := 32 + ); +port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + s :in std_logic; + clock : in std_logic; + resetn : in std_logic; + enable : in std_logic; + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); +end stage_I; + +architecture structure of stage_I is + +signal toreg_r : std_logic_vector(data_width-1 downto 0); +signal toreg_i : std_logic_vector(data_width-1 downto 0); +signal fromreg_r : std_logic_vector(data_width-1 downto 0); +signal fromreg_i : std_logic_vector(data_width-1 downto 0); + +signal tonext_r_aux : std_logic_vector(data_width-1 downto 0); +signal tonext_i_aux : std_logic_vector(data_width-1 downto 0); + +component shiftregN + generic ( + data_width : integer; + n : integer + ); + port ( + clock : IN std_logic; + enable : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0 ); + resetn : IN std_logic + ); +end component; + +component shiftreg1 + generic ( + data_width : integer +); + port ( + clock : IN std_logic; + enable: in std_logic; + clear: in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); +end component; + + +component BF2I + generic ( + data_width : INTEGER; + add_g: INTEGER + ); + port ( + fromreg_r :in std_logic_vector(data_width-1 downto 0); + fromreg_i :in std_logic_vector(data_width-1 downto 0); + prvs_r :in std_logic_vector(data_width-add_g-1 downto 0 ); + prvs_i :in std_logic_vector(data_width-add_g-1 downto 0); + s : in std_logic; + toreg_r :out std_logic_vector(data_width-1 downto 0); + toreg_i :out std_logic_vector(data_width-1 downto 0); + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); +end component; + +begin +regr : shiftregN + generic map ( + data_width=>data_width, + n=>shift_stages + ) + port map ( +clock=>clock, +enable=>enable, +read_data=>fromreg_r, +write_data=>toreg_r, +resetn=>resetn +); + +regi : shiftregN + generic map ( + data_width=>data_width, + n=>shift_stages + ) +port map ( + clock=>clock, + enable=>enable, + read_data=>fromreg_i, + write_data=>toreg_i, + resetn=>resetn + ); + +btrfly : BF2I + generic map ( + data_width=>data_width, + add_g=>add_g + ) + port map ( + fromreg_r=>fromreg_r, + fromreg_i=>fromreg_i, + prvs_r=>prvs_r, + prvs_i=>prvs_i, + s=>s, + toreg_r=>toreg_r, + toreg_i=>toreg_i, + tonext_r=>tonext_r_aux, + tonext_i=>tonext_i_aux + ); + + +regsegr : shiftreg1 + generic map ( + data_width=>data_width + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_r, + write_data=>tonext_r_aux, + resetn=>resetn + ); + +regsegi : shiftreg1 + generic map ( + data_width=>data_width + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_i, + write_data=>tonext_i_aux, + resetn=>resetn + ); + + +end; +
vhdl/WISHBONE_FFT/stage_I.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/rom1.vhd =================================================================== --- vhdl/WISHBONE_FFT/rom1.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/rom1.vhd (revision 5) @@ -0,0 +1,1061 @@ +-- Rom file for twiddle factors +-- ../../../rtl/vhdl/WISHBONE_FFT/rom1.vhd contains 1024 points of 16 width +-- for a 1024 point fft. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY rom1 IS + GENERIC( + data_width : integer :=16; + address_width : integer :=10 + ); + PORT( + clk :in std_logic; + address :in std_logic_vector (9 downto 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0) ; + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end rom1; +ARCHITECTURE behavior OF rom1 IS + + BEGIN + +process (address,clk) +begin + if(rising_edge(clk)) then + case address is + when "0000000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "0000000001" => datar <= "0111111111111101";datai <= "1111111001101110"; --2 + when "0000000010" => datar <= "0111111111110101";datai <= "1111110011011100"; --4 + when "0000000011" => datar <= "0111111111101001";datai <= "1111101101001010"; --6 + when "0000000100" => datar <= "0111111111011000";datai <= "1111100110111000"; --8 + when "0000000101" => datar <= "0111111111000001";datai <= "1111100000100111"; --10 + when "0000000110" => datar <= "0111111110100110";datai <= "1111011010010110"; --12 + when "0000000111" => datar <= "0111111110000110";datai <= "1111010100000101"; --14 + when "0000001000" => datar <= "0111111101100001";datai <= "1111001101110100"; --16 + when "0000001001" => datar <= "0111111100110111";datai <= "1111000111100100"; --18 + when "0000001010" => datar <= "0111111100001001";datai <= "1111000001010101"; --20 + when "0000001011" => datar <= "0111111011010101";datai <= "1110111011000110"; --22 + when "0000001100" => datar <= "0111111010011100";datai <= "1110110100111000"; --24 + when "0000001101" => datar <= "0111111001011111";datai <= "1110101110101011"; --26 + when "0000001110" => datar <= "0111111000011101";datai <= "1110101000011110"; --28 + when "0000001111" => datar <= "0111110111010101";datai <= "1110100010010010"; --30 + when "0000010000" => datar <= "0111110110001001";datai <= "1110011100000111"; --32 + when "0000010001" => datar <= "0111110100111001";datai <= "1110010101111110"; --34 + when "0000010010" => datar <= "0111110011100011";datai <= "1110001111110101"; --36 + when "0000010011" => datar <= "0111110010001000";datai <= "1110001001101101"; --38 + when "0000010100" => datar <= "0111110000101001";datai <= "1110000011100110"; --40 + when "0000010101" => datar <= "0111101111000101";datai <= "1101111101100001"; --42 + when "0000010110" => datar <= "0111101101011100";datai <= "1101110111011101"; --44 + when "0000010111" => datar <= "0111101011101110";datai <= "1101110001011010"; --46 + when "0000011000" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "0000011001" => datar <= "0111101000000101";datai <= "1101100101011000"; --50 + when "0000011010" => datar <= "0111100110001001";datai <= "1101011111011010"; --52 + when "0000011011" => datar <= "0111100100001001";datai <= "1101011001011101"; --54 + when "0000011100" => datar <= "0111100010000100";datai <= "1101010011100001"; --56 + when "0000011101" => datar <= "0111011111111010";datai <= "1101001101100111"; --58 + when "0000011110" => datar <= "0111011101101011";datai <= "1101000111101111"; --60 + when "0000011111" => datar <= "0111011011011000";datai <= "1101000001111001"; --62 + when "0000100000" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "0000100001" => datar <= "0111010110100101";datai <= "1100110110010010"; --66 + when "0000100010" => datar <= "0111010100000100";datai <= "1100110000100001"; --68 + when "0000100011" => datar <= "0111010001011111";datai <= "1100101010110011"; --70 + when "0000100100" => datar <= "0111001110110101";datai <= "1100100101000110"; --72 + when "0000100101" => datar <= "0111001100000111";datai <= "1100011111011100"; --74 + when "0000100110" => datar <= "0111001001010100";datai <= "1100011001110100"; --76 + when "0000100111" => datar <= "0111000110011101";datai <= "1100010100001110"; --78 + when "0000101000" => datar <= "0111000011100010";datai <= "1100001110101010"; --80 + when "0000101001" => datar <= "0111000000100010";datai <= "1100001001001000"; --82 + when "0000101010" => datar <= "0110111101011110";datai <= "1100000011101001"; --84 + when "0000101011" => datar <= "0110111010010110";datai <= "1011111110001101"; --86 + when "0000101100" => datar <= "0110110111001001";datai <= "1011111000110010"; --88 + when "0000101101" => datar <= "0110110011111000";datai <= "1011110011011011"; --90 + when "0000101110" => datar <= "0110110000100011";datai <= "1011101110000110"; --92 + when "0000101111" => datar <= "0110101101001010";datai <= "1011101000110011"; --94 + when "0000110000" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "0000110001" => datar <= "0110100110001011";datai <= "1011011110010111"; --98 + when "0000110010" => datar <= "0110100010100110";datai <= "1011011001001100"; --100 + when "0000110011" => datar <= "0110011110111100";datai <= "1011010100000101"; --102 + when "0000110100" => datar <= "0110011011001111";datai <= "1011001111000001"; --104 + when "0000110101" => datar <= "0110010111011101";datai <= "1011001001111111"; --106 + when "0000110110" => datar <= "0110010011101000";datai <= "1011000101000001"; --108 + when "0000110111" => datar <= "0110001111101110";datai <= "1011000000000101"; --110 + when "0000111000" => datar <= "0110001011110001";datai <= "1010111011001101"; --112 + when "0000111001" => datar <= "0110000111110000";datai <= "1010110110011000"; --114 + when "0000111010" => datar <= "0110000011101011";datai <= "1010110001100101"; --116 + when "0000111011" => datar <= "0101111111100011";datai <= "1010101100110111"; --118 + when "0000111100" => datar <= "0101111011010111";datai <= "1010101000001011"; --120 + when "0000111101" => datar <= "0101110111000111";datai <= "1010100011100011"; --122 + when "0000111110" => datar <= "0101110010110011";datai <= "1010011110111110"; --124 + when "0000111111" => datar <= "0101101110011100";datai <= "1010011010011100"; --126 + when "0001000000" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "0001000001" => datar <= "0101100101100100";datai <= "1010010001100100"; --130 + when "0001000010" => datar <= "0101100001000010";datai <= "1010001101001101"; --132 + when "0001000011" => datar <= "0101011100011101";datai <= "1010001000111001"; --134 + when "0001000100" => datar <= "0101010111110101";datai <= "1010000100101001"; --136 + when "0001000101" => datar <= "0101010011001001";datai <= "1010000000011101"; --138 + when "0001000110" => datar <= "0101001110011011";datai <= "1001111100010101"; --140 + when "0001000111" => datar <= "0101001001101000";datai <= "1001111000010000"; --142 + when "0001001000" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "0001001001" => datar <= "0100111111111011";datai <= "1001110000010010"; --146 + when "0001001010" => datar <= "0100111010111111";datai <= "1001101100011000"; --148 + when "0001001011" => datar <= "0100110110000001";datai <= "1001101000100011"; --150 + when "0001001100" => datar <= "0100110000111111";datai <= "1001100100110001"; --152 + when "0001001101" => datar <= "0100101011111011";datai <= "1001100001000100"; --154 + when "0001001110" => datar <= "0100100110110100";datai <= "1001011101011010"; --156 + when "0001001111" => datar <= "0100100001101001";datai <= "1001011001110101"; --158 + when "0001010000" => datar <= "0100011100011100";datai <= "1001010110010011"; --160 + when "0001010001" => datar <= "0100010111001101";datai <= "1001010010110110"; --162 + when "0001010010" => datar <= "0100010001111010";datai <= "1001001111011101"; --164 + when "0001010011" => datar <= "0100001100100101";datai <= "1001001100001000"; --166 + when "0001010100" => datar <= "0100000111001110";datai <= "1001001000110111"; --168 + when "0001010101" => datar <= "0100000001110011";datai <= "1001000101101010"; --170 + when "0001010110" => datar <= "0011111100010111";datai <= "1001000010100010"; --172 + when "0001010111" => datar <= "0011110110111000";datai <= "1000111111011110"; --174 + when "0001011000" => datar <= "0011110001010110";datai <= "1000111100011110"; --176 + when "0001011001" => datar <= "0011101011110010";datai <= "1000111001100011"; --178 + when "0001011010" => datar <= "0011100110001100";datai <= "1000110110101100"; --180 + when "0001011011" => datar <= "0011100000100100";datai <= "1000110011111001"; --182 + when "0001011100" => datar <= "0011011010111010";datai <= "1000110001001011"; --184 + when "0001011101" => datar <= "0011010101001101";datai <= "1000101110100001"; --186 + when "0001011110" => datar <= "0011001111011111";datai <= "1000101011111100"; --188 + when "0001011111" => datar <= "0011001001101110";datai <= "1000101001011011"; --190 + when "0001100000" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "0001100001" => datar <= "0010111110000111";datai <= "1000100100101000"; --194 + when "0001100010" => datar <= "0010111000010001";datai <= "1000100010010101"; --196 + when "0001100011" => datar <= "0010110010011001";datai <= "1000100000000110"; --198 + when "0001100100" => datar <= "0010101100011111";datai <= "1000011101111100"; --200 + when "0001100101" => datar <= "0010100110100011";datai <= "1000011011110111"; --202 + when "0001100110" => datar <= "0010100000100110";datai <= "1000011001110111"; --204 + when "0001100111" => datar <= "0010011010101000";datai <= "1000010111111011"; --206 + when "0001101000" => datar <= "0010010100101000";datai <= "1000010110000100"; --208 + when "0001101001" => datar <= "0010001110100110";datai <= "1000010100010010"; --210 + when "0001101010" => datar <= "0010001000100011";datai <= "1000010010100100"; --212 + when "0001101011" => datar <= "0010000010011111";datai <= "1000010000111011"; --214 + when "0001101100" => datar <= "0001111100011010";datai <= "1000001111010111"; --216 + when "0001101101" => datar <= "0001110110010011";datai <= "1000001101111000"; --218 + when "0001101110" => datar <= "0001110000001011";datai <= "1000001100011101"; --220 + when "0001101111" => datar <= "0001101010000010";datai <= "1000001011000111"; --222 + when "0001110000" => datar <= "0001100011111001";datai <= "1000001001110111"; --224 + when "0001110001" => datar <= "0001011101101110";datai <= "1000001000101011"; --226 + when "0001110010" => datar <= "0001010111100010";datai <= "1000000111100011"; --228 + when "0001110011" => datar <= "0001010001010101";datai <= "1000000110100001"; --230 + when "0001110100" => datar <= "0001001011001000";datai <= "1000000101100100"; --232 + when "0001110101" => datar <= "0001000100111010";datai <= "1000000100101011"; --234 + when "0001110110" => datar <= "0000111110101011";datai <= "1000000011110111"; --236 + when "0001110111" => datar <= "0000111000011100";datai <= "1000000011001001"; --238 + when "0001111000" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "0001111001" => datar <= "0000101011111011";datai <= "1000000001111010"; --242 + when "0001111010" => datar <= "0000100101101010";datai <= "1000000001011010"; --244 + when "0001111011" => datar <= "0000011111011001";datai <= "1000000000111111"; --246 + when "0001111100" => datar <= "0000011001001000";datai <= "1000000000101000"; --248 + when "0001111101" => datar <= "0000010010110110";datai <= "1000000000010111"; --250 + when "0001111110" => datar <= "0000001100100100";datai <= "1000000000001011"; --252 + when "0001111111" => datar <= "0000000110010010";datai <= "1000000000000011"; --254 + when "0010000000" => datar <= "0000000000000000";datai <= "1000000000000001"; --256 + when "0010000001" => datar <= "1111111001101110";datai <= "1000000000000011"; --258 + when "0010000010" => datar <= "1111110011011100";datai <= "1000000000001011"; --260 + when "0010000011" => datar <= "1111101101001010";datai <= "1000000000010111"; --262 + when "0010000100" => datar <= "1111100110111000";datai <= "1000000000101000"; --264 + when "0010000101" => datar <= "1111100000100111";datai <= "1000000000111111"; --266 + when "0010000110" => datar <= "1111011010010110";datai <= "1000000001011010"; --268 + when "0010000111" => datar <= "1111010100000101";datai <= "1000000001111010"; --270 + when "0010001000" => datar <= "1111001101110100";datai <= "1000000010011111"; --272 + when "0010001001" => datar <= "1111000111100100";datai <= "1000000011001001"; --274 + when "0010001010" => datar <= "1111000001010101";datai <= "1000000011110111"; --276 + when "0010001011" => datar <= "1110111011000110";datai <= "1000000100101011"; --278 + when "0010001100" => datar <= "1110110100111000";datai <= "1000000101100100"; --280 + when "0010001101" => datar <= "1110101110101011";datai <= "1000000110100001"; --282 + when "0010001110" => datar <= "1110101000011110";datai <= "1000000111100011"; --284 + when "0010001111" => datar <= "1110100010010010";datai <= "1000001000101011"; --286 + when "0010010000" => datar <= "1110011100000111";datai <= "1000001001110111"; --288 + when "0010010001" => datar <= "1110010101111110";datai <= "1000001011000111"; --290 + when "0010010010" => datar <= "1110001111110101";datai <= "1000001100011101"; --292 + when "0010010011" => datar <= "1110001001101101";datai <= "1000001101111000"; --294 + when "0010010100" => datar <= "1110000011100110";datai <= "1000001111010111"; --296 + when "0010010101" => datar <= "1101111101100001";datai <= "1000010000111011"; --298 + when "0010010110" => datar <= "1101110111011101";datai <= "1000010010100100"; --300 + when "0010010111" => datar <= "1101110001011010";datai <= "1000010100010010"; --302 + when "0010011000" => datar <= "1101101011011000";datai <= "1000010110000100"; --304 + when "0010011001" => datar <= "1101100101011000";datai <= "1000010111111011"; --306 + when "0010011010" => datar <= "1101011111011010";datai <= "1000011001110111"; --308 + when "0010011011" => datar <= "1101011001011101";datai <= "1000011011110111"; --310 + when "0010011100" => datar <= "1101010011100001";datai <= "1000011101111100"; --312 + when "0010011101" => datar <= "1101001101100111";datai <= "1000100000000110"; --314 + when "0010011110" => datar <= "1101000111101111";datai <= "1000100010010101"; --316 + when "0010011111" => datar <= "1101000001111001";datai <= "1000100100101000"; --318 + when "0010100000" => datar <= "1100111100000101";datai <= "1000100110111111"; --320 + when "0010100001" => datar <= "1100110110010010";datai <= "1000101001011011"; --322 + when "0010100010" => datar <= "1100110000100001";datai <= "1000101011111100"; --324 + when "0010100011" => datar <= "1100101010110011";datai <= "1000101110100001"; --326 + when "0010100100" => datar <= "1100100101000110";datai <= "1000110001001011"; --328 + when "0010100101" => datar <= "1100011111011100";datai <= "1000110011111001"; --330 + when "0010100110" => datar <= "1100011001110100";datai <= "1000110110101100"; --332 + when "0010100111" => datar <= "1100010100001110";datai <= "1000111001100011"; --334 + when "0010101000" => datar <= "1100001110101010";datai <= "1000111100011110"; --336 + when "0010101001" => datar <= "1100001001001000";datai <= "1000111111011110"; --338 + when "0010101010" => datar <= "1100000011101001";datai <= "1001000010100010"; --340 + when "0010101011" => datar <= "1011111110001101";datai <= "1001000101101010"; --342 + when "0010101100" => datar <= "1011111000110010";datai <= "1001001000110111"; --344 + when "0010101101" => datar <= "1011110011011011";datai <= "1001001100001000"; --346 + when "0010101110" => datar <= "1011101110000110";datai <= "1001001111011101"; --348 + when "0010101111" => datar <= "1011101000110011";datai <= "1001010010110110"; --350 + when "0010110000" => datar <= "1011100011100100";datai <= "1001010110010011"; --352 + when "0010110001" => datar <= "1011011110010111";datai <= "1001011001110101"; --354 + when "0010110010" => datar <= "1011011001001100";datai <= "1001011101011010"; --356 + when "0010110011" => datar <= "1011010100000101";datai <= "1001100001000100"; --358 + when "0010110100" => datar <= "1011001111000001";datai <= "1001100100110001"; --360 + when "0010110101" => datar <= "1011001001111111";datai <= "1001101000100011"; --362 + when "0010110110" => datar <= "1011000101000001";datai <= "1001101100011000"; --364 + when "0010110111" => datar <= "1011000000000101";datai <= "1001110000010010"; --366 + when "0010111000" => datar <= "1010111011001101";datai <= "1001110100001111"; --368 + when "0010111001" => datar <= "1010110110011000";datai <= "1001111000010000"; --370 + when "0010111010" => datar <= "1010110001100101";datai <= "1001111100010101"; --372 + when "0010111011" => datar <= "1010101100110111";datai <= "1010000000011101"; --374 + when "0010111100" => datar <= "1010101000001011";datai <= "1010000100101001"; --376 + when "0010111101" => datar <= "1010100011100011";datai <= "1010001000111001"; --378 + when "0010111110" => datar <= "1010011110111110";datai <= "1010001101001101"; --380 + when "0010111111" => datar <= "1010011010011100";datai <= "1010010001100100"; --382 + when "0011000000" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "0011000001" => datar <= "1010010001100100";datai <= "1010011010011100"; --386 + when "0011000010" => datar <= "1010001101001101";datai <= "1010011110111110"; --388 + when "0011000011" => datar <= "1010001000111001";datai <= "1010100011100011"; --390 + when "0011000100" => datar <= "1010000100101001";datai <= "1010101000001011"; --392 + when "0011000101" => datar <= "1010000000011101";datai <= "1010101100110111"; --394 + when "0011000110" => datar <= "1001111100010101";datai <= "1010110001100101"; --396 + when "0011000111" => datar <= "1001111000010000";datai <= "1010110110011000"; --398 + when "0011001000" => datar <= "1001110100001111";datai <= "1010111011001101"; --400 + when "0011001001" => datar <= "1001110000010010";datai <= "1011000000000101"; --402 + when "0011001010" => datar <= "1001101100011000";datai <= "1011000101000001"; --404 + when "0011001011" => datar <= "1001101000100011";datai <= "1011001001111111"; --406 + when "0011001100" => datar <= "1001100100110001";datai <= "1011001111000001"; --408 + when "0011001101" => datar <= "1001100001000100";datai <= "1011010100000101"; --410 + when "0011001110" => datar <= "1001011101011010";datai <= "1011011001001100"; --412 + when "0011001111" => datar <= "1001011001110101";datai <= "1011011110010111"; --414 + when "0011010000" => datar <= "1001010110010011";datai <= "1011100011100100"; --416 + when "0011010001" => datar <= "1001010010110110";datai <= "1011101000110011"; --418 + when "0011010010" => datar <= "1001001111011101";datai <= "1011101110000110"; --420 + when "0011010011" => datar <= "1001001100001000";datai <= "1011110011011011"; --422 + when "0011010100" => datar <= "1001001000110111";datai <= "1011111000110010"; --424 + when "0011010101" => datar <= "1001000101101010";datai <= "1011111110001101"; --426 + when "0011010110" => datar <= "1001000010100010";datai <= "1100000011101001"; --428 + when "0011010111" => datar <= "1000111111011110";datai <= "1100001001001000"; --430 + when "0011011000" => datar <= "1000111100011110";datai <= "1100001110101010"; --432 + when "0011011001" => datar <= "1000111001100011";datai <= "1100010100001110"; --434 + when "0011011010" => datar <= "1000110110101100";datai <= "1100011001110100"; --436 + when "0011011011" => datar <= "1000110011111001";datai <= "1100011111011100"; --438 + when "0011011100" => datar <= "1000110001001011";datai <= "1100100101000110"; --440 + when "0011011101" => datar <= "1000101110100001";datai <= "1100101010110011"; --442 + when "0011011110" => datar <= "1000101011111100";datai <= "1100110000100001"; --444 + when "0011011111" => datar <= "1000101001011011";datai <= "1100110110010010"; --446 + when "0011100000" => datar <= "1000100110111111";datai <= "1100111100000101"; --448 + when "0011100001" => datar <= "1000100100101000";datai <= "1101000001111001"; --450 + when "0011100010" => datar <= "1000100010010101";datai <= "1101000111101111"; --452 + when "0011100011" => datar <= "1000100000000110";datai <= "1101001101100111"; --454 + when "0011100100" => datar <= "1000011101111100";datai <= "1101010011100001"; --456 + when "0011100101" => datar <= "1000011011110111";datai <= "1101011001011101"; --458 + when "0011100110" => datar <= "1000011001110111";datai <= "1101011111011010"; --460 + when "0011100111" => datar <= "1000010111111011";datai <= "1101100101011000"; --462 + when "0011101000" => datar <= "1000010110000100";datai <= "1101101011011000"; --464 + when "0011101001" => datar <= "1000010100010010";datai <= "1101110001011010"; --466 + when "0011101010" => datar <= "1000010010100100";datai <= "1101110111011101"; --468 + when "0011101011" => datar <= "1000010000111011";datai <= "1101111101100001"; --470 + when "0011101100" => datar <= "1000001111010111";datai <= "1110000011100110"; --472 + when "0011101101" => datar <= "1000001101111000";datai <= "1110001001101101"; --474 + when "0011101110" => datar <= "1000001100011101";datai <= "1110001111110101"; --476 + when "0011101111" => datar <= "1000001011000111";datai <= "1110010101111110"; --478 + when "0011110000" => datar <= "1000001001110111";datai <= "1110011100000111"; --480 + when "0011110001" => datar <= "1000001000101011";datai <= "1110100010010010"; --482 + when "0011110010" => datar <= "1000000111100011";datai <= "1110101000011110"; --484 + when "0011110011" => datar <= "1000000110100001";datai <= "1110101110101011"; --486 + when "0011110100" => datar <= "1000000101100100";datai <= "1110110100111000"; --488 + when "0011110101" => datar <= "1000000100101011";datai <= "1110111011000110"; --490 + when "0011110110" => datar <= "1000000011110111";datai <= "1111000001010101"; --492 + when "0011110111" => datar <= "1000000011001001";datai <= "1111000111100100"; --494 + when "0011111000" => datar <= "1000000010011111";datai <= "1111001101110100"; --496 + when "0011111001" => datar <= "1000000001111010";datai <= "1111010100000101"; --498 + when "0011111010" => datar <= "1000000001011010";datai <= "1111011010010110"; --500 + when "0011111011" => datar <= "1000000000111111";datai <= "1111100000100111"; --502 + when "0011111100" => datar <= "1000000000101000";datai <= "1111100110111000"; --504 + when "0011111101" => datar <= "1000000000010111";datai <= "1111101101001010"; --506 + when "0011111110" => datar <= "1000000000001011";datai <= "1111110011011100"; --508 + when "0011111111" => datar <= "1000000000000011";datai <= "1111111001101110"; --510 + when "0100000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "0100000001" => datar <= "0111111111111110";datai <= "1111111100110111"; --1 + when "0100000010" => datar <= "0111111111111101";datai <= "1111111001101110"; --2 + when "0100000011" => datar <= "0111111111111001";datai <= "1111110110100101"; --3 + when "0100000100" => datar <= "0111111111110101";datai <= "1111110011011100"; --4 + when "0100000101" => datar <= "0111111111110000";datai <= "1111110000010011"; --5 + when "0100000110" => datar <= "0111111111101001";datai <= "1111101101001010"; --6 + when "0100000111" => datar <= "0111111111100001";datai <= "1111101010000001"; --7 + when "0100001000" => datar <= "0111111111011000";datai <= "1111100110111000"; --8 + when "0100001001" => datar <= "0111111111001101";datai <= "1111100011101111"; --9 + when "0100001010" => datar <= "0111111111000001";datai <= "1111100000100111"; --10 + when "0100001011" => datar <= "0111111110110100";datai <= "1111011101011110"; --11 + when "0100001100" => datar <= "0111111110100110";datai <= "1111011010010110"; --12 + when "0100001101" => datar <= "0111111110010111";datai <= "1111010111001101"; --13 + when "0100001110" => datar <= "0111111110000110";datai <= "1111010100000101"; --14 + when "0100001111" => datar <= "0111111101110100";datai <= "1111010000111100"; --15 + when "0100010000" => datar <= "0111111101100001";datai <= "1111001101110100"; --16 + when "0100010001" => datar <= "0111111101001101";datai <= "1111001010101100"; --17 + when "0100010010" => datar <= "0111111100110111";datai <= "1111000111100100"; --18 + when "0100010011" => datar <= "0111111100100001";datai <= "1111000100011101"; --19 + when "0100010100" => datar <= "0111111100001001";datai <= "1111000001010101"; --20 + when "0100010101" => datar <= "0111111011101111";datai <= "1110111110001110"; --21 + when "0100010110" => datar <= "0111111011010101";datai <= "1110111011000110"; --22 + when "0100010111" => datar <= "0111111010111001";datai <= "1110110111111111"; --23 + when "0100011000" => datar <= "0111111010011100";datai <= "1110110100111000"; --24 + when "0100011001" => datar <= "0111111001111110";datai <= "1110110001110001"; --25 + when "0100011010" => datar <= "0111111001011111";datai <= "1110101110101011"; --26 + when "0100011011" => datar <= "0111111000111110";datai <= "1110101011100100"; --27 + when "0100011100" => datar <= "0111111000011101";datai <= "1110101000011110"; --28 + when "0100011101" => datar <= "0111110111111010";datai <= "1110100101011000"; --29 + when "0100011110" => datar <= "0111110111010101";datai <= "1110100010010010"; --30 + when "0100011111" => datar <= "0111110110110000";datai <= "1110011111001101"; --31 + when "0100100000" => datar <= "0111110110001001";datai <= "1110011100000111"; --32 + when "0100100001" => datar <= "0111110101100010";datai <= "1110011001000010"; --33 + when "0100100010" => datar <= "0111110100111001";datai <= "1110010101111110"; --34 + when "0100100011" => datar <= "0111110100001110";datai <= "1110010010111001"; --35 + when "0100100100" => datar <= "0111110011100011";datai <= "1110001111110101"; --36 + when "0100100101" => datar <= "0111110010110110";datai <= "1110001100110001"; --37 + when "0100100110" => datar <= "0111110010001000";datai <= "1110001001101101"; --38 + when "0100100111" => datar <= "0111110001011001";datai <= "1110000110101001"; --39 + when "0100101000" => datar <= "0111110000101001";datai <= "1110000011100110"; --40 + when "0100101001" => datar <= "0111101111111000";datai <= "1110000000100011"; --41 + when "0100101010" => datar <= "0111101111000101";datai <= "1101111101100001"; --42 + when "0100101011" => datar <= "0111101110010001";datai <= "1101111010011111"; --43 + when "0100101100" => datar <= "0111101101011100";datai <= "1101110111011101"; --44 + when "0100101101" => datar <= "0111101100100110";datai <= "1101110100011011"; --45 + when "0100101110" => datar <= "0111101011101110";datai <= "1101110001011010"; --46 + when "0100101111" => datar <= "0111101010110110";datai <= "1101101110011001"; --47 + when "0100110000" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "0100110001" => datar <= "0111101001000001";datai <= "1101101000011000"; --49 + when "0100110010" => datar <= "0111101000000101";datai <= "1101100101011000"; --50 + when "0100110011" => datar <= "0111100111001000";datai <= "1101100010011001"; --51 + when "0100110100" => datar <= "0111100110001001";datai <= "1101011111011010"; --52 + when "0100110101" => datar <= "0111100101001010";datai <= "1101011100011011"; --53 + when "0100110110" => datar <= "0111100100001001";datai <= "1101011001011101"; --54 + when "0100110111" => datar <= "0111100011000111";datai <= "1101010110011111"; --55 + when "0100111000" => datar <= "0111100010000100";datai <= "1101010011100001"; --56 + when "0100111001" => datar <= "0111100000111111";datai <= "1101010000100100"; --57 + when "0100111010" => datar <= "0111011111111010";datai <= "1101001101100111"; --58 + when "0100111011" => datar <= "0111011110110011";datai <= "1101001010101011"; --59 + when "0100111100" => datar <= "0111011101101011";datai <= "1101000111101111"; --60 + when "0100111101" => datar <= "0111011100100010";datai <= "1101000100110100"; --61 + when "0100111110" => datar <= "0111011011011000";datai <= "1101000001111001"; --62 + when "0100111111" => datar <= "0111011010001101";datai <= "1100111110111111"; --63 + when "0101000000" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "0101000001" => datar <= "0111010111110011";datai <= "1100111001001011"; --65 + when "0101000010" => datar <= "0111010110100101";datai <= "1100110110010010"; --66 + when "0101000011" => datar <= "0111010101010101";datai <= "1100110011011010"; --67 + when "0101000100" => datar <= "0111010100000100";datai <= "1100110000100001"; --68 + when "0101000101" => datar <= "0111010010110010";datai <= "1100101101101010"; --69 + when "0101000110" => datar <= "0111010001011111";datai <= "1100101010110011"; --70 + when "0101000111" => datar <= "0111010000001010";datai <= "1100100111111100"; --71 + when "0101001000" => datar <= "0111001110110101";datai <= "1100100101000110"; --72 + when "0101001001" => datar <= "0111001101011110";datai <= "1100100010010001"; --73 + when "0101001010" => datar <= "0111001100000111";datai <= "1100011111011100"; --74 + when "0101001011" => datar <= "0111001010101110";datai <= "1100011100100111"; --75 + when "0101001100" => datar <= "0111001001010100";datai <= "1100011001110100"; --76 + when "0101001101" => datar <= "0111000111111001";datai <= "1100010111000000"; --77 + when "0101001110" => datar <= "0111000110011101";datai <= "1100010100001110"; --78 + when "0101001111" => datar <= "0111000101000000";datai <= "1100010001011011"; --79 + when "0101010000" => datar <= "0111000011100010";datai <= "1100001110101010"; --80 + when "0101010001" => datar <= "0111000010000011";datai <= "1100001011111001"; --81 + when "0101010010" => datar <= "0111000000100010";datai <= "1100001001001000"; --82 + when "0101010011" => datar <= "0110111111000001";datai <= "1100000110011000"; --83 + when "0101010100" => datar <= "0110111101011110";datai <= "1100000011101001"; --84 + when "0101010101" => datar <= "0110111011111011";datai <= "1100000000111011"; --85 + when "0101010110" => datar <= "0110111010010110";datai <= "1011111110001101"; --86 + when "0101010111" => datar <= "0110111000110000";datai <= "1011111011011111"; --87 + when "0101011000" => datar <= "0110110111001001";datai <= "1011111000110010"; --88 + when "0101011001" => datar <= "0110110101100001";datai <= "1011110110000110"; --89 + when "0101011010" => datar <= "0110110011111000";datai <= "1011110011011011"; --90 + when "0101011011" => datar <= "0110110010001110";datai <= "1011110000110000"; --91 + when "0101011100" => datar <= "0110110000100011";datai <= "1011101110000110"; --92 + when "0101011101" => datar <= "0110101110110111";datai <= "1011101011011100"; --93 + when "0101011110" => datar <= "0110101101001010";datai <= "1011101000110011"; --94 + when "0101011111" => datar <= "0110101011011100";datai <= "1011100110001011"; --95 + when "0101100000" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "0101100001" => datar <= "0110100111111101";datai <= "1011100000111101"; --97 + when "0101100010" => datar <= "0110100110001011";datai <= "1011011110010111"; --98 + when "0101100011" => datar <= "0110100100011001";datai <= "1011011011110001"; --99 + when "0101100100" => datar <= "0110100010100110";datai <= "1011011001001100"; --100 + when "0101100101" => datar <= "0110100000110010";datai <= "1011010110101000"; --101 + when "0101100110" => datar <= "0110011110111100";datai <= "1011010100000101"; --102 + when "0101100111" => datar <= "0110011101000110";datai <= "1011010001100011"; --103 + when "0101101000" => datar <= "0110011011001111";datai <= "1011001111000001"; --104 + when "0101101001" => datar <= "0110011001010110";datai <= "1011001100100000"; --105 + when "0101101010" => datar <= "0110010111011101";datai <= "1011001001111111"; --106 + when "0101101011" => datar <= "0110010101100011";datai <= "1011000111100000"; --107 + when "0101101100" => datar <= "0110010011101000";datai <= "1011000101000001"; --108 + when "0101101101" => datar <= "0110010001101100";datai <= "1011000010100011"; --109 + when "0101101110" => datar <= "0110001111101110";datai <= "1011000000000101"; --110 + when "0101101111" => datar <= "0110001101110000";datai <= "1010111101101001"; --111 + when "0101110000" => datar <= "0110001011110001";datai <= "1010111011001101"; --112 + when "0101110001" => datar <= "0110001001110001";datai <= "1010111000110010"; --113 + when "0101110010" => datar <= "0110000111110000";datai <= "1010110110011000"; --114 + when "0101110011" => datar <= "0110000101101110";datai <= "1010110011111110"; --115 + when "0101110100" => datar <= "0110000011101011";datai <= "1010110001100101"; --116 + when "0101110101" => datar <= "0110000001101000";datai <= "1010101111001110"; --117 + when "0101110110" => datar <= "0101111111100011";datai <= "1010101100110111"; --118 + when "0101110111" => datar <= "0101111101011101";datai <= "1010101010100000"; --119 + when "0101111000" => datar <= "0101111011010111";datai <= "1010101000001011"; --120 + when "0101111001" => datar <= "0101111001001111";datai <= "1010100101110110"; --121 + when "0101111010" => datar <= "0101110111000111";datai <= "1010100011100011"; --122 + when "0101111011" => datar <= "0101110100111110";datai <= "1010100001010000"; --123 + when "0101111100" => datar <= "0101110010110011";datai <= "1010011110111110"; --124 + when "0101111101" => datar <= "0101110000101000";datai <= "1010011100101101"; --125 + when "0101111110" => datar <= "0101101110011100";datai <= "1010011010011100"; --126 + when "0101111111" => datar <= "0101101100001111";datai <= "1010011000001101"; --127 + when "0110000000" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "0110000001" => datar <= "0101100111110011";datai <= "1010010011110001"; --129 + when "0110000010" => datar <= "0101100101100100";datai <= "1010010001100100"; --130 + when "0110000011" => datar <= "0101100011010011";datai <= "1010001111011000"; --131 + when "0110000100" => datar <= "0101100001000010";datai <= "1010001101001101"; --132 + when "0110000101" => datar <= "0101011110110000";datai <= "1010001011000010"; --133 + when "0110000110" => datar <= "0101011100011101";datai <= "1010001000111001"; --134 + when "0110000111" => datar <= "0101011010001010";datai <= "1010000110110001"; --135 + when "0110001000" => datar <= "0101010111110101";datai <= "1010000100101001"; --136 + when "0110001001" => datar <= "0101010101100000";datai <= "1010000010100011"; --137 + when "0110001010" => datar <= "0101010011001001";datai <= "1010000000011101"; --138 + when "0110001011" => datar <= "0101010000110010";datai <= "1001111110011000"; --139 + when "0110001100" => datar <= "0101001110011011";datai <= "1001111100010101"; --140 + when "0110001101" => datar <= "0101001100000010";datai <= "1001111010010010"; --141 + when "0110001110" => datar <= "0101001001101000";datai <= "1001111000010000"; --142 + when "0110001111" => datar <= "0101000111001110";datai <= "1001110110001111"; --143 + when "0110010000" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "0110010001" => datar <= "0101000010010111";datai <= "1001110010010000"; --145 + when "0110010010" => datar <= "0100111111111011";datai <= "1001110000010010"; --146 + when "0110010011" => datar <= "0100111101011101";datai <= "1001101110010100"; --147 + when "0110010100" => datar <= "0100111010111111";datai <= "1001101100011000"; --148 + when "0110010101" => datar <= "0100111000100000";datai <= "1001101010011101"; --149 + when "0110010110" => datar <= "0100110110000001";datai <= "1001101000100011"; --150 + when "0110010111" => datar <= "0100110011100000";datai <= "1001100110101010"; --151 + when "0110011000" => datar <= "0100110000111111";datai <= "1001100100110001"; --152 + when "0110011001" => datar <= "0100101110011101";datai <= "1001100010111010"; --153 + when "0110011010" => datar <= "0100101011111011";datai <= "1001100001000100"; --154 + when "0110011011" => datar <= "0100101001011000";datai <= "1001011111001110"; --155 + when "0110011100" => datar <= "0100100110110100";datai <= "1001011101011010"; --156 + when "0110011101" => datar <= "0100100100001111";datai <= "1001011011100111"; --157 + when "0110011110" => datar <= "0100100001101001";datai <= "1001011001110101"; --158 + when "0110011111" => datar <= "0100011111000011";datai <= "1001011000000011"; --159 + when "0110100000" => datar <= "0100011100011100";datai <= "1001010110010011"; --160 + when "0110100001" => datar <= "0100011001110101";datai <= "1001010100100100"; --161 + when "0110100010" => datar <= "0100010111001101";datai <= "1001010010110110"; --162 + when "0110100011" => datar <= "0100010100100100";datai <= "1001010001001001"; --163 + when "0110100100" => datar <= "0100010001111010";datai <= "1001001111011101"; --164 + when "0110100101" => datar <= "0100001111010000";datai <= "1001001101110010"; --165 + when "0110100110" => datar <= "0100001100100101";datai <= "1001001100001000"; --166 + when "0110100111" => datar <= "0100001001111010";datai <= "1001001010011111"; --167 + when "0110101000" => datar <= "0100000111001110";datai <= "1001001000110111"; --168 + when "0110101001" => datar <= "0100000100100001";datai <= "1001000111010000"; --169 + when "0110101010" => datar <= "0100000001110011";datai <= "1001000101101010"; --170 + when "0110101011" => datar <= "0011111111000101";datai <= "1001000100000101"; --171 + when "0110101100" => datar <= "0011111100010111";datai <= "1001000010100010"; --172 + when "0110101101" => datar <= "0011111001101000";datai <= "1001000000111111"; --173 + when "0110101110" => datar <= "0011110110111000";datai <= "1000111111011110"; --174 + when "0110101111" => datar <= "0011110100000111";datai <= "1000111101111101"; --175 + when "0110110000" => datar <= "0011110001010110";datai <= "1000111100011110"; --176 + when "0110110001" => datar <= "0011101110100101";datai <= "1000111011000000"; --177 + when "0110110010" => datar <= "0011101011110010";datai <= "1000111001100011"; --178 + when "0110110011" => datar <= "0011101001000000";datai <= "1000111000000111"; --179 + when "0110110100" => datar <= "0011100110001100";datai <= "1000110110101100"; --180 + when "0110110101" => datar <= "0011100011011001";datai <= "1000110101010010"; --181 + when "0110110110" => datar <= "0011100000100100";datai <= "1000110011111001"; --182 + when "0110110111" => datar <= "0011011101101111";datai <= "1000110010100010"; --183 + when "0110111000" => datar <= "0011011010111010";datai <= "1000110001001011"; --184 + when "0110111001" => datar <= "0011011000000100";datai <= "1000101111110110"; --185 + when "0110111010" => datar <= "0011010101001101";datai <= "1000101110100001"; --186 + when "0110111011" => datar <= "0011010010010110";datai <= "1000101101001110"; --187 + when "0110111100" => datar <= "0011001111011111";datai <= "1000101011111100"; --188 + when "0110111101" => datar <= "0011001100100110";datai <= "1000101010101011"; --189 + when "0110111110" => datar <= "0011001001101110";datai <= "1000101001011011"; --190 + when "0110111111" => datar <= "0011000110110101";datai <= "1000101000001101"; --191 + when "0111000000" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "0111000001" => datar <= "0011000001000001";datai <= "1000100101110011"; --193 + when "0111000010" => datar <= "0010111110000111";datai <= "1000100100101000"; --194 + when "0111000011" => datar <= "0010111011001100";datai <= "1000100011011110"; --195 + when "0111000100" => datar <= "0010111000010001";datai <= "1000100010010101"; --196 + when "0111000101" => datar <= "0010110101010101";datai <= "1000100001001101"; --197 + when "0111000110" => datar <= "0010110010011001";datai <= "1000100000000110"; --198 + when "0111000111" => datar <= "0010101111011100";datai <= "1000011111000001"; --199 + when "0111001000" => datar <= "0010101100011111";datai <= "1000011101111100"; --200 + when "0111001001" => datar <= "0010101001100001";datai <= "1000011100111001"; --201 + when "0111001010" => datar <= "0010100110100011";datai <= "1000011011110111"; --202 + when "0111001011" => datar <= "0010100011100101";datai <= "1000011010110110"; --203 + when "0111001100" => datar <= "0010100000100110";datai <= "1000011001110111"; --204 + when "0111001101" => datar <= "0010011101100111";datai <= "1000011000111000"; --205 + when "0111001110" => datar <= "0010011010101000";datai <= "1000010111111011"; --206 + when "0111001111" => datar <= "0010010111101000";datai <= "1000010110111111"; --207 + when "0111010000" => datar <= "0010010100101000";datai <= "1000010110000100"; --208 + when "0111010001" => datar <= "0010010001100111";datai <= "1000010101001010"; --209 + when "0111010010" => datar <= "0010001110100110";datai <= "1000010100010010"; --210 + when "0111010011" => datar <= "0010001011100101";datai <= "1000010011011010"; --211 + when "0111010100" => datar <= "0010001000100011";datai <= "1000010010100100"; --212 + when "0111010101" => datar <= "0010000101100001";datai <= "1000010001101111"; --213 + when "0111010110" => datar <= "0010000010011111";datai <= "1000010000111011"; --214 + when "0111010111" => datar <= "0001111111011101";datai <= "1000010000001000"; --215 + when "0111011000" => datar <= "0001111100011010";datai <= "1000001111010111"; --216 + when "0111011001" => datar <= "0001111001010111";datai <= "1000001110100111"; --217 + when "0111011010" => datar <= "0001110110010011";datai <= "1000001101111000"; --218 + when "0111011011" => datar <= "0001110011001111";datai <= "1000001101001010"; --219 + when "0111011100" => datar <= "0001110000001011";datai <= "1000001100011101"; --220 + when "0111011101" => datar <= "0001101101000111";datai <= "1000001011110010"; --221 + when "0111011110" => datar <= "0001101010000010";datai <= "1000001011000111"; --222 + when "0111011111" => datar <= "0001100110111110";datai <= "1000001010011110"; --223 + when "0111100000" => datar <= "0001100011111001";datai <= "1000001001110111"; --224 + when "0111100001" => datar <= "0001100000110011";datai <= "1000001001010000"; --225 + when "0111100010" => datar <= "0001011101101110";datai <= "1000001000101011"; --226 + when "0111100011" => datar <= "0001011010101000";datai <= "1000001000000110"; --227 + when "0111100100" => datar <= "0001010111100010";datai <= "1000000111100011"; --228 + when "0111100101" => datar <= "0001010100011100";datai <= "1000000111000010"; --229 + when "0111100110" => datar <= "0001010001010101";datai <= "1000000110100001"; --230 + when "0111100111" => datar <= "0001001110001111";datai <= "1000000110000010"; --231 + when "0111101000" => datar <= "0001001011001000";datai <= "1000000101100100"; --232 + when "0111101001" => datar <= "0001001000000001";datai <= "1000000101000111"; --233 + when "0111101010" => datar <= "0001000100111010";datai <= "1000000100101011"; --234 + when "0111101011" => datar <= "0001000001110010";datai <= "1000000100010001"; --235 + when "0111101100" => datar <= "0000111110101011";datai <= "1000000011110111"; --236 + when "0111101101" => datar <= "0000111011100011";datai <= "1000000011011111"; --237 + when "0111101110" => datar <= "0000111000011100";datai <= "1000000011001001"; --238 + when "0111101111" => datar <= "0000110101010100";datai <= "1000000010110011"; --239 + when "0111110000" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "0111110001" => datar <= "0000101111000100";datai <= "1000000010001100"; --241 + when "0111110010" => datar <= "0000101011111011";datai <= "1000000001111010"; --242 + when "0111110011" => datar <= "0000101000110011";datai <= "1000000001101001"; --243 + when "0111110100" => datar <= "0000100101101010";datai <= "1000000001011010"; --244 + when "0111110101" => datar <= "0000100010100010";datai <= "1000000001001100"; --245 + when "0111110110" => datar <= "0000011111011001";datai <= "1000000000111111"; --246 + when "0111110111" => datar <= "0000011100010001";datai <= "1000000000110011"; --247 + when "0111111000" => datar <= "0000011001001000";datai <= "1000000000101000"; --248 + when "0111111001" => datar <= "0000010101111111";datai <= "1000000000011111"; --249 + when "0111111010" => datar <= "0000010010110110";datai <= "1000000000010111"; --250 + when "0111111011" => datar <= "0000001111101101";datai <= "1000000000010000"; --251 + when "0111111100" => datar <= "0000001100100100";datai <= "1000000000001011"; --252 + when "0111111101" => datar <= "0000001001011011";datai <= "1000000000000111"; --253 + when "0111111110" => datar <= "0000000110010010";datai <= "1000000000000011"; --254 + when "0111111111" => datar <= "0000000011001001";datai <= "1000000000000010"; --255 + when "1000000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1000000001" => datar <= "0111111111111001";datai <= "1111110110100101"; --3 + when "1000000010" => datar <= "0111111111101001";datai <= "1111101101001010"; --6 + when "1000000011" => datar <= "0111111111001101";datai <= "1111100011101111"; --9 + when "1000000100" => datar <= "0111111110100110";datai <= "1111011010010110"; --12 + when "1000000101" => datar <= "0111111101110100";datai <= "1111010000111100"; --15 + when "1000000110" => datar <= "0111111100110111";datai <= "1111000111100100"; --18 + when "1000000111" => datar <= "0111111011101111";datai <= "1110111110001110"; --21 + when "1000001000" => datar <= "0111111010011100";datai <= "1110110100111000"; --24 + when "1000001001" => datar <= "0111111000111110";datai <= "1110101011100100"; --27 + when "1000001010" => datar <= "0111110111010101";datai <= "1110100010010010"; --30 + when "1000001011" => datar <= "0111110101100010";datai <= "1110011001000010"; --33 + when "1000001100" => datar <= "0111110011100011";datai <= "1110001111110101"; --36 + when "1000001101" => datar <= "0111110001011001";datai <= "1110000110101001"; --39 + when "1000001110" => datar <= "0111101111000101";datai <= "1101111101100001"; --42 + when "1000001111" => datar <= "0111101100100110";datai <= "1101110100011011"; --45 + when "1000010000" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "1000010001" => datar <= "0111100111001000";datai <= "1101100010011001"; --51 + when "1000010010" => datar <= "0111100100001001";datai <= "1101011001011101"; --54 + when "1000010011" => datar <= "0111100000111111";datai <= "1101010000100100"; --57 + when "1000010100" => datar <= "0111011101101011";datai <= "1101000111101111"; --60 + when "1000010101" => datar <= "0111011010001101";datai <= "1100111110111111"; --63 + when "1000010110" => datar <= "0111010110100101";datai <= "1100110110010010"; --66 + when "1000010111" => datar <= "0111010010110010";datai <= "1100101101101010"; --69 + when "1000011000" => datar <= "0111001110110101";datai <= "1100100101000110"; --72 + when "1000011001" => datar <= "0111001010101110";datai <= "1100011100100111"; --75 + when "1000011010" => datar <= "0111000110011101";datai <= "1100010100001110"; --78 + when "1000011011" => datar <= "0111000010000011";datai <= "1100001011111001"; --81 + when "1000011100" => datar <= "0110111101011110";datai <= "1100000011101001"; --84 + when "1000011101" => datar <= "0110111000110000";datai <= "1011111011011111"; --87 + when "1000011110" => datar <= "0110110011111000";datai <= "1011110011011011"; --90 + when "1000011111" => datar <= "0110101110110111";datai <= "1011101011011100"; --93 + when "1000100000" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "1000100001" => datar <= "0110100100011001";datai <= "1011011011110001"; --99 + when "1000100010" => datar <= "0110011110111100";datai <= "1011010100000101"; --102 + when "1000100011" => datar <= "0110011001010110";datai <= "1011001100100000"; --105 + when "1000100100" => datar <= "0110010011101000";datai <= "1011000101000001"; --108 + when "1000100101" => datar <= "0110001101110000";datai <= "1010111101101001"; --111 + when "1000100110" => datar <= "0110000111110000";datai <= "1010110110011000"; --114 + when "1000100111" => datar <= "0110000001101000";datai <= "1010101111001110"; --117 + when "1000101000" => datar <= "0101111011010111";datai <= "1010101000001011"; --120 + when "1000101001" => datar <= "0101110100111110";datai <= "1010100001010000"; --123 + when "1000101010" => datar <= "0101101110011100";datai <= "1010011010011100"; --126 + when "1000101011" => datar <= "0101100111110011";datai <= "1010010011110001"; --129 + when "1000101100" => datar <= "0101100001000010";datai <= "1010001101001101"; --132 + when "1000101101" => datar <= "0101011010001010";datai <= "1010000110110001"; --135 + when "1000101110" => datar <= "0101010011001001";datai <= "1010000000011101"; --138 + when "1000101111" => datar <= "0101001100000010";datai <= "1001111010010010"; --141 + when "1000110000" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "1000110001" => datar <= "0100111101011101";datai <= "1001101110010100"; --147 + when "1000110010" => datar <= "0100110110000001";datai <= "1001101000100011"; --150 + when "1000110011" => datar <= "0100101110011101";datai <= "1001100010111010"; --153 + when "1000110100" => datar <= "0100100110110100";datai <= "1001011101011010"; --156 + when "1000110101" => datar <= "0100011111000011";datai <= "1001011000000011"; --159 + when "1000110110" => datar <= "0100010111001101";datai <= "1001010010110110"; --162 + when "1000110111" => datar <= "0100001111010000";datai <= "1001001101110010"; --165 + when "1000111000" => datar <= "0100000111001110";datai <= "1001001000110111"; --168 + when "1000111001" => datar <= "0011111111000101";datai <= "1001000100000101"; --171 + when "1000111010" => datar <= "0011110110111000";datai <= "1000111111011110"; --174 + when "1000111011" => datar <= "0011101110100101";datai <= "1000111011000000"; --177 + when "1000111100" => datar <= "0011100110001100";datai <= "1000110110101100"; --180 + when "1000111101" => datar <= "0011011101101111";datai <= "1000110010100010"; --183 + when "1000111110" => datar <= "0011010101001101";datai <= "1000101110100001"; --186 + when "1000111111" => datar <= "0011001100100110";datai <= "1000101010101011"; --189 + when "1001000000" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "1001000001" => datar <= "0010111011001100";datai <= "1000100011011110"; --195 + when "1001000010" => datar <= "0010110010011001";datai <= "1000100000000110"; --198 + when "1001000011" => datar <= "0010101001100001";datai <= "1000011100111001"; --201 + when "1001000100" => datar <= "0010100000100110";datai <= "1000011001110111"; --204 + when "1001000101" => datar <= "0010010111101000";datai <= "1000010110111111"; --207 + when "1001000110" => datar <= "0010001110100110";datai <= "1000010100010010"; --210 + when "1001000111" => datar <= "0010000101100001";datai <= "1000010001101111"; --213 + when "1001001000" => datar <= "0001111100011010";datai <= "1000001111010111"; --216 + when "1001001001" => datar <= "0001110011001111";datai <= "1000001101001010"; --219 + when "1001001010" => datar <= "0001101010000010";datai <= "1000001011000111"; --222 + when "1001001011" => datar <= "0001100000110011";datai <= "1000001001010000"; --225 + when "1001001100" => datar <= "0001010111100010";datai <= "1000000111100011"; --228 + when "1001001101" => datar <= "0001001110001111";datai <= "1000000110000010"; --231 + when "1001001110" => datar <= "0001000100111010";datai <= "1000000100101011"; --234 + when "1001001111" => datar <= "0000111011100011";datai <= "1000000011011111"; --237 + when "1001010000" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "1001010001" => datar <= "0000101000110011";datai <= "1000000001101001"; --243 + when "1001010010" => datar <= "0000011111011001";datai <= "1000000000111111"; --246 + when "1001010011" => datar <= "0000010101111111";datai <= "1000000000011111"; --249 + when "1001010100" => datar <= "0000001100100100";datai <= "1000000000001011"; --252 + when "1001010101" => datar <= "0000000011001001";datai <= "1000000000000010"; --255 + when "1001010110" => datar <= "1111111001101110";datai <= "1000000000000011"; --258 + when "1001010111" => datar <= "1111110000010011";datai <= "1000000000010000"; --261 + when "1001011000" => datar <= "1111100110111000";datai <= "1000000000101000"; --264 + when "1001011001" => datar <= "1111011101011110";datai <= "1000000001001100"; --267 + when "1001011010" => datar <= "1111010100000101";datai <= "1000000001111010"; --270 + when "1001011011" => datar <= "1111001010101100";datai <= "1000000010110011"; --273 + when "1001011100" => datar <= "1111000001010101";datai <= "1000000011110111"; --276 + when "1001011101" => datar <= "1110110111111111";datai <= "1000000101000111"; --279 + when "1001011110" => datar <= "1110101110101011";datai <= "1000000110100001"; --282 + when "1001011111" => datar <= "1110100101011000";datai <= "1000001000000110"; --285 + when "1001100000" => datar <= "1110011100000111";datai <= "1000001001110111"; --288 + when "1001100001" => datar <= "1110010010111001";datai <= "1000001011110010"; --291 + when "1001100010" => datar <= "1110001001101101";datai <= "1000001101111000"; --294 + when "1001100011" => datar <= "1110000000100011";datai <= "1000010000001000"; --297 + when "1001100100" => datar <= "1101110111011101";datai <= "1000010010100100"; --300 + when "1001100101" => datar <= "1101101110011001";datai <= "1000010101001010"; --303 + when "1001100110" => datar <= "1101100101011000";datai <= "1000010111111011"; --306 + when "1001100111" => datar <= "1101011100011011";datai <= "1000011010110110"; --309 + when "1001101000" => datar <= "1101010011100001";datai <= "1000011101111100"; --312 + when "1001101001" => datar <= "1101001010101011";datai <= "1000100001001101"; --315 + when "1001101010" => datar <= "1101000001111001";datai <= "1000100100101000"; --318 + when "1001101011" => datar <= "1100111001001011";datai <= "1000101000001101"; --321 + when "1001101100" => datar <= "1100110000100001";datai <= "1000101011111100"; --324 + when "1001101101" => datar <= "1100100111111100";datai <= "1000101111110110"; --327 + when "1001101110" => datar <= "1100011111011100";datai <= "1000110011111001"; --330 + when "1001101111" => datar <= "1100010111000000";datai <= "1000111000000111"; --333 + when "1001110000" => datar <= "1100001110101010";datai <= "1000111100011110"; --336 + when "1001110001" => datar <= "1100000110011000";datai <= "1001000000111111"; --339 + when "1001110010" => datar <= "1011111110001101";datai <= "1001000101101010"; --342 + when "1001110011" => datar <= "1011110110000110";datai <= "1001001010011111"; --345 + when "1001110100" => datar <= "1011101110000110";datai <= "1001001111011101"; --348 + when "1001110101" => datar <= "1011100110001011";datai <= "1001010100100100"; --351 + when "1001110110" => datar <= "1011011110010111";datai <= "1001011001110101"; --354 + when "1001110111" => datar <= "1011010110101000";datai <= "1001011111001110"; --357 + when "1001111000" => datar <= "1011001111000001";datai <= "1001100100110001"; --360 + when "1001111001" => datar <= "1011000111100000";datai <= "1001101010011101"; --363 + when "1001111010" => datar <= "1011000000000101";datai <= "1001110000010010"; --366 + when "1001111011" => datar <= "1010111000110010";datai <= "1001110110001111"; --369 + when "1001111100" => datar <= "1010110001100101";datai <= "1001111100010101"; --372 + when "1001111101" => datar <= "1010101010100000";datai <= "1010000010100011"; --375 + when "1001111110" => datar <= "1010100011100011";datai <= "1010001000111001"; --378 + when "1001111111" => datar <= "1010011100101101";datai <= "1010001111011000"; --381 + when "1010000000" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "1010000001" => datar <= "1010001111011000";datai <= "1010011100101101"; --387 + when "1010000010" => datar <= "1010001000111001";datai <= "1010100011100011"; --390 + when "1010000011" => datar <= "1010000010100011";datai <= "1010101010100000"; --393 + when "1010000100" => datar <= "1001111100010101";datai <= "1010110001100101"; --396 + when "1010000101" => datar <= "1001110110001111";datai <= "1010111000110010"; --399 + when "1010000110" => datar <= "1001110000010010";datai <= "1011000000000101"; --402 + when "1010000111" => datar <= "1001101010011101";datai <= "1011000111100000"; --405 + when "1010001000" => datar <= "1001100100110001";datai <= "1011001111000001"; --408 + when "1010001001" => datar <= "1001011111001110";datai <= "1011010110101000"; --411 + when "1010001010" => datar <= "1001011001110101";datai <= "1011011110010111"; --414 + when "1010001011" => datar <= "1001010100100100";datai <= "1011100110001011"; --417 + when "1010001100" => datar <= "1001001111011101";datai <= "1011101110000110"; --420 + when "1010001101" => datar <= "1001001010011111";datai <= "1011110110000110"; --423 + when "1010001110" => datar <= "1001000101101010";datai <= "1011111110001101"; --426 + when "1010001111" => datar <= "1001000000111111";datai <= "1100000110011000"; --429 + when "1010010000" => datar <= "1000111100011110";datai <= "1100001110101010"; --432 + when "1010010001" => datar <= "1000111000000111";datai <= "1100010111000000"; --435 + when "1010010010" => datar <= "1000110011111001";datai <= "1100011111011100"; --438 + when "1010010011" => datar <= "1000101111110110";datai <= "1100100111111100"; --441 + when "1010010100" => datar <= "1000101011111100";datai <= "1100110000100001"; --444 + when "1010010101" => datar <= "1000101000001101";datai <= "1100111001001011"; --447 + when "1010010110" => datar <= "1000100100101000";datai <= "1101000001111001"; --450 + when "1010010111" => datar <= "1000100001001101";datai <= "1101001010101011"; --453 + when "1010011000" => datar <= "1000011101111100";datai <= "1101010011100001"; --456 + when "1010011001" => datar <= "1000011010110110";datai <= "1101011100011011"; --459 + when "1010011010" => datar <= "1000010111111011";datai <= "1101100101011000"; --462 + when "1010011011" => datar <= "1000010101001010";datai <= "1101101110011001"; --465 + when "1010011100" => datar <= "1000010010100100";datai <= "1101110111011101"; --468 + when "1010011101" => datar <= "1000010000001000";datai <= "1110000000100011"; --471 + when "1010011110" => datar <= "1000001101111000";datai <= "1110001001101101"; --474 + when "1010011111" => datar <= "1000001011110010";datai <= "1110010010111001"; --477 + when "1010100000" => datar <= "1000001001110111";datai <= "1110011100000111"; --480 + when "1010100001" => datar <= "1000001000000110";datai <= "1110100101011000"; --483 + when "1010100010" => datar <= "1000000110100001";datai <= "1110101110101011"; --486 + when "1010100011" => datar <= "1000000101000111";datai <= "1110110111111111"; --489 + when "1010100100" => datar <= "1000000011110111";datai <= "1111000001010101"; --492 + when "1010100101" => datar <= "1000000010110011";datai <= "1111001010101100"; --495 + when "1010100110" => datar <= "1000000001111010";datai <= "1111010100000101"; --498 + when "1010100111" => datar <= "1000000001001100";datai <= "1111011101011110"; --501 + when "1010101000" => datar <= "1000000000101000";datai <= "1111100110111000"; --504 + when "1010101001" => datar <= "1000000000010000";datai <= "1111110000010011"; --507 + when "1010101010" => datar <= "1000000000000011";datai <= "1111111001101110"; --510 + when "1010101011" => datar <= "1000000000000010";datai <= "0000000011001001"; --513 + when "1010101100" => datar <= "1000000000001011";datai <= "0000001100100100"; --516 + when "1010101101" => datar <= "1000000000011111";datai <= "0000010101111111"; --519 + when "1010101110" => datar <= "1000000000111111";datai <= "0000011111011001"; --522 + when "1010101111" => datar <= "1000000001101001";datai <= "0000101000110011"; --525 + when "1010110000" => datar <= "1000000010011111";datai <= "0000110010001100"; --528 + when "1010110001" => datar <= "1000000011011111";datai <= "0000111011100011"; --531 + when "1010110010" => datar <= "1000000100101011";datai <= "0001000100111010"; --534 + when "1010110011" => datar <= "1000000110000010";datai <= "0001001110001111"; --537 + when "1010110100" => datar <= "1000000111100011";datai <= "0001010111100010"; --540 + when "1010110101" => datar <= "1000001001010000";datai <= "0001100000110011"; --543 + when "1010110110" => datar <= "1000001011000111";datai <= "0001101010000010"; --546 + when "1010110111" => datar <= "1000001101001010";datai <= "0001110011001111"; --549 + when "1010111000" => datar <= "1000001111010111";datai <= "0001111100011010"; --552 + when "1010111001" => datar <= "1000010001101111";datai <= "0010000101100001"; --555 + when "1010111010" => datar <= "1000010100010010";datai <= "0010001110100110"; --558 + when "1010111011" => datar <= "1000010110111111";datai <= "0010010111101000"; --561 + when "1010111100" => datar <= "1000011001110111";datai <= "0010100000100110"; --564 + when "1010111101" => datar <= "1000011100111001";datai <= "0010101001100001"; --567 + when "1010111110" => datar <= "1000100000000110";datai <= "0010110010011001"; --570 + when "1010111111" => datar <= "1000100011011110";datai <= "0010111011001100"; --573 + when "1011000000" => datar <= "1000100110111111";datai <= "0011000011111011"; --576 + when "1011000001" => datar <= "1000101010101011";datai <= "0011001100100110"; --579 + when "1011000010" => datar <= "1000101110100001";datai <= "0011010101001101"; --582 + when "1011000011" => datar <= "1000110010100010";datai <= "0011011101101111"; --585 + when "1011000100" => datar <= "1000110110101100";datai <= "0011100110001100"; --588 + when "1011000101" => datar <= "1000111011000000";datai <= "0011101110100101"; --591 + when "1011000110" => datar <= "1000111111011110";datai <= "0011110110111000"; --594 + when "1011000111" => datar <= "1001000100000101";datai <= "0011111111000101"; --597 + when "1011001000" => datar <= "1001001000110111";datai <= "0100000111001110"; --600 + when "1011001001" => datar <= "1001001101110010";datai <= "0100001111010000"; --603 + when "1011001010" => datar <= "1001010010110110";datai <= "0100010111001101"; --606 + when "1011001011" => datar <= "1001011000000011";datai <= "0100011111000011"; --609 + when "1011001100" => datar <= "1001011101011010";datai <= "0100100110110100"; --612 + when "1011001101" => datar <= "1001100010111010";datai <= "0100101110011101"; --615 + when "1011001110" => datar <= "1001101000100011";datai <= "0100110110000001"; --618 + when "1011001111" => datar <= "1001101110010100";datai <= "0100111101011101"; --621 + when "1011010000" => datar <= "1001110100001111";datai <= "0101000100110011"; --624 + when "1011010001" => datar <= "1001111010010010";datai <= "0101001100000010"; --627 + when "1011010010" => datar <= "1010000000011101";datai <= "0101010011001001"; --630 + when "1011010011" => datar <= "1010000110110001";datai <= "0101011010001010"; --633 + when "1011010100" => datar <= "1010001101001101";datai <= "0101100001000010"; --636 + when "1011010101" => datar <= "1010010011110001";datai <= "0101100111110011"; --639 + when "1011010110" => datar <= "1010011010011100";datai <= "0101101110011100"; --642 + when "1011010111" => datar <= "1010100001010000";datai <= "0101110100111110"; --645 + when "1011011000" => datar <= "1010101000001011";datai <= "0101111011010111"; --648 + when "1011011001" => datar <= "1010101111001110";datai <= "0110000001101000"; --651 + when "1011011010" => datar <= "1010110110011000";datai <= "0110000111110000"; --654 + when "1011011011" => datar <= "1010111101101001";datai <= "0110001101110000"; --657 + when "1011011100" => datar <= "1011000101000001";datai <= "0110010011101000"; --660 + when "1011011101" => datar <= "1011001100100000";datai <= "0110011001010110"; --663 + when "1011011110" => datar <= "1011010100000101";datai <= "0110011110111100"; --666 + when "1011011111" => datar <= "1011011011110001";datai <= "0110100100011001"; --669 + when "1011100000" => datar <= "1011100011100100";datai <= "0110101001101101"; --672 + when "1011100001" => datar <= "1011101011011100";datai <= "0110101110110111"; --675 + when "1011100010" => datar <= "1011110011011011";datai <= "0110110011111000"; --678 + when "1011100011" => datar <= "1011111011011111";datai <= "0110111000110000"; --681 + when "1011100100" => datar <= "1100000011101001";datai <= "0110111101011110"; --684 + when "1011100101" => datar <= "1100001011111001";datai <= "0111000010000011"; --687 + when "1011100110" => datar <= "1100010100001110";datai <= "0111000110011101"; --690 + when "1011100111" => datar <= "1100011100100111";datai <= "0111001010101110"; --693 + when "1011101000" => datar <= "1100100101000110";datai <= "0111001110110101"; --696 + when "1011101001" => datar <= "1100101101101010";datai <= "0111010010110010"; --699 + when "1011101010" => datar <= "1100110110010010";datai <= "0111010110100101"; --702 + when "1011101011" => datar <= "1100111110111111";datai <= "0111011010001101"; --705 + when "1011101100" => datar <= "1101000111101111";datai <= "0111011101101011"; --708 + when "1011101101" => datar <= "1101010000100100";datai <= "0111100000111111"; --711 + when "1011101110" => datar <= "1101011001011101";datai <= "0111100100001001"; --714 + when "1011101111" => datar <= "1101100010011001";datai <= "0111100111001000"; --717 + when "1011110000" => datar <= "1101101011011000";datai <= "0111101001111100"; --720 + when "1011110001" => datar <= "1101110100011011";datai <= "0111101100100110"; --723 + when "1011110010" => datar <= "1101111101100001";datai <= "0111101111000101"; --726 + when "1011110011" => datar <= "1110000110101001";datai <= "0111110001011001"; --729 + when "1011110100" => datar <= "1110001111110101";datai <= "0111110011100011"; --732 + when "1011110101" => datar <= "1110011001000010";datai <= "0111110101100010"; --735 + when "1011110110" => datar <= "1110100010010010";datai <= "0111110111010101"; --738 + when "1011110111" => datar <= "1110101011100100";datai <= "0111111000111110"; --741 + when "1011111000" => datar <= "1110110100111000";datai <= "0111111010011100"; --744 + when "1011111001" => datar <= "1110111110001110";datai <= "0111111011101111"; --747 + when "1011111010" => datar <= "1111000111100100";datai <= "0111111100110111"; --750 + when "1011111011" => datar <= "1111010000111100";datai <= "0111111101110100"; --753 + when "1011111100" => datar <= "1111011010010110";datai <= "0111111110100110"; --756 + when "1011111101" => datar <= "1111100011101111";datai <= "0111111111001101"; --759 + when "1011111110" => datar <= "1111101101001010";datai <= "0111111111101001"; --762 + when "1011111111" => datar <= "1111110110100101";datai <= "0111111111111001"; --765 + when "1100000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100000111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100001111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100010111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100011111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100100111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100101111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100110111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1100111111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101000111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101001111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101010111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101011111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101100111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101101111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101110111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101111111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110000111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110001111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110010111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110011111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110100111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110101111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110110111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110111111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111000111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111001111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111010111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111011111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111100111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111101111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111110111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111111111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when others => for i in data_width-1 downto 0 loop + datar(i)<='0';datai(i)<='0';end loop; + end case; + + end if; + +end process; +END behavior;
vhdl/WISHBONE_FFT/rom1.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/adder.vhd =================================================================== --- vhdl/WISHBONE_FFT/adder.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/adder.vhd (revision 5) @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity adder is + generic ( + inst_width : INTEGER := 32 + ); + port ( + inst_A : in std_logic_vector(inst_width-1 downto 0); + inst_B : in std_logic_vector(inst_width-1 downto 0 ); + SUM : out std_logic_vector(inst_width downto 0) + + ); + end adder; + +architecture oper of adder is + signal a_signed, b_signed, sum_signed: SIGNED(inst_width downto 0); +begin + a_signed <= SIGNED(inst_A(inst_width-1) & inst_A); + b_signed <= SIGNED(inst_B(inst_width-1) & inst_B); + sum_signed <= a_signed + b_signed; + SUM <= std_logic_vector(sum_signed); +end oper;
vhdl/WISHBONE_FFT/adder.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/rom2.vhd =================================================================== --- vhdl/WISHBONE_FFT/rom2.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/rom2.vhd (revision 5) @@ -0,0 +1,293 @@ +-- Rom file for twiddle factors +-- ../../../rtl/vhdl/WISHBONE_FFT/rom2.vhd contains 256 points of 16 width +-- for a 1024 point fft. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY rom2 IS + GENERIC( + data_width : integer :=16; + address_width : integer :=8 + ); + PORT( + clk :in std_logic; + address :in std_logic_vector (7 downto 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0) ; + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end rom2; +ARCHITECTURE behavior OF rom2 IS + + BEGIN + +process (address,clk) +begin + if(rising_edge(clk)) then + case address is + when "00000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "00000001" => datar <= "0111111111011000";datai <= "1111100110111000"; --8 + when "00000010" => datar <= "0111111101100001";datai <= "1111001101110100"; --16 + when "00000011" => datar <= "0111111010011100";datai <= "1110110100111000"; --24 + when "00000100" => datar <= "0111110110001001";datai <= "1110011100000111"; --32 + when "00000101" => datar <= "0111110000101001";datai <= "1110000011100110"; --40 + when "00000110" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "00000111" => datar <= "0111100010000100";datai <= "1101010011100001"; --56 + when "00001000" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "00001001" => datar <= "0111001110110101";datai <= "1100100101000110"; --72 + when "00001010" => datar <= "0111000011100010";datai <= "1100001110101010"; --80 + when "00001011" => datar <= "0110110111001001";datai <= "1011111000110010"; --88 + when "00001100" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "00001101" => datar <= "0110011011001111";datai <= "1011001111000001"; --104 + when "00001110" => datar <= "0110001011110001";datai <= "1010111011001101"; --112 + when "00001111" => datar <= "0101111011010111";datai <= "1010101000001011"; --120 + when "00010000" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "00010001" => datar <= "0101010111110101";datai <= "1010000100101001"; --136 + when "00010010" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "00010011" => datar <= "0100110000111111";datai <= "1001100100110001"; --152 + when "00010100" => datar <= "0100011100011100";datai <= "1001010110010011"; --160 + when "00010101" => datar <= "0100000111001110";datai <= "1001001000110111"; --168 + when "00010110" => datar <= "0011110001010110";datai <= "1000111100011110"; --176 + when "00010111" => datar <= "0011011010111010";datai <= "1000110001001011"; --184 + when "00011000" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "00011001" => datar <= "0010101100011111";datai <= "1000011101111100"; --200 + when "00011010" => datar <= "0010010100101000";datai <= "1000010110000100"; --208 + when "00011011" => datar <= "0001111100011010";datai <= "1000001111010111"; --216 + when "00011100" => datar <= "0001100011111001";datai <= "1000001001110111"; --224 + when "00011101" => datar <= "0001001011001000";datai <= "1000000101100100"; --232 + when "00011110" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "00011111" => datar <= "0000011001001000";datai <= "1000000000101000"; --248 + when "00100000" => datar <= "0000000000000000";datai <= "1000000000000001"; --256 + when "00100001" => datar <= "1111100110111000";datai <= "1000000000101000"; --264 + when "00100010" => datar <= "1111001101110100";datai <= "1000000010011111"; --272 + when "00100011" => datar <= "1110110100111000";datai <= "1000000101100100"; --280 + when "00100100" => datar <= "1110011100000111";datai <= "1000001001110111"; --288 + when "00100101" => datar <= "1110000011100110";datai <= "1000001111010111"; --296 + when "00100110" => datar <= "1101101011011000";datai <= "1000010110000100"; --304 + when "00100111" => datar <= "1101010011100001";datai <= "1000011101111100"; --312 + when "00101000" => datar <= "1100111100000101";datai <= "1000100110111111"; --320 + when "00101001" => datar <= "1100100101000110";datai <= "1000110001001011"; --328 + when "00101010" => datar <= "1100001110101010";datai <= "1000111100011110"; --336 + when "00101011" => datar <= "1011111000110010";datai <= "1001001000110111"; --344 + when "00101100" => datar <= "1011100011100100";datai <= "1001010110010011"; --352 + when "00101101" => datar <= "1011001111000001";datai <= "1001100100110001"; --360 + when "00101110" => datar <= "1010111011001101";datai <= "1001110100001111"; --368 + when "00101111" => datar <= "1010101000001011";datai <= "1010000100101001"; --376 + when "00110000" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "00110001" => datar <= "1010000100101001";datai <= "1010101000001011"; --392 + when "00110010" => datar <= "1001110100001111";datai <= "1010111011001101"; --400 + when "00110011" => datar <= "1001100100110001";datai <= "1011001111000001"; --408 + when "00110100" => datar <= "1001010110010011";datai <= "1011100011100100"; --416 + when "00110101" => datar <= "1001001000110111";datai <= "1011111000110010"; --424 + when "00110110" => datar <= "1000111100011110";datai <= "1100001110101010"; --432 + when "00110111" => datar <= "1000110001001011";datai <= "1100100101000110"; --440 + when "00111000" => datar <= "1000100110111111";datai <= "1100111100000101"; --448 + when "00111001" => datar <= "1000011101111100";datai <= "1101010011100001"; --456 + when "00111010" => datar <= "1000010110000100";datai <= "1101101011011000"; --464 + when "00111011" => datar <= "1000001111010111";datai <= "1110000011100110"; --472 + when "00111100" => datar <= "1000001001110111";datai <= "1110011100000111"; --480 + when "00111101" => datar <= "1000000101100100";datai <= "1110110100111000"; --488 + when "00111110" => datar <= "1000000010011111";datai <= "1111001101110100"; --496 + when "00111111" => datar <= "1000000000101000";datai <= "1111100110111000"; --504 + when "01000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "01000001" => datar <= "0111111111110101";datai <= "1111110011011100"; --4 + when "01000010" => datar <= "0111111111011000";datai <= "1111100110111000"; --8 + when "01000011" => datar <= "0111111110100110";datai <= "1111011010010110"; --12 + when "01000100" => datar <= "0111111101100001";datai <= "1111001101110100"; --16 + when "01000101" => datar <= "0111111100001001";datai <= "1111000001010101"; --20 + when "01000110" => datar <= "0111111010011100";datai <= "1110110100111000"; --24 + when "01000111" => datar <= "0111111000011101";datai <= "1110101000011110"; --28 + when "01001000" => datar <= "0111110110001001";datai <= "1110011100000111"; --32 + when "01001001" => datar <= "0111110011100011";datai <= "1110001111110101"; --36 + when "01001010" => datar <= "0111110000101001";datai <= "1110000011100110"; --40 + when "01001011" => datar <= "0111101101011100";datai <= "1101110111011101"; --44 + when "01001100" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "01001101" => datar <= "0111100110001001";datai <= "1101011111011010"; --52 + when "01001110" => datar <= "0111100010000100";datai <= "1101010011100001"; --56 + when "01001111" => datar <= "0111011101101011";datai <= "1101000111101111"; --60 + when "01010000" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "01010001" => datar <= "0111010100000100";datai <= "1100110000100001"; --68 + when "01010010" => datar <= "0111001110110101";datai <= "1100100101000110"; --72 + when "01010011" => datar <= "0111001001010100";datai <= "1100011001110100"; --76 + when "01010100" => datar <= "0111000011100010";datai <= "1100001110101010"; --80 + when "01010101" => datar <= "0110111101011110";datai <= "1100000011101001"; --84 + when "01010110" => datar <= "0110110111001001";datai <= "1011111000110010"; --88 + when "01010111" => datar <= "0110110000100011";datai <= "1011101110000110"; --92 + when "01011000" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "01011001" => datar <= "0110100010100110";datai <= "1011011001001100"; --100 + when "01011010" => datar <= "0110011011001111";datai <= "1011001111000001"; --104 + when "01011011" => datar <= "0110010011101000";datai <= "1011000101000001"; --108 + when "01011100" => datar <= "0110001011110001";datai <= "1010111011001101"; --112 + when "01011101" => datar <= "0110000011101011";datai <= "1010110001100101"; --116 + when "01011110" => datar <= "0101111011010111";datai <= "1010101000001011"; --120 + when "01011111" => datar <= "0101110010110011";datai <= "1010011110111110"; --124 + when "01100000" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "01100001" => datar <= "0101100001000010";datai <= "1010001101001101"; --132 + when "01100010" => datar <= "0101010111110101";datai <= "1010000100101001"; --136 + when "01100011" => datar <= "0101001110011011";datai <= "1001111100010101"; --140 + when "01100100" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "01100101" => datar <= "0100111010111111";datai <= "1001101100011000"; --148 + when "01100110" => datar <= "0100110000111111";datai <= "1001100100110001"; --152 + when "01100111" => datar <= "0100100110110100";datai <= "1001011101011010"; --156 + when "01101000" => datar <= "0100011100011100";datai <= "1001010110010011"; --160 + when "01101001" => datar <= "0100010001111010";datai <= "1001001111011101"; --164 + when "01101010" => datar <= "0100000111001110";datai <= "1001001000110111"; --168 + when "01101011" => datar <= "0011111100010111";datai <= "1001000010100010"; --172 + when "01101100" => datar <= "0011110001010110";datai <= "1000111100011110"; --176 + when "01101101" => datar <= "0011100110001100";datai <= "1000110110101100"; --180 + when "01101110" => datar <= "0011011010111010";datai <= "1000110001001011"; --184 + when "01101111" => datar <= "0011001111011111";datai <= "1000101011111100"; --188 + when "01110000" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "01110001" => datar <= "0010111000010001";datai <= "1000100010010101"; --196 + when "01110010" => datar <= "0010101100011111";datai <= "1000011101111100"; --200 + when "01110011" => datar <= "0010100000100110";datai <= "1000011001110111"; --204 + when "01110100" => datar <= "0010010100101000";datai <= "1000010110000100"; --208 + when "01110101" => datar <= "0010001000100011";datai <= "1000010010100100"; --212 + when "01110110" => datar <= "0001111100011010";datai <= "1000001111010111"; --216 + when "01110111" => datar <= "0001110000001011";datai <= "1000001100011101"; --220 + when "01111000" => datar <= "0001100011111001";datai <= "1000001001110111"; --224 + when "01111001" => datar <= "0001010111100010";datai <= "1000000111100011"; --228 + when "01111010" => datar <= "0001001011001000";datai <= "1000000101100100"; --232 + when "01111011" => datar <= "0000111110101011";datai <= "1000000011110111"; --236 + when "01111100" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "01111101" => datar <= "0000100101101010";datai <= "1000000001011010"; --244 + when "01111110" => datar <= "0000011001001000";datai <= "1000000000101000"; --248 + when "01111111" => datar <= "0000001100100100";datai <= "1000000000001011"; --252 + when "10000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "10000001" => datar <= "0111111110100110";datai <= "1111011010010110"; --12 + when "10000010" => datar <= "0111111010011100";datai <= "1110110100111000"; --24 + when "10000011" => datar <= "0111110011100011";datai <= "1110001111110101"; --36 + when "10000100" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "10000101" => datar <= "0111011101101011";datai <= "1101000111101111"; --60 + when "10000110" => datar <= "0111001110110101";datai <= "1100100101000110"; --72 + when "10000111" => datar <= "0110111101011110";datai <= "1100000011101001"; --84 + when "10001000" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "10001001" => datar <= "0110010011101000";datai <= "1011000101000001"; --108 + when "10001010" => datar <= "0101111011010111";datai <= "1010101000001011"; --120 + when "10001011" => datar <= "0101100001000010";datai <= "1010001101001101"; --132 + when "10001100" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "10001101" => datar <= "0100100110110100";datai <= "1001011101011010"; --156 + when "10001110" => datar <= "0100000111001110";datai <= "1001001000110111"; --168 + when "10001111" => datar <= "0011100110001100";datai <= "1000110110101100"; --180 + when "10010000" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "10010001" => datar <= "0010100000100110";datai <= "1000011001110111"; --204 + when "10010010" => datar <= "0001111100011010";datai <= "1000001111010111"; --216 + when "10010011" => datar <= "0001010111100010";datai <= "1000000111100011"; --228 + when "10010100" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "10010101" => datar <= "0000001100100100";datai <= "1000000000001011"; --252 + when "10010110" => datar <= "1111100110111000";datai <= "1000000000101000"; --264 + when "10010111" => datar <= "1111000001010101";datai <= "1000000011110111"; --276 + when "10011000" => datar <= "1110011100000111";datai <= "1000001001110111"; --288 + when "10011001" => datar <= "1101110111011101";datai <= "1000010010100100"; --300 + when "10011010" => datar <= "1101010011100001";datai <= "1000011101111100"; --312 + when "10011011" => datar <= "1100110000100001";datai <= "1000101011111100"; --324 + when "10011100" => datar <= "1100001110101010";datai <= "1000111100011110"; --336 + when "10011101" => datar <= "1011101110000110";datai <= "1001001111011101"; --348 + when "10011110" => datar <= "1011001111000001";datai <= "1001100100110001"; --360 + when "10011111" => datar <= "1010110001100101";datai <= "1001111100010101"; --372 + when "10100000" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "10100001" => datar <= "1001111100010101";datai <= "1010110001100101"; --396 + when "10100010" => datar <= "1001100100110001";datai <= "1011001111000001"; --408 + when "10100011" => datar <= "1001001111011101";datai <= "1011101110000110"; --420 + when "10100100" => datar <= "1000111100011110";datai <= "1100001110101010"; --432 + when "10100101" => datar <= "1000101011111100";datai <= "1100110000100001"; --444 + when "10100110" => datar <= "1000011101111100";datai <= "1101010011100001"; --456 + when "10100111" => datar <= "1000010010100100";datai <= "1101110111011101"; --468 + when "10101000" => datar <= "1000001001110111";datai <= "1110011100000111"; --480 + when "10101001" => datar <= "1000000011110111";datai <= "1111000001010101"; --492 + when "10101010" => datar <= "1000000000101000";datai <= "1111100110111000"; --504 + when "10101011" => datar <= "1000000000001011";datai <= "0000001100100100"; --516 + when "10101100" => datar <= "1000000010011111";datai <= "0000110010001100"; --528 + when "10101101" => datar <= "1000000111100011";datai <= "0001010111100010"; --540 + when "10101110" => datar <= "1000001111010111";datai <= "0001111100011010"; --552 + when "10101111" => datar <= "1000011001110111";datai <= "0010100000100110"; --564 + when "10110000" => datar <= "1000100110111111";datai <= "0011000011111011"; --576 + when "10110001" => datar <= "1000110110101100";datai <= "0011100110001100"; --588 + when "10110010" => datar <= "1001001000110111";datai <= "0100000111001110"; --600 + when "10110011" => datar <= "1001011101011010";datai <= "0100100110110100"; --612 + when "10110100" => datar <= "1001110100001111";datai <= "0101000100110011"; --624 + when "10110101" => datar <= "1010001101001101";datai <= "0101100001000010"; --636 + when "10110110" => datar <= "1010101000001011";datai <= "0101111011010111"; --648 + when "10110111" => datar <= "1011000101000001";datai <= "0110010011101000"; --660 + when "10111000" => datar <= "1011100011100100";datai <= "0110101001101101"; --672 + when "10111001" => datar <= "1100000011101001";datai <= "0110111101011110"; --684 + when "10111010" => datar <= "1100100101000110";datai <= "0111001110110101"; --696 + when "10111011" => datar <= "1101000111101111";datai <= "0111011101101011"; --708 + when "10111100" => datar <= "1101101011011000";datai <= "0111101001111100"; --720 + when "10111101" => datar <= "1110001111110101";datai <= "0111110011100011"; --732 + when "10111110" => datar <= "1110110100111000";datai <= "0111111010011100"; --744 + when "10111111" => datar <= "1111011010010110";datai <= "0111111110100110"; --756 + when "11000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11000111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11001111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11010111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11011111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11100111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11101111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11110111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "11111111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when others => for i in data_width-1 downto 0 loop + datar(i)<='0';datai(i)<='0';end loop; + end case; + + end if; + +end process; +END behavior;
vhdl/WISHBONE_FFT/rom2.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/.vhd =================================================================== --- vhdl/WISHBONE_FFT/.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/.vhd (revision 5) @@ -0,0 +1,55 @@ + +-- hds header_start +--1 stage shift register, data_width bits wide. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY shiftreg1 IS + GENERIC( + data_width : integer := 25 + ); + PORT( + clock : IN std_logic; + enable : in std_logic; + clear : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); + +-- Declarations + +END shiftreg1 ; + +-- hds interface_end +ARCHITECTURE behavior OF shiftreg1 IS +--signal reg00 : std_logic_vector(data_width-1 downto 0); +BEGIN +process(Clock,resetn) +begin +if (resetn='0') then +-- for i in data_width-1 downto 0 loop +-- r eg00(i)<='0'; + read_data <= (others => '0'); +-- end loop; + elsif (Clock'event and Clock='1') then + + if (enable='1') then + + if(clear ='1') then +-- reg00<=write_data; +-- read _data<=reg00; + read_data <= (others => '0'); + + else + read_data <= write_data; + + + end if; + end if; + end if; +end process; +END behavior; Index: vhdl/WISHBONE_FFT/rom3.vhd =================================================================== --- vhdl/WISHBONE_FFT/rom3.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/rom3.vhd (revision 5) @@ -0,0 +1,101 @@ +-- Rom file for twiddle factors +-- ../../../rtl/vhdl/WISHBONE_FFT/rom3.vhd contains 64 points of 16 width +-- for a 1024 point fft. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY rom3 IS + GENERIC( + data_width : integer :=16; + address_width : integer :=6 + ); + PORT( + clk :in std_logic; + address :in std_logic_vector (5 downto 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0) ; + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end rom3; +ARCHITECTURE behavior OF rom3 IS + + BEGIN + +process (address,clk) +begin + if(rising_edge(clk)) then + case address is + when "000000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "000001" => datar <= "0111110110001001";datai <= "1110011100000111"; --32 + when "000010" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "000011" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "000100" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "000101" => datar <= "0100011100011100";datai <= "1001010110010011"; --160 + when "000110" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "000111" => datar <= "0001100011111001";datai <= "1000001001110111"; --224 + when "001000" => datar <= "0000000000000000";datai <= "1000000000000001"; --256 + when "001001" => datar <= "1110011100000111";datai <= "1000001001110111"; --288 + when "001010" => datar <= "1100111100000101";datai <= "1000100110111111"; --320 + when "001011" => datar <= "1011100011100100";datai <= "1001010110010011"; --352 + when "001100" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "001101" => datar <= "1001010110010011";datai <= "1011100011100100"; --416 + when "001110" => datar <= "1000100110111111";datai <= "1100111100000101"; --448 + when "001111" => datar <= "1000001001110111";datai <= "1110011100000111"; --480 + when "010000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "010001" => datar <= "0111111101100001";datai <= "1111001101110100"; --16 + when "010010" => datar <= "0111110110001001";datai <= "1110011100000111"; --32 + when "010011" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "010100" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "010101" => datar <= "0111000011100010";datai <= "1100001110101010"; --80 + when "010110" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "010111" => datar <= "0110001011110001";datai <= "1010111011001101"; --112 + when "011000" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "011001" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "011010" => datar <= "0100011100011100";datai <= "1001010110010011"; --160 + when "011011" => datar <= "0011110001010110";datai <= "1000111100011110"; --176 + when "011100" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "011101" => datar <= "0010010100101000";datai <= "1000010110000100"; --208 + when "011110" => datar <= "0001100011111001";datai <= "1000001001110111"; --224 + when "011111" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "100000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "100001" => datar <= "0111101001111100";datai <= "1101101011011000"; --48 + when "100010" => datar <= "0110101001101101";datai <= "1011100011100100"; --96 + when "100011" => datar <= "0101000100110011";datai <= "1001110100001111"; --144 + when "100100" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "100101" => datar <= "0000110010001100";datai <= "1000000010011111"; --240 + when "100110" => datar <= "1110011100000111";datai <= "1000001001110111"; --288 + when "100111" => datar <= "1100001110101010";datai <= "1000111100011110"; --336 + when "101000" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "101001" => datar <= "1000111100011110";datai <= "1100001110101010"; --432 + when "101010" => datar <= "1000001001110111";datai <= "1110011100000111"; --480 + when "101011" => datar <= "1000000010011111";datai <= "0000110010001100"; --528 + when "101100" => datar <= "1000100110111111";datai <= "0011000011111011"; --576 + when "101101" => datar <= "1001110100001111";datai <= "0101000100110011"; --624 + when "101110" => datar <= "1011100011100100";datai <= "0110101001101101"; --672 + when "101111" => datar <= "1101101011011000";datai <= "0111101001111100"; --720 + when "110000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "110111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111001" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111010" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111011" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "111111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when others => for i in data_width-1 downto 0 loop + datar(i)<='0';datai(i)<='0';end loop; + end case; + + end if; + +end process; +END behavior;
vhdl/WISHBONE_FFT/rom3.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/fft_pkg.vhd =================================================================== --- vhdl/WISHBONE_FFT/fft_pkg.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/fft_pkg.vhd (revision 5) @@ -0,0 +1,20 @@ + +library IEEE; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + +package fft_pkg is + type ioarray is array (integer range <>) of std_logic_vector(255 downto 0); + function log2(A: integer) return integer; +end; + +package body fft_pkg is + function log2(A: integer) return integer is + begin + for I in 1 to 30 loop -- Works for up to 32 bit integers + if (2**I > A) then return(I-1); + end if; + end loop; + return(30); + end; +end;
vhdl/WISHBONE_FFT/fft_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/rom4.vhd =================================================================== --- vhdl/WISHBONE_FFT/rom4.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/rom4.vhd (revision 5) @@ -0,0 +1,53 @@ +-- Rom file for twiddle factors +-- ../../../rtl/vhdl/WISHBONE_FFT/rom4.vhd contains 16 points of 16 width +-- for a 1024 point fft. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY rom4 IS + GENERIC( + data_width : integer :=16; + address_width : integer :=4 + ); + PORT( + clk :in std_logic; + address :in std_logic_vector (3 downto 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0) ; + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end rom4; +ARCHITECTURE behavior OF rom4 IS + + BEGIN + +process (address,clk) +begin + if(rising_edge(clk)) then + case address is + when "0000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "0001" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "0010" => datar <= "0000000000000000";datai <= "1000000000000001"; --256 + when "0011" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "0100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "0101" => datar <= "0111011001000001";datai <= "1100111100000101"; --64 + when "0110" => datar <= "0101101010000010";datai <= "1010010101111110"; --128 + when "0111" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "1000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1001" => datar <= "0011000011111011";datai <= "1000100110111111"; --192 + when "1010" => datar <= "1010010101111110";datai <= "1010010101111110"; --384 + when "1011" => datar <= "1000100110111111";datai <= "0011000011111011"; --576 + when "1100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when "1111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0 + when others => for i in data_width-1 downto 0 loop + datar(i)<='0';datai(i)<='0';end loop; + end case; + + end if; + +end process; +END behavior;
vhdl/WISHBONE_FFT/rom4.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/BF2I.vhd =================================================================== --- vhdl/WISHBONE_FFT/BF2I.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/BF2I.vhd (revision 5) @@ -0,0 +1,167 @@ + +--Butterfly stage type 1 +--7/17/02 + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity BF2I is + +generic ( + data_width : INTEGER :=13; + add_g : INTEGER :=1 + ); + +port ( + fromreg_r :in std_logic_vector(data_width-1 downto 0); + fromreg_i :in std_logic_vector(data_width-1 downto 0); + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + s : in std_logic; + toreg_r :out std_logic_vector(data_width-1 downto 0); + toreg_i :out std_logic_vector(data_width-1 downto 0); + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); + +end BF2I; + +architecture behavior of BF2I is +signal prvs_ext_r : std_logic_vector(data_width-1 downto 0); +signal prvs_ext_i : std_logic_vector(data_width-1 downto 0); +signal add1_out : std_logic_vector(data_width downto 0); +signal add2_out : std_logic_vector(data_width downto 0); +signal sub1_out : std_logic_vector(data_width downto 0); +signal sub2_out : std_logic_vector(data_width downto 0); + +component adder + generic ( + inst_width:integer + ); + port( + inst_A : in std_logic_vector(data_width-1 downto 0); + inst_B : in std_logic_vector(data_width-1 downto 0); + SUM : out std_logic_vector(data_width downto 0) + ); +end component; + +component subtract + generic ( + inst_width:integer + ); + port( + inst_A : in std_logic_vector(data_width-1 downto 0); + inst_B : in std_logic_vector(data_width-1 downto 0); + DIFF : out std_logic_vector(data_width downto 0) + ); +end component; + +component mux2_mmw + generic (data_width:integer); + port( + s : in std_logic; + in0: in std_logic_vector(data_width-1 downto 0); + in1: in std_logic_vector(data_width downto 0); + data: out std_logic_vector(data_width-1 downto 0) + ); +end component; + +begin + + add1 : adder + generic map ( +inst_width=>data_width + ) + port map ( + inst_A=>prvs_ext_r, + inst_B=>fromreg_r, + SUM=>add1_out + ); + + add2 : adder + generic map ( + inst_width=>data_width +) + port map ( + inst_A=>prvs_ext_i, + inst_B=>fromreg_i, + SUM=>add2_out + ); + + sub1 : subtract + generic map ( + inst_width=>data_width + ) + port map ( + inst_A=>fromreg_r, + inst_B=>prvs_ext_r, + DIFF=>sub1_out + ); + + sub2 : subtract + generic map ( + inst_width=>data_width + ) + port map ( + inst_A=>fromreg_i, + inst_B=>prvs_ext_i, + DIFF=>sub2_out + ); + + mux_1 : mux2_mmw + generic map ( + data_width=>data_width + ) + port map ( + s=>s, + in0=>fromreg_r, + in1=>add1_out, + data=>tonext_r + ); + + mux_2 : mux2_mmw + generic map ( + data_width=>data_width + ) + port map ( + s=>s, + in0=>fromreg_i, + in1=>add2_out, + data=>tonext_i + ); + + mux_3 : mux2_mmw + generic map ( + data_width=>data_width + ) + port map ( + s=>s, + in0=>prvs_ext_r, + in1=>sub1_out, + data=>toreg_r + ); + + mux_4 : mux2_mmw + generic map ( + data_width=>data_width + ) + port map ( + s=>s, + in0=>prvs_ext_i, + in1=>sub2_out, + data=>toreg_i); + +process(prvs_r, prvs_i) +begin + if add_g=1 then + prvs_ext_r <= prvs_r(data_width-2) & prvs_r; + prvs_ext_i <= prvs_i(data_width-2) & prvs_i; + else + prvs_ext_r <= prvs_r; + prvs_ext_i <= prvs_i; + end if; +end process; + +end; +
vhdl/WISHBONE_FFT/BF2I.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/stage_II.vhd =================================================================== --- vhdl/WISHBONE_FFT/stage_II.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/stage_II.vhd (revision 5) @@ -0,0 +1,201 @@ + +--Component for Stages using BF2II (second and every even stage) +--Doesn 't handle last stage +--Input is a stand ard logic vector of data_width-add_g +--data_width - width of the internal busses +-- Add growth variable - if 1, data_width gro add_g - ws by 1, if 0 then 0 +--mult_g - mult g rowth variable - can r ange from 0 to twiddle_width+1 +--twiddle_width - width of the twiddle factor input +--shift_stages - number of shift register stages +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity stage_II is +generic ( + data_width : INTEGER :=14; + add_g : INTEGER := 1; + mult_g : INTEGER :=9; + twiddle_width : INTEGER :=10; + shift_stages : INTEGER := 16 + ); + +port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width -1-add_g downto 0); + t :in std_logic; + s :in std_logic; + clock : in std_logic; + enable : in std_logic; + resetn : in std_logic; + fromrom_r :in std_logic_vector(twiddle_width-1 downto 0); + fromrom_i :in std_logic_vector(twiddle_width-1 downto 0); + tonext_r :out std_logic_vector(data_width+mult_g-1 downto 0) ; + tonext_i :out std_logic_vector(data_width+mult_g-1 downto 0 ) + ); +end stage_II; + +architecture structure of stage_II is +signal toreg_r : std_logic_vector(data_width-1 downto 0); +signal toreg_i : std_logic_vector(data_width-1 downto 0); +signal fromreg_r : std_logic_vector(data_width-1 downto 0); +signal fromreg_i : std_logic_vector(data_width-1 downto 0); +signal tomult_r : std_logic_vector(data_width-1 downto 0); +signal tomult_i : std_logic_vector(data_width-1 downto 0); + +signal tonext_r_aux : std_logic_vector(data_width+mult_g-1 downto 0); +signal tonext_i_aux : std_logic_vector(data_width+mult_g-1 downto 0); + +component shiftregN + generic ( + data_width : integer; + n : integer +); + port ( + clock : IN std_logic; + enable : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); +end component; + +component shiftreg1 + generic ( + data_width : integer +); + port ( + clock : IN std_logic; + enable: in std_logic; + clear: in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); +end component; + + +component BF2II + generic ( + data_width : INTEGER; + add_g: INTEGER + ); + port ( + fromreg_r :in std_logic_vector(data_width-1 downto 0); + fromreg_i :in std_logic_vector(data_width-1 downto 0); + prvs_r :in std_logic_vector(data_width-add_g-1 downto 0); + prvs_i :in std_logic_vector(data_width-add_g-1 downto 0); + t : in std_logic; + s : in std_logic; + toreg_r :out std_logic_vector(data_width-1 downto 0); + toreg_i :out std_logic_vector(data_width-1 downto 0); + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); +end component; + +component twiddle_mult + generic ( + mult_width : INTEGER; + twiddle_width : INTEGER; + output_width : INTEGER +); + port ( + data_r :in std_logic_vector(mult_width-1 downto 0); + data_i :in std_logic_vector(mult_width-1 downto 0); + twdl_r :in std_logic_vector(twiddle_width-1 downto 0) ; + twdl_i :in std_logic_vector(twiddle_width-1 downto 0); + out_r :out std_logic_vector(output_width-1 downto 0); + out_i :out std_logic_vector(output_width-1 downto 0) + ); +end component; + +begin +regr : shiftregN + generic map ( + data_width=>data_width, n=>shift_stages +) + port map ( + clock=>clock, + enable=>enable, + read_data=>fromreg_r, + write_data=>toreg_r, + resetn=>resetn + ); + +regi : shiftregN + generic map ( + data_width=>data_width, + n=>shift_stages + ) + port map ( + clock=>clock, + enable=>enable, + read_data=>fromreg_i, + write_data=>toreg_i, + resetn=>resetn + ); + +btrfly : BF2II + generic map ( + data_width=>data_width, + add_g=>add_g + ) + port map ( + fromreg_r=>fromreg_r, + fromreg_i=>fromreg_i, + prvs_r=>prvs_r, prvs_i=>prvs_i, + t=>t, + s=>s, + toreg_r=>toreg_r, + toreg_i=>toreg_i, + tonext_r=>tomult_r, + tonext_i =>tomult_i + ); + +twiddle : twiddle_mult + generic map ( + mult_width=>data_width, + twiddle_width=>twiddle_width, + output_width=> data_width+mult_g + ) + port map ( + data_r=>tomult_r, + data_i=>tomult_i, + twdl_r=>fromrom_r, + twdl_i=>fromrom_i, + out_r=>tonext_r_aux, + out_i=>tonext_i_aux + ); + + +regsegr : shiftreg1 + generic map ( + data_width=>data_width+mult_g + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_r, + write_data=>tonext_r_aux, + resetn=>resetn + ); + +regsegi : shiftreg1 + generic map ( + data_width=>data_width+mult_g + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_i, + write_data=>tonext_i_aux, + resetn=>resetn + ); + + +end;
vhdl/WISHBONE_FFT/stage_II.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/multiplier.vhd =================================================================== --- vhdl/WISHBONE_FFT/multiplier.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/multiplier.vhd (revision 5) @@ -0,0 +1,25 @@ + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity multiplier is + generic ( + inst_width1 : INTEGER := 16; + inst_width2 : INTEGER := 16 + ); + port ( + inst_A : in std_logic_vector(inst_width1-1 downto 0); + inst_B : in std_logic_vector(inst_width2-1 downto 0); + PRODUCT_inst : out std_logic_vector(inst_width1 + inst_width2 - 1 downto 0) + + ); + end multiplier; + +architecture oper of multiplier is + signal mult_sig : SIGNED(inst_width1+inst_width2-1 downto 0) ; + +begin + mult_sig <= SIGNED(inst_A) * SIGNED(inst_B); + PRODUCT_inst <= std_logic_vector(mult_sig); +end oper;
vhdl/WISHBONE_FFT/multiplier.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/subtract.vhd =================================================================== --- vhdl/WISHBONE_FFT/subtract.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/subtract.vhd (revision 5) @@ -0,0 +1,27 @@ + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity subtract is + generic ( + inst_width : INTEGER := 32 + ); + port ( + inst_A : in std_logic_vector(inst_width-1 downto 0); + inst_B : in std_logic_vector(inst_width-1 downto 0); + DIFF : out std_logic_vector(inst_width downto 0) + + ); + end subtract; + +architecture oper of subtract is + signal a_signed, b_signed, diff_signed: SIGNED(inst_width downto 0); + +begin + a_signed <= SIGNED(inst_A(inst_width-1) & inst_A); + b_signed <= SIGNED(inst_B(inst_width-1) & inst_B); + diff_signed <= a_signed - b_signed; + DIFF <= std_logic_vector(diff_signed); +end oper; +
vhdl/WISHBONE_FFT/subtract.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/shiftregN.vhd =================================================================== --- vhdl/WISHBONE_FFT/shiftregN.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/shiftregN.vhd (revision 5) @@ -0,0 +1,72 @@ +-- hds header_start +-- age shift registe -n st r, data_width bits wide. + +LIBRARY ieee ; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY shiftregN IS + GENERIC( + data_width : integer := 25; + n : integer := 254 + ); + PORT( + clock : IN std_logic; + enable : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); + +-- Declarations + +END shiftregN ; + +-- hds interface_end +ARCHITECTURE behavior OF shiftregN IS + +type regArray is array (0 to n) of std_logic_vector(data_width-1 downto 0); + +signal registerFile : regArray; + +component shiftreg1 IS + GENERIC( + data_width : integer := 25 + ); + PORT( + clock : IN std_logic; + enable : in std_logic; + clear : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); + +-- Declarations + +END component; +BEGIN + +registerFile(0)<=write_data; +read_data<=registerFile(n); + +registers: for i in 0 to n-1 generate + +regi: shiftreg1 generic map( +data_width=>data_width + +) +port map( +clock=>clock, + enable=>enable, + clear=>'0', + read_data=>registerFile(i+1), + write_data=>registerFile(i), + resetn=>resetn + +); + +end generate; + +END behavior;
vhdl/WISHBONE_FFT/shiftregN.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/interface_slave_fft.vhd =================================================================== --- vhdl/WISHBONE_FFT/interface_slave_fft.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/interface_slave_fft.vhd (revision 5) @@ -0,0 +1,191 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +--use work.fft_pkg.all; + +entity interface_slave_fft is +generic( +N: integer:=1024; +data_wordwidth: integer:=32; +adress_wordwidth: integer:=32; +reg_control:integer:=0; +reg_data:integer:=4; +reg_status:integer:=8; +reg_memory:integer:=12 + + +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( adress_wordwidth-1 downto 0 ); + ADR_FFT: in std_logic_vector( integer(ceil(log2(real(N))))-1 downto 0 ); + DAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + FFT_finish_in: in std_logic;--from SLAVE + FFT_enable: out std_logic;--to SLAVE + enable_in: in std_logic;--from SLAVE + clear_out: out std_logic;--to SLAVE + clk: in std_logic + ); +end entity; + +architecture RTL of interface_slave_fft is + +component ramsita IS + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END component; + +component RAM_Memory is +generic( + +Add_WordWidth: integer; +Data_WordWidth: integer +); +port( + + + DATi: in std_logic_vector( Data_WordWidth-1 downto 0 ); + DATo: out std_logic_vector( Data_WordWidth-1 downto 0 ); + ADR_WB: in std_logic_vector( Add_WordWidth-1 downto 0 ); + ADR_FFT: in std_logic_vector( Add_WordWidth-1 downto 0 ); + W_R: in std_logic; + clk: in std_logic + + ); +end component; + +signal OUT_AUX,OUT_AUX1, ZERO: std_logic_vector( Data_wordwidth-1 downto 0 ); +signal ADD_aux:std_logic_vector( integer(ceil(log2(real((N+3)*4))))-1 downto 0 ); + +signal ack_r, ack_w: std_logic; + +begin + + OUT_AUX<=DAT_I; + ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth)); + + + + ACK_O<=ack_r or ack_w; + + --Reconocimiento de escritura sin estado de espera + ack_w<= '1' when (STB_I='1' and WE_I='1') else '0'; + + + + --Reconocimiento de lectura con 1 estado de espera, caso RAM sincrona + process(clk) + + begin + if(rising_edge(clk)) then + if(STB_I='1' and WE_I='0') then + + ack_r<='1'; + else + ack_r<='0'; + + end if; + end if; + + end process; + + + --Se elimina offset para direcciones de lectura de memoria RAM + ADD_aux<=std_logic_vector(unsigned(ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0))-(reg_memory)); + + RAM: RAM_Memory +generic map( + +Add_WordWidth=>integer(ceil(log2(real(N)))), +Data_WordWidth=>Data_WordWidth +) +port map( + + + DATi=>sDAT_I, + DATo=>OUT_AUX1, + --Divide entre cuatro, direcciones alineadas cada 4 bytes + ADR_WB=>ADD_aux(integer(ceil(log2(real((N)))))+1 downto 2), + ADR_FFT=>ADR_FFT(integer(ceil(log2(real(N))))-1 downto 0), + W_R=>enable_in, + clk=>clk + ); + + + --Decodificador de escritura + process(ADR_I,STB_I,WE_I,ZERO,OUT_AUX,OUT_AUX1,FFT_finish_in) + begin + + + if (WE_I='1' and STB_I='1') then--ESCRIBIR EN FFT + case ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0) is + + when std_logic_vector(to_unsigned(Reg_control,integer(ceil(log2(real((N+3)*4)))))) => + clear_out<='1'; + FFT_enable<='1'; + sDAT_O<=ZERO; + when std_logic_vector(to_unsigned(Reg_data,integer(ceil(log2(real((N+3)*4))))))=> + sDAT_O<=OUT_AUX; + FFT_enable<='1'; + clear_out<='0'; + + when OTHERS => sDAT_O<=ZERO; + clear_out<='0'; + FFT_enable<='0'; + end case; + + else + sDAT_O<=ZERO; + clear_out<='0'; + FFT_enable<='0'; + end if; + + + + end process; + + --Decodificador de lectura + process(ADR_I,STB_I,WE_I,ZERO,OUT_AUX,OUT_AUX1,FFT_finish_in) + begin + + + + if (WE_I='0' and STB_I='1') then + + + + if ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0) = std_logic_vector(to_unsigned(Reg_status,integer(ceil(log2(real((N+3)*4)))))) then + + DAT_O(0)<=FFT_finish_in; + DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1); + else + DAT_O<=OUT_AUX1; + + end if; + + else + DAT_O<=ZERO; + end if; + +end process; + + + +end architecture; + + +
vhdl/WISHBONE_FFT/interface_slave_fft.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/BF2II.vhd =================================================================== --- vhdl/WISHBONE_FFT/BF2II.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/BF2II.vhd (revision 5) @@ -0,0 +1,135 @@ +--Butterfly stage type 2 +--7/17/0 2 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity BF2II is + +generic ( data_width : INTEGER :=13; + add_g: INTEGER :=1 + ); + +port ( fromreg_r :in std_logic_vector(data_width-1 downto +0 ); + fromreg_i :in std_logic_vector(data_width-1 downto +0) ; + prvs_r :in std_logic_vector(data_width-1-add_g downto +0) ; + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + t : in std_logic; + s : in std_logic; + toreg_r :out std_logic_vector(data_width -1 downto 0); + + toreg_i :out std_logic_vector(data_width -1 downto 0); + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); + +end BF2II; + +architecture behavior of BF2II is +signal prvs_ext_r : std_logic_vector(data_width-1 downto 0); +signal prvs_ext_i : std_logic_vector(data_width-1 downto 0); +signal add1_out : std_logic_vector(data_width downto 0); +signal add2_out : std_logic_vector(data_width downto 0); +signal sub1_out : std_logic_vector(data_width downto 0); +signal sub2_out : std_logic_vector(data_width downto 0); +signal swapadd : std_logic_vector(data_width downto 0); +signal swapsub : std_logic_vector(data_width downto 0); + +component adder + generic (inst_width:integer); + port( + inst_A : in std_logic_vector( data_width-1 downto 0); + inst_B : in std_logic_vector( data_width-1 downto 0); + SUM : out std_logic_vector(data_width downto 0) + ); +end component; + +component subtract + generic (inst_width:integer); + port( + inst_A : in std_logic_vector(data_width-1 downto 0); + inst_B : in std_logic_vector(data_width-1 downto 0); + DIFF : out std_logic_vector(data_width downto 0) + ); +end component; + +component mux2_mmw + generic (data_width:integer); + port( + s : in std_logic; + in0: in std_logic_vector(data_width-1 downto 0); + in1: in std_logic_vector(data_width downto 0); + data: out std_logic_vector(data_width-1 downto 0) + ); +end component; + +begin + + add1 : adder + generic map (inst_width=>data_width) + port map (inst_A=>prvs_ext_r, inst_B=>fromreg_r, SUM=>add1_out); + + add2 : adder + generic map (inst_width=>data_width) + port map (inst_A=>prvs_ext_i, inst_B=>fromreg_i, SUM=>add2_out); + + sub1 : subtract + generic map (inst_width=>data_width) + port map (inst_A=>fromreg_r, inst_B=>prvs_ext_r, DIFF=>sub1_out); + + sub2 : subtract + generic map (inst_width=>data_width) + port map (inst_A=>fromreg_i, inst_B=>prvs_ext_i, DIFF=>sub2_out); + + mux_1 : mux2_mmw + generic map (data_width=>data_width) + port map (s=>s, in0=>fromreg_r, in1=>add1_out, data=>tonext_r); + + mux_2 : mux2_mmw + generic map (data_width=>data_width) + port map (s=>s, in0=>fromreg_i, in1=>swapadd, data=>tonext_i); + + mux_3 : mux2_mmw + generic map (data_width=>data_width) + port map (s=>s, in0=>prvs_ext_r, in1=>sub1_out, data=>toreg_r); + + mux_4 : mux2_mmw + generic map (data_width=>data_width) + port map (s=>s, in0=>prvs_ext_i, in1=>swapsub, data=>toreg_i); +process(prvs_r,prvs_i,s,t) +begin + if add_g=1 then + if (t='0' and s='1') then + prvs_ext_r <= prvs_i(data_width-2) & prvs_i; + prvs_ext_i <= prvs_r(data_width-2) & prvs_r; + else + prvs_ext_r <= prvs_r(data_width-2) & prvs_r; + prvs_ext_i <= prvs_i(data_width-2) & prvs_i; + end if; + else + if (t='0' and s='1') then + prvs_ext_r <= prvs_i; + prvs_ext_i <= prvs_r; + else + prvs_ext_r <= prvs_r; + prvs_ext_i <= prvs_i; + end if; + end if; +end process; + +process(add2_out, sub2_out, s, t) +begin + if (t='0' and s='1') then + swapadd<=sub2_out; + swapsub<=add2_out; + else + swapadd<=add2_out; + swapsub<=sub2_out; + end if; +end process; +end;
vhdl/WISHBONE_FFT/BF2II.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/shiftreg1.vhd =================================================================== --- vhdl/WISHBONE_FFT/shiftreg1.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/shiftreg1.vhd (revision 5) @@ -0,0 +1,55 @@ + +-- hds header_start +--1 stage shift register, data_width bits wide. + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + + +ENTITY shiftreg1 IS + GENERIC( + data_width : integer := 25 + ); + PORT( + clock : IN std_logic; + enable : in std_logic; + clear : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); + +-- Declarations + +END shiftreg1 ; + +-- hds interface_end +ARCHITECTURE behavior OF shiftreg1 IS +--signal reg00 : std_logic_vector(data_width-1 downto 0); +BEGIN +process(Clock,resetn) +begin +if (resetn='0') then +-- for i in data_width-1 downto 0 loop +-- r eg00(i)<='0'; + read_data <= (others => '0'); +-- end loop; + elsif (Clock'event and Clock='1') then + + if (enable='1') then + + if(clear ='1') then +-- reg00<=write_data; +-- read _data<=reg00; + read_data <= (others => '0'); + + else + read_data <= write_data; + + + end if; + end if; + end if; +end process; +END behavior;
vhdl/WISHBONE_FFT/shiftreg1.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/fft_core_pipeline1.vhd =================================================================== --- vhdl/WISHBONE_FFT/fft_core_pipeline1.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/fft_core_pipeline1.vhd (revision 5) @@ -0,0 +1,547 @@ +-- N point FFT +-- Uses R2^2SDF algorithm +-- +-- Generics used: +-- N - number of points taken - powers of 2 only, ranging f 8 to 1024 points. +-- input_ width - bit width of the input vector +-- twiddle width - width of the twiddle factors stored in the ROM +-- add_g - Adder growth - Adders grow 0 or 1 bits each time they are used +-- Exculdes adders in the complex multiplier (that is handled by mult_g) +-- mult_g - multiplier growth - 0 to twiddle_width+ 1 - Growth during the complex +-- multiplier stages +-- +-- Width of output vector is as follows (num_stages=log2(N): +-- N width +-- 8,16 input_width + (num_stages * add_g) + mult_g +-- 32,64 input_width + (num_ stages * add_g) + 2*mult_g +-- 128,256 input_width + (num_stage s * add_g) + 3*mult_g +-- 512,1024 input_width + (num_stages * add_g) + 4*mult_g +-- +-- Due to the way this system was made parameterizable, there are many signals +-- that will remain unconnected. This is normal. +-- +-- Default generics are for a simple 64 point FFT + +-- Each stage with complex multiplier introduces a 1/2 gain + +--Changes made by Alex-Parrado to the original version of Adam Robert Miller + + --Pipeline registers and clock enables, have been added. Clock frequency above of 100 MHz for all FFT sizes + + --Synchronous ROMs for proper RAM block inferring. MATLAB scripts have been modified. + + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +USE ieee.numeric_std.ALL; +--USE ieee.std_logic_arith.ALL; +use ieee.math_real.all; +use work.fft_pkg .all; + +entity fft_core_pipeline1 is + generic ( + input_width : integer :=16; + twiddle_width : integer :=16; + N : integer :=1024; + add_g : integer:=0;--1; --Either 0 or 1 only. + mult_g : integer:=0--9 --Can be any number from 0 to twiddle_width+1 + ); + port ( clock : in std_logic; + resetn : in std_logic; + enable : in std_logic; + clear : in std_logic; + enable_out: out std_logic; + frame_ready: out std_logic; + index : out std_logic_vector(integer(ceil(log2(real((N)))))-1 downto 0); + xin_r : in std_logic_vector(input_width-1 downto 0); + xin_i : in std_logic_vector(input_width-1 downto 0); + Xout_r : out std_logic_vector (input_width+((integer(ceil(log2(real((N)))))-1)/2)*mult_g+integer(ceil(log2(real((N)))))*add_g-1 downto 0); + Xout_i : out std_logic_vector (input_width+((integer(ceil(log2(real((N)))))-1)/2)*mult_g+integer(ceil(log2(real((N)))))*add_g-1 downto 0) + ); +end fft_core_pipeline1; + +architecture structure of fft_core_pipeline1 is +--Signal declarations +constant num_stages: integer :=integer(ceil(log2(real((N))))); +signal control: std_logic_vector(num_stages-1 downto 0); +signal bit_reverse_index: std_logic_vector(num_stages-1 downto 0); +type stage_array is array (1 to num_stages-1) of + std_logic_vector(input_width+(num_stages*add_g)+(((num_stages-1)/2)*mult_g)-1 downto 0); +signal stoscon_r: stage_array; +signal stoscon_i: stage_array; +type rom_array is array (1 to (num_stages-1)/2) of std_logic_vector(twiddle_width-1 downto 0); +signal rtoscon_r: rom_array; +signal rtoscon_i: rom_array; + +type enables_array is array (0 to num_stages+1) of std_logic_vector(0 downto 0); +signal enables: enables_array; + + +type counter_registers_array is array (0 to num_stages+1) of std_logic_vector(num_stages-1 downto 0); +signal counter_registers: counter_registers_array; + +-- + +signal xin_r_reg : std_logic_vector(input_width-1 downto 0); +signal xin_i_reg : std_logic_vector(input_width-1 downto 0); + +signal t_ff: std_logic_vector(0 downto 0); +signal en_t_ff:std_logic_vector(0 downto 0); +signal clear_t_ff:std_logic; + + +--component declarations +component counterhle + generic (width : integer); + + port ( clock : in std_logic; + resetn : in std_logic; + enable : in std_logic; + clear : in std_logic; + countout : out std_logic_vector(width-1 downto 0) + ); +end component; + +component rom1 + generic ( + data_width : integer; + address_width : integer); + port ( + clk: in std_logic; + address: IN std_logic_vector (address_width-1 DOWNTO 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0); + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end component; + +component rom2 + generic ( + data_width : integer; + address_width : integer); + port ( + clk: in std_logic; + address : IN std_logic_vector (address_width-1 DOWNTO 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0); + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end component; + +component rom3 + generic ( + data_width : integer; + address_width : integer); + port ( + clk: in std_logic; + address : IN std_logic_vector (address_width-1 DOWNTO 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0); + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end component; + +component rom4 + generic ( + data_width : integer; + address_width : integer); + port ( + clk: in std_logic; + address : IN std_logic_vector (address_width-1 DOWNTO 0); + datar : OUT std_logic_vector (data_width-1 DOWNTO 0); + datai : OUT std_logic_vector (data_width-1 DOWNTO 0) + ); +end component; + +component stage_I + generic ( + data_width : INTEGER; + add_g : INTEGER; + shift_stages : INTEGER); + port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + s :in std_logic; + clock : in std_logic; + enable: in std_logic; + resetn : in std_logic; + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0)); +end component; + +component stage_II + generic ( + data_width : INTEGER; + add_g : INTEGER; + mult_g : INTEGER; + twiddle_width : INTEGER; + shift_stages : INTEGER + ); + port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0) ; + t :in std_logic; + s :in std_logic; + clock : in std_logic; + enable: in std_logic; + resetn : in std_logic; + fromrom_r :in std_logic_vector (twiddle_width-1 downto 0) ; + fromrom_i :in std_logic_vector(twiddle_width-1 downto 0); + tonext_r :out std_logic_vector(data_width+mult_g-1 downto 0); + tonext_i :out std_logic_vector(data_width+mult_g-1 downto 0)); +end component; + +component stage_I_last + generic ( + data_width : INTEGER; + add_g : INTEGER + ); + port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + s :in std_logic; clock : in std_logic; resetn : in std_logic; + enable: in std_logic; + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0)); +end component; + +component stage_II_last + generic ( + data_width : INTEGER; + add_g : INTEGER + ); + port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + t :in std_logic; + s :in std_logic; + clock : in std_logic; + enable: in std_logic; + resetn : in std_logic; + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0)); +end component; + +component shiftreg1 + generic ( + data_width : integer +); + port ( + clock : IN std_logic; + enable: in std_logic; + clear: in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); +end component; + +begin + +controller : component counterhle + generic map ( + width=>num_stages +) + port map ( + clock=>clock, + resetn=>resetn, + clear => clear, + enable=>enable, + countout=>control + ); + + +-- Counter, pipeline registers +counter_registers(0)<=control; +forcounterregs: for i in 0 to num_stages generate +counterregi: shiftreg1 +generic map( + data_width=>num_stages +) + port map ( + clock=>clock, + enable=>'1', + clear => clear, + read_data=>counter_registers(i+1), + write_data=>counter_registers(i), + resetn=>resetn + ); + +end generate; + + +--Enable, pipeline registers +enables(0)(0)<=enable; +forenablesregs: for i in 0 to num_stages generate +enableregi: shiftreg1 +generic map( + data_width=>1 +) + port map ( + clock=>clock, + enable=>'1', + clear => clear, + read_data=>enables(i+1), + write_data=>enables(i), + resetn=>resetn + ); + +end generate; + + + +--Input registers +reginputr: shiftreg1 +generic map( + data_width=>input_width +) + port map ( + clock=>clock, + enable=>'1', + clear => '0', + read_data=>xin_r_reg, + write_data=>xin_r, + resetn=>resetn + ); + +reginputi: shiftreg1 +generic map( + data_width=>input_width +) + port map ( + clock=>clock, + enable=>'1', + clear => '0', + read_data=>xin_i_reg, + write_data=>xin_i, + resetn=>resetn + ); + + +stages : for i in 1 to num_stages generate +-- constan ity : in r :=i rem 2; t par tege +-- constant shift_stages : integer := 2**(num_stages - i); +-- consta nt rom_loc : integer :=i/2; +-- constant data_width : integer :=input_width + (i*add_g) + (((i-1)/2)*mult_g); +-- constant s: integer : =(num_stages-i); +-- constant t : integer :=(num_stages-i+1); + initial_stage: if i=1 generate + initial_stage_I : component stage_I + generic map ( + data_width=>input_width + (i*add_g)+(((i-1)/2)*mult_g), + add_g=>add_g, + shift_stages=>2**(num_stages - i)) + port map ( + prvs_r=>xin_r_reg,prvs_i=>xin_i_reg,s=>counter_registers(i)((num_stages-i)), + clock=>clock, + enable=>enables(i)(0), + resetn=>resetn, + tonext_r=>stoscon_r(i)(input_width+(i*add_g) + (( (i-1)/2)*mult_g)-1 downto 0), + tonext_i=>stoscon_i(i)(input_width+ (i*add_g) + (( (i-1)/2)*mult_g)-1 downto 0)); + end generate initial_stage; + + even_stages: if ((i rem 2)=0) and (i/=num_stages) generate + inner_stage_II : component stage_II + generic map ( + data_width=>input_width + (i*add_g) + (((i-1)/2)*mult_g), + add_g=>add_g,mult_g=>mult_g, + twiddle_width=>twiddle_width, + shift_stages=>2**(num_stages - i) + ) + port map ( + prvs_r=>stoscon_r(i-1)(input_width + (i*add_g) + (((i -1)/2)*mult_g)-1-add_g downto 0), + prvs_i=>stoscon_i(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + t=>counter_registers(i)((num_stages-i+1)), + s=>counter_registers(i)((num_stages-i)),clock=>clock,resetn=>resetn, + enable=>enables(i)(0), + fromrom_r=>rtoscon_r(i/2),fromrom_i=>rtoscon_i(i/2), + tonext_r=>stoscon_r(i)(input_width + (i*add_g) + (((i-1)/2)*mult_g)+mult_g-1 downto 0), + tonext_i=>stoscon_i(i)(input_width + (i*add_g) + (((i-1)/2)*mult_g)+mult_g-1 downto 0) + ); + + first_rom: if (i/2)=1 generate + rom_1 : component rom1 + + generic map ( + data_width=>twiddle_width, + address_width=>(num_stages-i+1)+1 + ) + port map ( + clk=>clock, + address=>counter_registers(i-1)((num_stages-i+1) downto 0 ), + datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2)); + end generate first_rom; + + second_rom: if (i/2)=2 generate + rom_2 : component rom2 + generic map ( + data_width=>twiddle_width, + address_width=>(num_stages-i+1)+1 + ) + port map ( + clk=>clock, + address=>counter_registers(i-1)((num_stages-i+1 ) downto 0), + datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2) + ); + end generate second_rom; + + third_rom: if (i/2)=3 generate + rom_3 : component rom3 + generic map ( + + data_width =>twiddle_width, + address_width=>(num_stages-i+1)+1 + ) + port map ( + clk=>clock, + address=>counter_registers(i-1)((num_stages-i+1) downto 0), + datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2) + ); + end generate third_rom; + + fourth_rom: if (i/2)=4 generate + rom_4 : component rom4 + generic map ( + data_width=>twiddle_width, + address_width=>(num_stages-i+1)+1 + ) + port map ( + clk=>clock, + address=>counter_registers(i-1)((num_stages-i+1) downto 0), + datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2) + ); + end generate fourth_rom; + + end generate even_stages; + + + + odd_stages: if (((i rem 2)=1) and (i/=num_stages)) and (i/=1) + generate + inner_stage_I : component stage_I + generic map ( + data_width=>input_width + (i*add_g) + (((i-1)/2)*mult_g), + add_g=>add_g, + shift_stages=>2**(num_stages - i) + ) + port map ( + prvs_r=>stoscon_r(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + prvs_i=>stoscon_i(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + s=>counter_registers(i)( (num_stages-i)), + enable=>enables(i)(0), + clock=>clock, + resetn=>resetn, + tonext_r=>stoscon_r(i)(input_width+ (i*add_g) + ( ((i -1)/2)*mult_g)-1 downto 0), + tonext_i=>stoscon_i(i)(input_width + (i*add_g) + ( ((i- 1)/2)*mult_g)-1 downto 0) + ); + end generate odd_stages; + + end_on_even: if (i=num_stages) and ((i rem 2)=0) generate + last_stage_II : component stage_II_last + generic map ( + data_width=>input_width + (i*add_g) + (((i-1)/2)*mult_g), + add_g=>add_g + ) + port map ( + prvs_r=>stoscon_r(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + prvs_i=>stoscon_i(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + t=>counter_registers(i)((num_stages-i+1)), + s=>counter_registers(i)((num_stages-i)),clock=>clock , + resetn=>resetn, + enable=>enables(i)(0), + tonext_r=>Xout_r, + tonext_i=>Xout_i + ); + end generate end_on_even; + + end_on_odd: if (i=num_stages) and ((i rem 2)=1) generate + last_stage_I : component stage_I_last + generic map ( + data_width=>input_width + (i*add_g) + (((i-1)/2)*mult_g), add_g=>add_g + ) + port map ( + prvs_r=>stoscon_r(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + prvs_i=>stoscon_i(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), + s=>counter_registers(i)( (num_stages-i)), + clock=>clock, + enable=>enables(i)(0), + resetn=>resetn, + tonext_r=>Xout_r, + tonext_i=>Xout_i + ); + + + end generate end_on_odd; + +end generate stages; + +--Frequency bin with bit reversal +bit_reverse_index<=std_logic_vector(unsigned(counter_registers(num_stages+1))+1); + +bit_reverse: for i in 0 to num_stages-1 generate + index(i)<=bit_reverse_index(num_stages-1-i); + +end generate; + + +--T flip-flop for enable_out generation control + +tff: shiftreg1 generic map( + data_width=>1 +) + port map ( + clock=>clock, + enable=>((en_t_ff(0) or clear_t_Ff) and enables(num_stages)(0)) or clear, + clear => clear or clear_t_ff, + read_data=>t_ff, + write_data=>en_t_ff, + resetn=>resetn + ); + + + +en_t_ff(0)<= '1' when (unsigned(counter_registers(num_stages+1))=(N-1)) else '0'; +clear_t_ff <= '1' when (unsigned(counter_registers(num_stages+1))=(N-1) and t_ff(0)='1') else '0'; + +--Enable out includes pipeline latency +enable_out<=enables(num_stages+1)(0) when (t_ff="1") else '0' ; + + +--Frame ready, falling edge detector + +process(resetn,clock) + variable detect : std_ulogic_vector (1 downto 0); + begin + if resetn ='0' then + detect := "00"; + + elsif rising_edge(clock) then + + if (clear ='1') then + + frame_ready<='0'; + + else + + detect(1) := detect(0); -- record last value of sync in detect(1) + detect(0) := t_ff(0) ; --record current sync in detect(0) + + if detect = "01" then -- rising_edge + + frame_ready<='0'; + + elsif detect = "10" then --falling_edge + +frame_ready<='1'; + + + end if; + + end if; + + end if; +end process; + + + + +end;
vhdl/WISHBONE_FFT/fft_core_pipeline1.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/twiddle_mult.vhd =================================================================== --- vhdl/WISHBONE_FFT/twiddle_mult.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/twiddle_mult.vhd (revision 5) @@ -0,0 +1,67 @@ + +--Twiddle multiplier +--7/17/02 +--Uses a both inputs same width complex multiplier +--Won't sign extend output, but will truncate it down +--(mult_width + twiddle_width >= output_width) +-- +--Twiddle factors are limited to -1 < twdl < 1. +--(twiddle factor can't be 0b1000000000) + +library IEEE; +use IEEE.std_logic_1164.all; + +entity twiddle_mult is + +generic ( + mult_width : INTEGER := 7; + twiddle_width : INTEGER :=3; + output_width : INTEGER :=9 + ); + +port ( data_r :in std_logic_vector(mult_width-1 downto 0); + data_i :in std_logic_vector(mult_width-1 downto 0); + twdl_r :in std_logic_vector(twiddle_width-1 downto 0); + twdl_i :in std_logic_vector(twiddle_width-1 downto 0); + out_r :out std_logic_vector(output_width-1 downto 0); + + out_i :out std_logic_vector(output_width-1 downto 0) + ); + +end twiddle_mult; + +architecture behavior of twiddle_mult is +signal mult_out_r : std_logic_vector(twiddle_width + mult_width downto 0); +signal mult_out_i : std_logic_vector(twiddle_width + mult_width downto 0); + +component comp_mult + generic ( inst_width1:integer; + inst_width2:integer ); + port ( Re1 : in std_logic_vector(inst_width1-1 downto 0); + Im1 : in std_logic_vector(inst_width1-1 downto 0); + Re2 : in std_logic_vector(inst_width2-1 downto 0); + Im2 : in std_logic_vector(inst_width2-1 downto 0); + Re : out std_logic_vector(inst_width1 + inst_width2 +downto 0); + Im : out std_logic_vector(inst_width1 + inst_width2 +downto 0) + + ) ; + +end component; + +begin + + U1 : comp_mult + generic map( + inst_width1 => mult_width, inst_width2 => twiddle_width) + port map (Re1=>data_r, Im1=>data_i, Re2=>twdl_r, Im2=>twdl_i, +Re=>mult_out_r, Im=>mult_out_i); + + process(mult_out_r,mult_out_i) + begin + out_r <= mult_out_r((twiddle_width+mult_width-1) downto (twiddle_width+mult_width-output_width)); + out_i <= mult_out_i((twiddle_width+mult_width-1) downto (twiddle_width+mult_width-output_width)); + + end process; +end;
vhdl/WISHBONE_FFT/twiddle_mult.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FFT/stage_I_last.vhd =================================================================== --- vhdl/WISHBONE_FFT/stage_I_last.vhd (nonexistent) +++ vhdl/WISHBONE_FFT/stage_I_last.vhd (revision 5) @@ -0,0 +1,141 @@ +--Component for Stages using BF2I (if BF2I is the last stage) +--Input is a standard logic vector of data_width-add_g +--data_width - width of the internal busses +--add_g - Add growth variable - if 1, data_width grows by 1, if 0 then 0 +--Only 1 shift stage + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity stage_I_last is +generic ( + data_width : INTEGER :=13; + add_g : INTEGER := 1 + ); +port ( + prvs_r :in std_logic_vector(data_width-1-add_g downto 0); + prvs_i :in std_logic_vector(data_width-1-add_g downto 0); + s :in std_logic; + clock : in std_logic; + enable : in std_logic; + resetn : in std_logic; + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector(data_width-1 downto 0) + ); +end stage_I_last; + +architecture structure of stage_I_last is +signal toreg_r : std_logic_vector(data_width-1 downto 0); +signal toreg_i : std_logic_vector(data_width-1 downto 0); +signal fromreg_r : std_logic_vector(data_width-1 downto 0); +signal fromreg_i: std_logic_vector(data_width -1 downto 0); + +signal tonext_r_aux : std_logic_vector(data_width-1 downto 0); +signal tonext_i_aux : std_logic_vector(data_width-1 downto 0); + +component shiftreg1 + generic ( + data_width : integer +); + port ( + clock : IN std_logic; + enable : in std_logic; + clear : in std_logic; + read_data : OUT std_logic_vector (data_width-1 DOWNTO 0); + write_data : IN std_logic_vector (data_width-1 DOWNTO 0); + resetn : IN std_logic + ); +end component; + +component BF2I + generic ( + data_width : INTEGER; + add_g: INTEGER +); + port ( + fromreg_r :in std_logic_vector(data_width-1 downto 0); + fromreg_i :in std_logic_vector(data_width -1 downto 0); + prvs_r :in std_logic_vector(data_width-add_g-1 downto 0) ; + prvs_i :in std_logic_vector(data_width-add_g-1 downto 0) ; + s : in std_logic; + toreg_r :out std_logic_vector(data_width-1 downto 0); + toreg_i :out std_logic_vector(data_width-1 downto 0); + tonext_r :out std_logic_vector(data_width-1 downto 0); + tonext_i :out std_logic_vector( data_width-1 downto 0) + ); +end component; + +begin +regr : shiftreg1 + generic map ( + data_width=>data_width + ) + port map ( + clock=>clock, + enable=>enable, + clear =>'0', + read_data=>fromreg_r, + write_data=>toreg_r, + resetn=>resetn + ); +regi : shiftreg1 + generic map ( + data_width=>data_width + ) + port map ( + clock=>clock, + enable=>enable, + clear =>'0', + read_data=>fromreg_i, + write_data=>toreg_i, + resetn=>resetn + ); +btrfly : BF2I + generic map ( + data_width=>data_width, + add_g=>add_g + ) + port map ( + fromreg_r=>fromreg_r, + fromreg_i=>fromreg_i, + prvs_r=>prvs_r, + prvs_i=>prvs_i, + s=>s, + toreg_r=>toreg_r, toreg_i=>toreg_i, + tonext_r=>tonext_r_aux, + tonext_i=>tonext_i_aux +); + + + +regsegr : shiftreg1 + generic map ( + data_width=>data_width + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_r, + write_data=>tonext_r_aux, + resetn=>resetn + ); + +regsegi : shiftreg1 + generic map ( + data_width=>data_width + + ) +port map ( + clock=>clock, + enable=>'1', + clear=>'0', + read_data=>tonext_i, + write_data=>tonext_i_aux, + resetn=>resetn + ); + + +end;
vhdl/WISHBONE_FFT/stage_I_last.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/WISHBONE_FIR/.vhd =================================================================== --- vhdl/WISHBONE_FIR/.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/.vhd (revision 5) @@ -0,0 +1,23 @@ +library ieee; +use ieee.math_real.all; + +package coeff_pkg is + constant Nb : integer := 16; + constant Nh : integer := 255; + constant Q : integer := 15; + +-- type coeff is array (Nh-1 downto 0) of integer range -(2**(Nb-1)) to (2**(Nb-1)-1); +-- constant h0 : coeff := ( +-- -89, +-- 971, +-- 860, +-- -8051, +-- -985, +-- 14393, +-- -985, +-- -8051, +-- 860, +-- 971, +-- -89 +-- ); +end coeff_pkg; Index: vhdl/WISHBONE_FIR/cell.vhd =================================================================== --- vhdl/WISHBONE_FIR/cell.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/cell.vhd (revision 5) @@ -0,0 +1,132 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +--The cell mult and sum +entity cell is +generic (WordWidth:integer:=24;--width signal of in/out + M:integer:=16;--width word of coefs + WordWidth_Q:integer:=4--width signal of Q + ); + +port( + +signal_input :in std_logic_vector(WordWidth-1 downto 0); +filter_coef: in std_logic_vector(M-1 downto 0); +reg_input:in std_logic_vector(WordWidth-1 downto 0); +signal_output:out std_logic_vector(WordWidth-1 downto 0); +clk,reset,clear,enable:in std_logic; +Q :in std_logic_vector(WordWidth_Q-1 downto 0) + +); +end entity; + +architecture RTL of cell is +--The fullregister component +component fullregister is + + generic + ( + N: integer + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + clear : in std_logic; + d : in std_logic_vector(N-1 downto 0); + q : out std_logic_vector(N-1 downto 0) + + ); +end component; + +component Barrel_Shifter is + +generic ( + + WordWidth_in:integer;--width signal of in + WordWidth_out:integer;--width signal of out + WordWidth_Q:integer--width signal of Q +); +port( +signal_input :in std_logic_vector(WordWidth_in-1 downto 0); +signal_out :out std_logic_vector(WordWidth_out-1 downto 0); +Q :in std_logic_vector(WordWidth_Q-1 downto 0) +); +end component; + +component Barrel_Shifter_left is + +generic ( + + WordWidth_in:integer;--width signal of in + WordWidth_out:integer;--width signal of out + WordWidth_Q:integer--width signal of Q +); +port( +signal_input :in std_logic_vector(WordWidth_in-1 downto 0); +signal_out :out std_logic_vector(WordWidth_out-1 downto 0); +Q :in std_logic_vector(WordWidth_Q-1 downto 0) +); +end component; + +signal signal_output_aux: std_logic_vector(WordWidth-1 downto 0); +signal sum_mult: std_logic_vector(M+WordWidth-1 downto 0); +signal reg_input_aux,reg_output_aux:std_logic_vector(M+WordWidth-1 downto 0); +--signal sext:std_logic_vector(WordWidth-Q downto 0); +begin + +--reg_input_aux(Q-1 downto 0)<= (others =>'0'); +--sext<=(others=>reg_input(WordWidth-1)); +--reg_input_aux(2*wordwidth downto Q)<=sext & reg_input; + +Barrel_Shifter2:Barrel_Shifter_left + +generic map( + + WordWidth_in=>WordWidth, + WordWidth_out=>WordWidth+M, + WordWidth_Q=>WordWidth_Q +) +port map( +signal_input=>reg_input, +signal_out=>reg_input_aux, +Q=>Q +); + + + +sum_mult<=std_logic_vector((signed(filter_coef)*signed(signal_input)) + signed(reg_input_aux)); + +mycell:fullregister +generic map( + N=>M+WordWidth +) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enable, + clear=>clear, + d=>sum_mult, + q=>reg_output_aux + ); + +Barrel_Shifter1:Barrel_Shifter + +generic map( + + WordWidth_in=>WordWidth+M, + WordWidth_out=>WordWidth, + WordWidth_Q=>WordWidth_Q +) +port map( +signal_input=>reg_output_aux, +signal_out=>signal_output_aux, +Q=>Q +); + + +signal_output<=signal_output_aux; + +end architecture; \ No newline at end of file Index: vhdl/WISHBONE_FIR/Barrel_Shifter_left.vhd =================================================================== --- vhdl/WISHBONE_FIR/Barrel_Shifter_left.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/Barrel_Shifter_left.vhd (revision 5) @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Barrel_Shifter_left is + +generic ( + + WordWidth_in:integer:=20;--width signal of in + WordWidth_out:integer:=32;--width signal of out + WordWidth_Q:integer:=4--width signal of Q +); +port( +signal_input :in std_logic_vector(WordWidth_in-1 downto 0); +signal_out :out std_logic_vector(WordWidth_out-1 downto 0); +Q :in std_logic_vector(WordWidth_Q-1 downto 0) +); +end entity; + +architecture RTL of Barrel_Shifter_left is +signal signal_aux: std_logic_vector(WordWidth_out-1 downto 0); +signal signal_aux_input: std_logic_vector(WordWidth_out-1 downto 0); +signal sext: std_logic_vector(WordWidth_out-WordWidth_in-1 downto 0); +begin + +sext<= (others=>signal_input(WordWidth_in-1)); +signal_aux_input<= sext & signal_input; + +--signal_aux<=std_logic_vector(signed(signal_input)*to_signed(2**(to_integer(-signed(Q))),24)); +signal_aux<=to_stdlogicvector(to_bitvector(signal_aux_input) sll to_integer(unsigned(Q))); +--signal_aux<=std_logic_vector(signed(signal_input) ror (to_integer(unsigned(Q)))); +signal_out<=signal_aux; +end architecture; \ No newline at end of file Index: vhdl/WISHBONE_FIR/FILTER_FIR.vhd =================================================================== --- vhdl/WISHBONE_FIR/FILTER_FIR.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/FILTER_FIR.vhd (revision 5) @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--use work.coeff_pkg.all; + +entity FILTER_FIR is +generic (WordWidth:integer;--width signal of in/out + N_coef:integer;--coefs + M:integer;--width word of coefs + WordWidth_Q:integer;--width signal of Q + bit_growth:integer:=8 + ); + +port( +signal_input: in std_logic_vector(WordWidth-1 downto 0); +signal_output:out std_logic_vector(WordWidth+bit_growth-1 downto 0); +filter_coef: in std_logic_vector(M*N_coef-1 downto 0); +enable,clear,reset,clk: in std_logic; +Q :in std_logic_vector(WordWidth_Q-1 downto 0) + +); +end entity; + +architecture RTL of FILTER_FIR is + +--The cell mult and sum +component cell is +generic (WordWidth:integer;--width signal of in/out + M:integer;--width word of coefs + WordWidth_Q:integer--width signal of Q + + ); + +port( + +signal_input :in std_logic_vector(WordWidth-1 downto 0); +filter_coef: in std_logic_vector(M-1 downto 0); +reg_input:in std_logic_vector(WordWidth-1 downto 0); +signal_output:out std_logic_vector(WordWidth-1 downto 0); +clk,reset,clear,enable:in std_logic; +Q :in std_logic_vector(WordWidth_Q-1 downto 0) + +); +end component; + +type array_aux is array(N_coef downto 0) of std_logic_vector(WordWidth+bit_growth-1 downto 0); +signal cell_aux: array_aux; +signal sext:std_logic_vector(bit_growth-1 downto 0); +begin +sext<=(others=>signal_input(WordWidth-1)); +myfilter: + for k in N_coef-1 downto 0 generate +filter:cell + generic map( + WordWidth=>WordWidth+bit_growth, + M=>M, + WordWidth_Q=>WordWidth_Q + + ) + + port map( + signal_input=>sext&signal_input, + signal_output=>cell_aux(k), + filter_coef=>filter_coef((k+1)*M-1 downto k*M), + reg_input=>cell_aux(k+1), + enable=>enable, + clk=>clk, + reset=>reset, + clear=>clear, + Q=>Q + + ); + signal_output<=cell_aux(0)(WordWidth+bit_growth-1 downto 0); + end generate; + +end architecture; Index: vhdl/WISHBONE_FIR/fullregister.vhd =================================================================== --- vhdl/WISHBONE_FIR/fullregister.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/fullregister.vhd (revision 5) @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity fullregister is + + generic + ( + N: integer + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + clear : in std_logic; + d : in std_logic_vector(N-1 downto 0); + q : out std_logic_vector(N-1 downto 0) + + ); + +end entity; + +architecture rtl of fullregister is +begin + + process (clk,reset_n,d,clear,enable) + + begin + if reset_n = '0' then + q <= (others=>'0'); + elsif (rising_edge(clk)) then + + if enable = '1' then + if clear='1' then + + q <= (others=>'0'); + + else + + q<=d; + + end if; + + + end if; + + end if; + + + end process; + +end rtl; \ No newline at end of file Index: vhdl/WISHBONE_FIR/FIR_WB.vhd =================================================================== --- vhdl/WISHBONE_FIR/FIR_WB.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/FIR_WB.vhd (revision 5) @@ -0,0 +1,154 @@ +library ieee; +library work; +--use work.coeff_pkg.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity FIR_WB is +generic (Filter_Width:integer:=16;--Filter width signals of in/out + WB_Width:integer:=32;--WishBone width signal of in/out + N_coef:integer:=50;--coefs + M:integer:=16;--width word of coefs + WordWidth_Q:integer:=4;--width signal of Q + bit_growth:integer:=8; + adress_wordwidth:integer:=32 ; + Adr_bas:integer:=8; + reg_control:integer:=4; + reg_data:integer:=8; + reg_status:integer:=12; + reg_Q:integer:=16; + reg_coef:integer:=20 + + ); + +port( +DAT_I: in std_logic_vector(WB_Width-1 downto 0); +DAT_O:out std_logic_vector(WB_Width-1 downto 0); +ADR_I :in std_logic_vector(adress_wordwidth-1 downto 0); +STB_I,RST_I,CLK_I,WE_I,clear: in std_logic; +ACK_O: out std_logic +); +end entity; + + +architecture RTL of FIR_WB is + +component FILTER_FIR is +generic (WordWidth:integer;--width signal of in/out + N_coef:integer;--coefs + M:integer;--width word of coefs + WordWidth_Q:integer;--width signal of Q + bit_growth:integer + + + ); + +port( +signal_input: in std_logic_vector(WordWidth-1 downto 0); +signal_output:out std_logic_vector(WordWidth+bit_growth-1 downto 0); +filter_coef: in std_logic_vector(M*N_coef-1 downto 0); +enable,clear,reset,clk: in std_logic; +Q :in std_logic_vector(WordWidth_Q-1 downto 0) + +); +end component; + +component interface_slave_fir is +generic( + +data_wordwidth: integer; +adress_wordwidth: integer; +Adr_bas:integer; +reg_control:integer; +reg_data:integer; +reg_status:integer; +reg_Q:integer; +reg_coef:integer; +N_coef:integer; +M:integer; +WordWidth_Q:integer +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( adress_wordwidth-1 downto 0 ); + DAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + Start: out std_logic;--to SLAVE + h0: out std_logic_vector( (N_coef*M)-1 downto 0 ); + Q: out std_logic_vector( WordWidth_Q-1 downto 0 ); + clear,reset,clk: in std_logic + ); +end component; + +signal h0_aux:std_logic_vector(M*N_coef-1 downto 0); +signal fir_data_in:std_logic_vector(WB_Width-1 downto 0); +signal fir_data_out:std_logic_vector(Filter_Width+bit_growth-1 downto 0); +signal Q_aux:std_logic_vector(WordWidth_Q-1 downto 0); +signal Start_aux, WE_O_aux:std_logic; +signal sext:std_logic_vector(bit_growth-1 downto 0); +begin + +sext<=(others=>fir_data_out(Filter_Width+bit_growth-1)); + +myFilter:FILTER_FIR +generic map( + WordWidth=>Filter_Width, + N_coef=>N_coef, + M=>M, + WordWidth_Q=>WordWidth_Q, + bit_growth=>bit_growth +) + port map ( + signal_input=>fir_data_in(Filter_Width-1 downto 0), + signal_output=>fir_data_out, + filter_coef=>h0_aux, + enable=>Start_aux, + clear=>clear, + reset=>RST_I, + clk=>CLK_I, + Q=>Q_aux + ); + +wb_interface:interface_slave_fir +generic map( + +data_wordwidth=>WB_Width, +adress_wordwidth=>adress_wordwidth, +Adr_bas=>Adr_bas, +reg_control=>reg_control, +reg_data=>reg_data, +reg_status=>reg_status, +reg_Q=>reg_Q, +reg_coef=>reg_coef, +N_coef=>N_coef, +M=>M, +WordWidth_Q=>WordWidth_Q + +) +port map( + + + ACK_O=>ACK_O, + ADR_I=>ADR_I, + DAT_I=>DAT_I, + sDAT_I=>sext&fir_data_out, + DAT_O=>DAT_O, + sDAT_O=>fir_data_in, + STB_I=>STB_I, + WE_I=>WE_I, + Start=>Start_aux, + h0=>h0_aux, + Q=>Q_aux, + clear=>clear, + reset=>RST_I, + clk=>CLK_I + ); + +end architecture; \ No newline at end of file Index: vhdl/WISHBONE_FIR/interface_slave_fir.vhd =================================================================== --- vhdl/WISHBONE_FIR/interface_slave_fir.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/interface_slave_fir.vhd (revision 5) @@ -0,0 +1,193 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity interface_slave_fir is +generic( + +data_wordwidth: integer; +adress_wordwidth: integer; +Adr_bas:integer; +reg_control:integer; +reg_data:integer; +reg_status:integer; +reg_Q:integer; +reg_coef:integer; + +N_coef:integer; + +M:integer; +WordWidth_Q:integer--width signal of Q + +); +port( + + + ACK_O: out std_logic;--to MASTER + ADR_I: in std_logic_vector( adress_wordwidth-1 downto 0 ); + DAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER + sDAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE + DAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER + sDAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE + STB_I: in std_logic;--from MASTER + WE_I: in std_logic;--from MASTER + Start: out std_logic;--to SLAVE + h0: out std_logic_vector( (N_coef*M)-1 downto 0 );--to SLAVE + Q :out std_logic_vector(WordWidth_Q-1 downto 0); + clear,reset,clk: in std_logic + + ); +end entity; + +architecture RTL of interface_slave_fir is + +--The fullregister component +component fullregister is + + generic + ( + N: integer + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + clear : in std_logic; + d : in std_logic_vector(N-1 downto 0); + q : out std_logic_vector(N-1 downto 0) + + ); +end component; + +signal OUT_AUX,rSTATUS_O, ZERO: std_logic_vector( data_wordwidth-1 downto 0 ); +signal ZERO1: std_logic_vector( WordWidth_Q-1 downto 0 ); + +type array_aux is array(N_coef downto 0) of std_logic_vector(M-1 downto 0); +signal h0_aux:array_aux; + +type array_aux1 is array(N_coef downto 0) of std_logic; +signal enables:array_aux1; + +begin + ZERO<=std_logic_vector(to_unsigned(0,data_wordwidth)); + ZERO1<=std_logic_vector(to_unsigned(0,WordWidth_Q)); + OUT_AUX<=DAT_I; + ACK_O<=STB_I; + + + DAT_O<=sDAT_I; + + coefficients: + for k in N_coef-1 downto 0 generate + + enables(k)<='1' when (STB_I='1' and WE_I='1' and ADR_I(9 downto 0)=std_logic_vector(to_unsigned((4*k)+reg_coef,10))) else + '0'; + + coefs:fullregister + generic map( + N=>M + ) + port map ( + clk=>clk, + reset_n=>reset, + enable=>enables(k), + clear=>clear, + d=>OUT_AUX(M-1 downto 0), + q=>h0_aux(k) + ); + h0((k+1)*M-1 downto k*M)<=std_logic_vector(signed(h0_aux(k))); + + end generate; + + + + process(ADR_I,STB_I,WE_I,ZERO,ZERO1,OUT_AUX,sDAT_I,rSTATUS_O) + begin + + --if ((ADR_I(adress_wordwidth-1 downto adress_wordwidth-4))=std_logic_vector(to_unsigned(Adr_bas,4))) then + if (WE_I='1' and STB_I='1') then + case ADR_I(9 downto 0) is + + when std_logic_vector(to_unsigned(reg_control,10)) => start<='1'; + --sDAT_O<=ZERO; + --DAT_O<=ZERO; + rSTATUS_O<=ZERO; + --Q<=ZERO1; + + + when std_logic_vector(to_unsigned(Reg_status,10)) => rSTATUS_O<=std_logic_vector(unsigned(OUT_AUX)); + --sDAT_O<=ZERO; + -- DAT_O<=ZERO; + start<='0'; + --Q<=ZERO1; + + + when OTHERS => --DAT_O<=ZERO; + --sDAT_O<=ZERO; + start<='0'; + rSTATUS_O<=ZERO; + --Q<=ZERO1; + end case; +-- elsif (WE_I='0' and STB_I='1') then +-- case ADR_I(4 downto 0) is +-- when std_logic_vector(to_unsigned(reg_data,5)) => DAT_O<=sDAT_I; +-- --sDAT_O<=ZERO; +-- start<='0'; +-- rSTATUS_O<=ZERO; +-- ---Q<=ZERO1; +-- +-- when std_logic_vector(to_unsigned(Reg_status,5)) => DAT_O<=rSTATUS_O; +-- --sDAT_O<=ZERO; +-- start<='0'; +-- rSTATUS_O<=ZERO; +-- --Q<=ZERO1; +-- when OTHERS => DAT_O<=ZERO; +-- --sDAT_O<=ZERO; +-- start<='0'; +-- rSTATUS_O<=ZERO; +-- --Q<=ZERO1; +-- end case; + + --end if; + else + -- DAT_O<=ZERO; + --sDAT_O<=ZERO; + start<='0'; + rSTATUS_O<=ZERO; + --Q<=ZERO1; + end if; + + end process; + + process(ADR_I,STB_I,WE_I,ZERO,ZERO1,OUT_AUX,sDAT_I,rSTATUS_O) + begin + if rising_edge(clk) then + + if (WE_I='1' and STB_I='1') then + if ADR_I(9 downto 0)=std_logic_vector(to_unsigned(reg_data,10)) then + + + sDAT_O<=OUT_AUX; + end if; + if ADR_I(9 downto 0)=std_logic_vector(to_unsigned(reg_Q,10)) then + + + --Q<=OUT_AUX(data_wordwidth-1 downto data_wordwidth-WordWidth_Q); + Q<=OUT_AUX(WordWidth_Q-1 downto 0); + end if; + + + + + + end if; + end if; + + + end process; +end architecture; + + + \ No newline at end of file Index: vhdl/WISHBONE_FIR/.vhd.bak =================================================================== --- vhdl/WISHBONE_FIR/.vhd.bak (nonexistent) +++ vhdl/WISHBONE_FIR/.vhd.bak (revision 5) @@ -0,0 +1,23 @@ +library ieee; +use ieee.math_real.all; + +package coeff_pkg is + constant Nb : integer := 16; + constant Nh : integer := 11; + constant Q : integer := 15; + + type coeff is array (Nh-1 downto 0) of integer range -(2**(Nb-1)) to (2**(Nb-1)-1); + constant h0 : coeff := ( + -89, + 971, + 860, + -8051, + -985, + 14393, + -985, + -8051, + 860, + 971, + -89 + ); +end coeff_pkg; Index: vhdl/WISHBONE_FIR/.bak =================================================================== --- vhdl/WISHBONE_FIR/.bak (nonexistent) +++ vhdl/WISHBONE_FIR/.bak (revision 5) @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity slave is +generic( + +data_wordwidth: integer; +adress_wordwidth integer; + +); +port( + + ACK_O : out std_logic; + ADR_I : in std_logic_vector( adress_wordwidth downto 0 ); + CLK_I : in std_logic; + DAT_I : in std_logic_vector( data_wordwidth downto 0 ); + DAT_O : out std_logic_vector( data_wordwidth downto 0 ); + STB_I : in std_logic; + WE_I : in std_logic + + ); + + + \ No newline at end of file Index: vhdl/WISHBONE_FIR/Barrel_Shifter.vhd =================================================================== --- vhdl/WISHBONE_FIR/Barrel_Shifter.vhd (nonexistent) +++ vhdl/WISHBONE_FIR/Barrel_Shifter.vhd (revision 5) @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Barrel_Shifter is + +generic ( + + WordWidth_in:integer:=32;--width signal of in + WordWidth_out:integer:=20;--width signal of out + WordWidth_Q:integer:=4--width signal of Q +); +port( +signal_input :in std_logic_vector(WordWidth_in-1 downto 0); +signal_out :out std_logic_vector(WordWidth_out-1 downto 0); +Q :in std_logic_vector(WordWidth_Q-1 downto 0) +); +end entity; + +architecture RTL of Barrel_Shifter is +signal signal_aux: std_logic_vector(WordWidth_in-1 downto 0); +begin + +--signal_aux<=std_logic_vector(signed(signal_input)*to_signed(2**(to_integer(-signed(Q))),24)); +signal_aux<=to_stdlogicvector(to_bitvector(signal_input) sra to_integer(unsigned(Q))); +--signal_aux<=std_logic_vector(signed(signal_input) ror (to_integer(unsigned(Q)))); +signal_out<=signal_aux(WordWidth_out-1 downto 0); +end architecture; \ No newline at end of file

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