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/fm_hvc/fm_hvc_data.v
0,0 → 1,282
//=======================================================================
// Project Monophony
// Wire-Frame 3D Graphics Accelerator IP Core
//
// File:
// fm_hvc_data.v
//
// Abstract:
// LCD output color data construction
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
//
//======================================================================
//
// Copyright (c) 2015, Kenji Ishimaru
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// -Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// -Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
 
module fm_hvc_data (
clk_core,
clk_vi,
rst_x,
// sdram interface
i_rstr,
i_rd,
// timing input
i_h_active,
i_first_line,
i_hsync,
i_vsync,
o_fifo_available,
i_fifo_available_ack,
// configuration
i_video_start,
i_color_mode,
// test color input
i_test_r,
i_test_g,
i_test_b,
// color out
o_r,
o_g,
o_b,
o_a
);
 
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input clk_vi; // 25MHz
input rst_x;
// sdram interface
input i_rstr;
input [31:0] i_rd;
// timing input
input i_h_active;
input i_first_line;
input i_hsync;
input i_vsync;
output o_fifo_available;
input i_fifo_available_ack;
// configuration
input i_video_start;
input [1:0] i_color_mode;
// test color input
input [7:0] i_test_r;
input [7:0] i_test_g;
input [7:0] i_test_b;
 
output [7:0] o_r;
output [7:0] o_g;
output [7:0] o_b;
output [7:0] o_a;
//////////////////////////////////
// reg
//////////////////////////////////
reg [9:0] r_pix_cnt;
reg r_fifo_available;
 
reg [7:0] r_r;
reg [7:0] r_g;
reg [7:0] r_b;
 
reg [7:0] r_r_neg;
reg [7:0] r_g_neg;
reg [7:0] r_b_neg;
 
reg r_fifo_available_ack_1z;
reg r_fifo_available_ack_2z;
reg r_fifo_available_ack_3z;
 
//////////////////////////////////
// wire
//////////////////////////////////
wire w_rstr_base;
wire w_rstr_upper;
wire [15:0] w_di;
wire [31:0] w_do;
wire [31:0] w_do_normal;
wire [7:0] w_r_aa;
wire [7:0] w_g_aa;
wire [7:0] w_b_aa;
wire [7:0] w_r_f;
wire [7:0] w_g_f;
wire [7:0] w_b_f;
 
wire [7:0] w_r;
wire [7:0] w_g;
wire [7:0] w_b;
 
wire w_ren;
wire w_fifo_reset_x;
wire w_fifo_available_ack_rise;
wire w_pix_av_c0;
wire w_pix_av_c2;
wire w_pix_av_c3;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_fifo_available_ack_rise = r_fifo_available_ack_2z &
!r_fifo_available_ack_3z;
assign w_fifo_reset_x = i_vsync & rst_x;
assign w_rstr_base = i_rstr;
assign w_rstr_upper = i_rstr;
assign w_ren = i_h_active;
 
assign w_r_f = w_do_normal[31:24];
assign w_g_f = w_do_normal[23:16];
assign w_b_f = w_do_normal[15:8];
assign w_do_normal = f_get_color(w_di,i_color_mode);
 
assign w_b = (!i_video_start) ? i_test_b :
(i_h_active )? w_b_f :
8'h00;
assign w_g = (!i_video_start) ? i_test_g :
(i_h_active )? w_g_f :
8'h00;
assign w_r = (!i_video_start) ? i_test_r :
(i_h_active )? w_r_f :
8'h00;
assign o_b = r_b; //r_b_neg
assign o_g = r_g; // r_g_neg
assign o_r = r_r; // r_r_neg
 
assign o_fifo_available = r_fifo_available;
 
assign w_pix_av_c0 = ((i_color_mode == 'd0)&(r_pix_cnt == 'd63));
assign w_pix_av_c2 = ((i_color_mode == 'd2)&(r_pix_cnt == 'd127));
assign w_pix_av_c3 = ((i_color_mode == 'd3)&(r_pix_cnt == 'd255));
//////////////////////////////////
// always
//////////////////////////////////
 
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_pix_cnt <= 10'd0;
end else begin
if (~i_hsync) r_pix_cnt <= 10'd0;
else if (w_pix_av_c0|w_pix_av_c2|w_pix_av_c3)r_pix_cnt <= 10'd0;
else if (w_ren) r_pix_cnt <= r_pix_cnt + 1'b1;
end
end
 
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_fifo_available <= 1'b0;
end else begin
if (w_pix_av_c0|w_pix_av_c2|w_pix_av_c3) r_fifo_available <= 1'b1; // 32 x 2
else if (~i_hsync | w_fifo_available_ack_rise) r_fifo_available <= 1'b0;
end
end
 
 
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_fifo_available_ack_1z <= 1'b0;
r_fifo_available_ack_2z <= 1'b0;
r_fifo_available_ack_3z <= 1'b0;
end else begin
r_fifo_available_ack_1z <= i_fifo_available_ack;
r_fifo_available_ack_2z <= r_fifo_available_ack_1z;
r_fifo_available_ack_3z <= r_fifo_available_ack_2z;
end
end
 
always @(posedge clk_vi) begin
r_r <= w_r;
r_g <= w_g;
r_b <= w_b;
end
 
//////////////////////////////////
// function
//////////////////////////////////
function [31:0] f_get_color;
input [15:0] idata;
input [1:0] mode;
reg [7:0] r;
reg [7:0] g;
reg [7:0] b;
reg [7:0] a;
begin
case (mode)
2'b00 : begin
// color mode 5:6:5
r = {idata[15:11],idata[15:13]};
g = {idata[10:5],idata[10:9]};
b = {idata[4:0],idata[4:2]};
a = 8'h0;
end
2'b01 : begin
// color mode 5:5:5:1
r = {idata[15:11],idata[15:13]};
g = {idata[10:6],idata[10:8]};
b = {idata[5:1],idata[5:3]};
a = {idata[0],7'b0};
end
2'b10 : begin
// color mode 2:3:3
r = {'d4{idata[7:6]}};
g = {idata[5:3],idata[5:3],idata[5:4]};
b = {idata[2:0],idata[2:0],idata[2:1]};
a = 8'h0;
end
default : begin
// color mode 1:2:2
r = {'d8{idata[3]}};
g = {'d4{idata[2:1]}};
b = {'d8{idata[0]}};
a = 8'h0;
end
endcase
f_get_color = {r,g,b,a};
end
endfunction
 
 
//////////////////////////////////
// module instance
//////////////////////////////////
// 32bit x 128 entry fifo for current line
fm_afifo fm_afifo_c (
.clk_core(clk_core),
.clk_vi(clk_vi),
.rst_x(w_fifo_reset_x),
.i_color_mode(i_color_mode),
.i_wstrobe(w_rstr_base),
.i_dt(i_rd),
.o_full(),
.i_renable(w_ren),
.o_dt(w_di),
.o_empty(),
.o_dnum()
);
 
 
endmodule
fm_hvc/fm_hvc_data.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fm_hvc/fm_cmn_ram.v =================================================================== --- fm_hvc/fm_cmn_ram.v (nonexistent) +++ fm_hvc/fm_cmn_ram.v (revision 3) @@ -0,0 +1,149 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_cmn_ram.v +// +// Abstract: +// Dualport RAM, this will be mapped to block ram +// with different clocks +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History +//======================================================================= +// Project Polyphony +// +// File: +// fm_cmn_bram_02.v +// +// Abstract: +// Dualport RAM, this will be mapped onto block ram +// with different clocks +// Created: +// 5 November 2008 +//====================================================================== +// +// Copyright (c) 2013, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History +// $Date: 2014-12-09 16:38:37 +0900 (Tue, 09 Dec 2014) $ +// $Rev: 14 $ + +module fm_cmn_ram ( + clka, + clkb, + wea, + addra, + addrb, + dia, + doa, + dob + ); + +////////////////////////////////// +// parameter +////////////////////////////////// + parameter P_RAM_TYPE="TYPE_A"; + parameter P_WIDTH = 32; + parameter P_RANGE = 2; + parameter P_DEPTH = 1 << P_RANGE; +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clka; + input clkb; + input wea; + input [P_RANGE-1:0] addra; + input [P_RANGE-1:0] addrb; + input [P_WIDTH-1:0] dia; + output [P_WIDTH-1:0] doa; + output [P_WIDTH-1:0] dob; + +////////////////////////////////// +// reg +////////////////////////////////// + reg [P_WIDTH-1:0] ram [P_DEPTH-1:0]; + reg [P_WIDTH-1:0] doa; + reg [P_WIDTH-1:0] dob; + +////////////////////////////////// +// always +////////////////////////////////// +generate + if (P_RAM_TYPE=="TYPE_A") begin + always @(posedge clka) begin + if (wea) ram[addra] <= dia; + end + + always @(posedge clkb) begin + dob <= ram[addrb]; + end + end else begin + // port A: write-first + always @(posedge clka) begin + if (wea) begin + ram[addra] <= dia; + doa <= dia; + end else begin + doa <= ram[addra]; + end + end + + // port B: read-first + always @(posedge clkb) begin + dob <= ram[addrb]; + end + end +endgenerate +endmodule
fm_hvc/fm_cmn_ram.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fm_hvc/fm_hvc.v =================================================================== --- fm_hvc/fm_hvc.v (nonexistent) +++ fm_hvc/fm_hvc.v (revision 3) @@ -0,0 +1,207 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_hvc.v +// +// Abstract: +// VGA LCD Controller +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_hvc ( + clk_core, + clk_vi, + rst_x, + // configuration registers + i_video_start, + i_fb0_offset, + i_fb0_ms_offset, + i_fb1_offset, + i_fb1_ms_offset, + i_color_mode, + i_front_buffer, + i_aa_en, + i_fb_blend_en, + // status out + o_vint_x, + o_vint_edge, + // dram if + o_req, + o_adrs, + o_len, + i_ack, + i_rstr, + i_rd, + // video out + clk_vo, + o_r, + o_g, + o_b, + o_vsync_x, + o_hsync_x, + o_blank_x, + o_de +); + +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clk_core; + input clk_vi; // 25MHz + input rst_x; + // configuration registers + input i_video_start; + input [6:0] i_fb0_offset; + input [3:0] i_fb0_ms_offset; + input [6:0] i_fb1_offset; + input [3:0] i_fb1_ms_offset; + input [1:0] i_color_mode; + input i_front_buffer; + input [2:0] i_aa_en; + input i_fb_blend_en; + // status out + output o_vint_x; + output o_vint_edge; + // dram if + output o_req; + output [23:0] o_adrs; + output [5:0] o_len; + input i_ack; + input i_rstr; + input [31:0] i_rd; + + output clk_vo; + output [7:0] o_r; + output [7:0] o_g; + output [7:0] o_b; + output o_vsync_x; + output o_hsync_x; + output o_blank_x; + output o_de; + +////////////////////////////////// +// wire +////////////////////////////////// + wire [7:0] w_test_r; + wire [7:0] w_test_g; + wire [7:0] w_test_b; + + wire w_vsync_i; + wire w_hsync_i; + wire w_active; + wire w_first_line; + wire w_fifo_available; + wire w_fifo_available_ack; +////////////////////////////////// +// assign +////////////////////////////////// + assign clk_vo = clk_vi; +/////////////////////////// +// module instance +////////////////////////// + +fm_hvc_core fm_hvc_core ( + .clk_vi(clk_vi), + .rst_x(rst_x), + // configuration registers + .i_video_start(i_video_start), + // control out (only for internal use) + .o_vsync_i(w_vsync_i), + .o_hsync_i(w_hsync_i), + // video out timing + .o_active(w_active), + .o_first_line(w_first_line), + .o_r(w_test_r), + .o_g(w_test_g), + .o_b(w_test_b), + .o_vsync_x(o_vsync_x), + .o_hsync_x(o_hsync_x), + .o_blank_x(o_blank_x), + .o_de(o_de) +); + +fm_hvc_dma fm_hvc_dma ( + .clk_core(clk_core), + .rst_x(rst_x), + .i_color_mode(i_color_mode), + .i_video_start(i_video_start), + .i_vsync(w_vsync_i), + .i_hsync(w_hsync_i), + .i_fb0_offset(i_fb0_offset), + .i_fb0_ms_offset(i_fb0_ms_offset), + .i_fb1_offset(i_fb1_offset), + .i_fb1_ms_offset(i_fb1_ms_offset), + .i_front_buffer(i_front_buffer), + .i_aa_en(i_aa_en[0]), + .i_fifo_available(w_fifo_available), + .o_fifo_available_ack(w_fifo_available_ack), + .o_vsync(o_vint_x), + .o_vsync_edge(o_vint_edge), + // dram if + .o_req(o_req), + .o_adrs(o_adrs), + .o_len(o_len), + .i_ack(i_ack) +); + +fm_hvc_data fm_hvc_data ( + .clk_core(clk_core), + .clk_vi(clk_vi), + .rst_x(rst_x), + // sdram interface + .i_rstr(i_rstr), + .i_rd(i_rd), + // timing control + .i_h_active(w_active), + .i_first_line(w_first_line), + .i_hsync(w_hsync_i), + .i_vsync(w_vsync_i), + .o_fifo_available(w_fifo_available), + .i_fifo_available_ack(w_fifo_available_ack), + // configuration + .i_video_start(i_video_start), + .i_color_mode(i_color_mode), + // test color input + .i_test_r(w_test_r), + .i_test_g(w_test_g), + .i_test_b(w_test_b), + // color out + .o_r(o_r), + .o_g(o_g), + .o_b(o_b), + .o_a() +); + + +endmodule
fm_hvc/fm_hvc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fm_hvc/fm_hvc_dma.v =================================================================== --- fm_hvc/fm_hvc_dma.v (nonexistent) +++ fm_hvc/fm_hvc_dma.v (revision 3) @@ -0,0 +1,284 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_hvc_dma.v +// +// Abstract: +// VGA LCD Controller DMAC +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_hvc_dma ( + clk_core, + rst_x, + i_color_mode, + i_video_start, + i_vsync, + i_hsync, + i_fb0_offset, + i_fb0_ms_offset, + i_fb1_offset, + i_fb1_ms_offset, + i_front_buffer, + i_aa_en, + i_fifo_available, + o_fifo_available_ack, + o_vsync, + o_vsync_edge, + // dram if + o_req, + o_adrs, + o_len, + i_ack +); + +//////////////////////////// +// Parameter definition +//////////////////////////// + parameter P_IDLE = 3'd0; + parameter P_REQ = 3'd1; + parameter P_REQ_AA = 3'd2; + parameter P_WAIT_FIFO_AVL = 3'd3; + parameter P_WAIT_AVL_FALL = 3'd4; + + parameter P_BURST_SIZE = 6'd32; + parameter P_BURST_SIZE_H = 6'd16; +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clk_core; + input rst_x; + input [1:0] i_color_mode; + input i_video_start; + input i_vsync; + input i_hsync; + input [6:0] i_fb0_offset; + input [3:0] i_fb0_ms_offset; + input [6:0] i_fb1_offset; + input [3:0] i_fb1_ms_offset; + input i_front_buffer; + input i_aa_en; + input i_fifo_available; + output o_fifo_available_ack; + output o_vsync; + output o_vsync_edge; + // dram if + output o_req; + output [23:0] o_adrs; + output [5:0] o_len; // 32 burst x 10 + input i_ack; + +////////////////////////////////// +// reg +////////////////////////////////// + reg [2:0] r_state; + reg r_req; +// reg [13:0] r_cur_adrs_l; + reg [12:0] r_cur_adrs_l; + + reg [3:0] r_req_cnt; + // syncro register + reg r_vsync_1z; + reg r_vsync_2z; + reg r_vsync_3z; + + reg r_hsync_1z; + reg r_hsync_2z; + reg r_hsync_3z; + + reg r_fifo_available_1z; + reg r_fifo_available_2z; + reg r_fifo_available_3z; + reg r_fifo_available_ack; +////////////////////////////////// +// wire +////////////////////////////////// + wire w_set_initial_adrs; + wire w_v_rise; + wire w_h_start; + wire w_adrs_inc; + wire w_line_end; + wire w_req_cnt_clear; + + wire [6:0] w_fb_offset; + wire [6:0] w_fb_ms_offset; + wire [6:0] w_offset; + wire w_hburst; +////////////////////////////////// +// assign +////////////////////////////////// + assign o_req = r_req; + assign w_hburst = (i_color_mode == 2'd3)&(r_req_cnt == 4'd2); + assign o_len = (w_hburst) ? P_BURST_SIZE_H : P_BURST_SIZE; + assign o_fifo_available_ack = r_fifo_available_ack; + + assign w_set_initial_adrs = w_v_rise; + assign w_adrs_inc = (i_aa_en) ? (r_state == P_REQ_AA) & i_ack: + (r_state == P_REQ) & i_ack; + + assign w_h_start = i_video_start & r_hsync_2z & !r_hsync_3z; // rise of hsync + assign w_v_rise = r_vsync_2z & !r_vsync_3z; // rising edge of vsync + assign w_line_end = (i_color_mode == 2'd3) ? (r_req_cnt == 4'd3) :// 80 times: + (i_color_mode == 2'd2) ? (r_req_cnt == 4'd5) :// 160 times + (r_req_cnt == 4'd10); // 320 times + + assign w_req_cnt_clear = (w_line_end & !r_fifo_available_2z & + (r_state == P_WAIT_AVL_FALL)) | + (w_line_end & (r_state == P_WAIT_FIFO_AVL) & (i_color_mode == 'd3)); + +// assign o_adrs = {w_offset, r_cur_adrs_l,4'b0}; // w_offset[21:18] + assign o_adrs = {w_offset,r_cur_adrs_l,4'b0}; // w_offset[23:17] + + assign w_fb_offset = (i_front_buffer) ? i_fb1_offset : i_fb0_offset; + assign w_fb_ms_offset = (i_front_buffer) ? i_fb1_ms_offset : i_fb0_ms_offset; + assign w_offset = (r_state == P_REQ_AA) ? w_fb_ms_offset : w_fb_offset; + + assign o_vsync = r_vsync_2z; + assign o_vsync_edge = !r_vsync_2z & r_vsync_3z; // falling edge + +////////////////////////////////// +// always +////////////////////////////////// + // request state + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_state <= P_IDLE; + r_req <= 1'b0; + r_fifo_available_ack <= 1'b0; + end else begin + case (r_state) + P_IDLE: begin + if (w_h_start) begin + r_req <= 1'b1; + r_state <= P_REQ; + end + end + P_REQ: begin + if (i_ack) begin + if (i_aa_en) begin + r_req <= 1'b1; + r_state <= P_REQ_AA; + end else begin + r_req <= 1'b0; + r_state <= P_WAIT_FIFO_AVL; + end + end + end + P_REQ_AA: begin + if (i_ack) begin + r_req <= 1'b0; + r_state <= P_WAIT_FIFO_AVL; + end + end + P_WAIT_FIFO_AVL: begin + if (r_req_cnt < 4'd4) begin + if (w_line_end) begin + r_state <= P_IDLE; + end else begin + r_req <= 1'b1; + r_state <= P_REQ; + end + end else begin + if (r_fifo_available_2z) begin + r_fifo_available_ack <= 1'b1; + r_state <= P_WAIT_AVL_FALL; + end + end + end + P_WAIT_AVL_FALL: begin + if (!r_fifo_available_2z) begin + r_fifo_available_ack <= 1'b0; + if (w_line_end) begin + r_state <= P_IDLE; + end else begin + r_req <= 1'b1; + r_state <= P_REQ; + end + end + end + endcase + end + end + + // current address + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_cur_adrs_l <= 13'h0; // for simulation + end else begin + if (w_set_initial_adrs) begin + r_cur_adrs_l <= 13'h0; + end else if (w_adrs_inc) begin + if (w_hburst) + r_cur_adrs_l <= r_cur_adrs_l + 1'b1; // same as + 16 + else + r_cur_adrs_l <= r_cur_adrs_l + 2'b10; // same as + 32 + end + end + end + + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_req_cnt <= 4'd0; + end else begin + if (w_req_cnt_clear) r_req_cnt <= 4'd0; + else if (w_adrs_inc) r_req_cnt <= r_req_cnt + 1'b1; + end + end + + // syncro register + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_vsync_1z <= 1'b1; + r_vsync_2z <= 1'b1; + r_vsync_3z <= 1'b1; + r_hsync_1z <= 1'b1; + r_hsync_2z <= 1'b1; + r_hsync_3z <= 1'b1; + r_fifo_available_1z <= 1'b0; + r_fifo_available_2z <= 1'b0; + end else begin + r_vsync_1z <= i_vsync; + r_vsync_2z <= r_vsync_1z; + r_vsync_3z <= r_vsync_2z; + r_hsync_1z <= i_hsync; + r_hsync_2z <= r_hsync_1z; + r_hsync_3z <= r_hsync_2z; + r_fifo_available_1z <= i_fifo_available; + r_fifo_available_2z <= r_fifo_available_1z; + end + end + + + +endmodule
fm_hvc/fm_hvc_dma.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fm_hvc/fm_afifo.v =================================================================== --- fm_hvc/fm_afifo.v (nonexistent) +++ fm_hvc/fm_afifo.v (revision 3) @@ -0,0 +1,177 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_afifo.v +// +// Abstract: +// Asynchronus FIFO +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_afifo ( + clk_core, + clk_vi, + rst_x, + i_color_mode, + i_wstrobe, + i_dt, + o_full, + i_renable, + o_dt, + o_empty, + o_dnum +); + +// set default parameters +parameter P_RANGE = 7; +parameter P_DEPTH = 1 << P_RANGE; // 128 +//////////////////////////// +// I/O definition +//////////////////////////// +input clk_core; // system clock +input clk_vi; +input rst_x; // system reset +input [1:0] i_color_mode; +input i_wstrobe; // write strobe +input [31:0] i_dt; // write data +output o_full; // write data full +input i_renable; // read enable +output [15:0] o_dt; // read data +output o_empty; // read data empty +output [P_RANGE:0] o_dnum; // written data number + +///////////////////////// +// Register definition +///////////////////////// +reg [P_RANGE-1:0] r_write_counter; +reg [P_RANGE-1:0] r_read_counter; +// data registers +reg [2:0] r_select_hw; +///////////////////////// +// wire definition +///////////////////////// +wire o_full; +wire o_empty; +wire [15:0] o_dt; +wire w_we; +wire w_re; +wire [31:0] w_dt32; +wire [P_RANGE-1:0] w_read_counter_inc; +wire [P_RANGE-1:0] w_read_counter; +wire [15:0] w_dt16; +wire [7:0] w_dt8; +wire [3:0] w_dt4; +// ///////////////////////// +// assign statement +///////////////////////// +assign w_dt16 = (r_select_hw[0]) ? w_dt32[31:16] : w_dt32[15:0]; +assign w_dt8 = (r_select_hw[1:0] == 'd3) ? w_dt32[31:24] : + (r_select_hw[1:0] == 'd2) ? w_dt32[23:16] : + (r_select_hw[1:0] == 'd1) ? w_dt32[15:8] : + w_dt32[7:0]; + +assign w_dt4 = (r_select_hw[2:0] == 'd7) ? w_dt32[31:28] : + (r_select_hw[2:0] == 'd6) ? w_dt32[27:24] : + (r_select_hw[2:0] == 'd5) ? w_dt32[23:20] : + (r_select_hw[2:0] == 'd4) ? w_dt32[19:16] : + (r_select_hw[2:0] == 'd3) ? w_dt32[15:12] : + (r_select_hw[2:0] == 'd2) ? w_dt32[11:8] : + (r_select_hw[2:0] == 'd1) ? w_dt32[7:4] : + w_dt32[3:0]; + +assign o_dt = (i_color_mode == 'd3) ? {12'd0,w_dt4} : + (i_color_mode == 'd2) ? {8'd0,w_dt8} : + w_dt16 ; +assign o_dnum = 0; +assign o_full = 1'b0; +assign o_empty = 1'b0; +assign w_we = i_wstrobe; +assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw == 'd7) : + (i_color_mode == 'd2) ? (r_select_hw[1:0] == 'd3) : + (r_select_hw[0] == 'd1) + ); +assign w_read_counter_inc = r_read_counter + 1'b1; +assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter; + +//////////////////////// +// always +/////////////////////// + // write side (clk_core) + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_write_counter <= 'd0; + end else begin + if (w_we) begin + r_write_counter <= r_write_counter + 1'b1; + end + end + end + + // read side (clk_vi) + always @(posedge clk_vi or negedge rst_x) begin + if (~rst_x) begin + r_read_counter <= 'd0; + end else begin + if (w_re) begin + r_read_counter <= w_read_counter_inc; + end + end + end + + // select half word + always @(posedge clk_vi or negedge rst_x) begin + if (~rst_x) begin + r_select_hw <= 3'b0; + end else begin + if (i_renable) r_select_hw <= r_select_hw + 1'b1; + end + end + +/////////////////// +// module instance +/////////////////// + fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(32),.P_RANGE( P_RANGE)) ram_00 ( + .clka(clk_core), + .clkb(clk_vi), + .wea(w_we), + .addra(r_write_counter), + .addrb(w_read_counter), + .dia(i_dt), + .doa(), + .dob(w_dt32) + ); + +endmodule + +
fm_hvc/fm_afifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fm_hvc/fm_hvc_core.v =================================================================== --- fm_hvc/fm_hvc_core.v (nonexistent) +++ fm_hvc/fm_hvc_core.v (revision 3) @@ -0,0 +1,227 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_hvc_core.v +// +// Abstract: +// HV counter core +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_hvc_core ( + clk_vi, + rst_x, + // configuration registers + i_video_start, + // control out (only for internal use) + o_vsync_i, + o_hsync_i, + // video out timing + o_active, + o_first_line, + // video out + o_r, + o_g, + o_b, + o_vsync_x, + o_hsync_x, + o_blank_x, + o_de +); + +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clk_vi; // 25MHz + input rst_x; + // configuration registers + input i_video_start; + // control out (only for internal use) + output o_vsync_i; + output o_hsync_i; + // video out timing + output o_active; + output o_first_line; + + output [7:0] o_r; + output [7:0] o_g; + output [7:0] o_b; + output o_vsync_x; + output o_hsync_x; + output o_blank_x; + output o_de; +////////////////////////////////// +// reg +////////////////////////////////// + reg [9:0] r_hcnt; + reg [9:0] r_vcnt; + reg r_vsync_x; + reg r_hsync_x; + reg r_hsync_x_i; // internal use, vactive only + + reg r_blank_x; + + reg r_vsync_neg; + reg r_hsync_neg; + reg r_de; + + +////////////////////////////////// +// wire +////////////////////////////////// + wire w_h_end; + wire w_v_end; + + wire w_vsync; + wire w_hsync; + wire w_hsync_dma; + wire w_hactive; + wire w_vactive_first; // for aa + wire w_vactive; + wire w_active; + wire w_active_first; // for aa + + // color bar + wire w_r_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) | + ((r_hcnt >= 252) & (r_hcnt <= 343)) | + ((r_hcnt >= 527) & (r_hcnt <= 617)) | + ((r_hcnt >= 618) & (r_hcnt <= 708)); + wire w_g_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) | + ((r_hcnt >= 252) & (r_hcnt <= 343)) | + ((r_hcnt >= 344) & (r_hcnt <= 435)) | + ((r_hcnt >= 436) & (r_hcnt <= 526)); + wire w_b_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) | + ((r_hcnt >= 344) & (r_hcnt <= 435)) | + ((r_hcnt >= 527) & (r_hcnt <= 617)) | + ((r_hcnt >= 709) & (r_hcnt <= 799)); + + wire [7:0] w_r_test = {8{w_r_test_en}}; + wire [7:0] w_g_test = {8{w_g_test_en}}; + wire [7:0] w_b_test = {8{w_b_test_en}}; + + wire w_hsync_x_i; +////////////////////////////////// +// assign +////////////////////////////////// + + // VGA : 60Hz + assign w_h_end = (r_hcnt == 'd799); // 800 clock + assign w_v_end = w_h_end & (r_vcnt == 'd524); // 525 line + + assign w_vsync = ((r_vcnt == 10'd10) | (r_vcnt == 10'd11)) ? 1'b0 : 1'b1; + assign w_hsync = ((r_hcnt >= 10'd16)&(r_hcnt <= 10'd111)) ? 1'b0 : 1'b1; + assign w_hsync_dma = ((r_hcnt >= 10'd16)&(r_hcnt <= 10'd39)) ? 1'b0 : 1'b1; + + assign w_hactive = ((r_hcnt >= 10'd160)&(r_hcnt <= 10'd799)) ? 1'b1 : 1'b0; + assign w_vactive = ((r_vcnt >= 10'd45)&(r_vcnt <= 10'd524)) ? 1'b1 : 1'b0; + assign w_vactive_first = (r_vcnt == 10'd45); + + assign w_active = w_hactive & w_vactive; + assign w_active_first = w_vactive_first; + + assign w_hsync_x_i = w_vactive & w_hsync_dma; + // color should be black in blanking + //assign w_r = (w_active) ? w_rgb[7:0] : 8'h00; + //assign w_g = (w_active) ? w_rgb[15:8] : 8'h00; + //assign w_b = (w_active) ? w_rgb[23:16] : 8'h00; + + assign o_vsync_x = r_vsync_x;//r_vsync_neg; + assign o_hsync_x = r_hsync_x;//r_hsync_neg; + assign o_blank_x = r_blank_x; + assign o_de = r_de; + + assign o_r = (w_active) ? w_r_test : 8'h00; + assign o_g = (w_active) ? w_g_test : 8'h00; + assign o_b = (w_active) ? w_b_test : 8'h00; + + assign o_vsync_i = r_vsync_x; + assign o_hsync_i = r_hsync_x_i; + assign o_active = w_active; + assign o_first_line = w_active_first; +////////////////////////////////// +// always +////////////////////////////////// + // H counter + always @(posedge clk_vi or negedge rst_x) begin + if (~rst_x) begin + r_hcnt <= 11'b0; + end else begin + if (w_h_end) r_hcnt <= 11'b0; + else r_hcnt <= r_hcnt + 1'b1; + end + end + + // V counter + always @(posedge clk_vi or negedge rst_x) begin + if (~rst_x) begin +// r_vcnt <= 10'd0; +// r_vcnt <= 10'd36; // this is only for faster simulatin + r_vcnt <= 10'd9; // this is only for faster simulatin (v rise) + end else begin + if (w_v_end) r_vcnt <= 10'd0; + else if (w_h_end) r_vcnt <= r_vcnt + 1'b1; + end + end + + // sync + always @(posedge clk_vi or negedge rst_x) begin + if (~rst_x) begin + r_vsync_x <= 1'b1; + r_hsync_x <= 1'b1; + r_blank_x <= 1'b1; + r_de <= 1'b0; + end else begin + r_vsync_x <= w_vsync; + r_hsync_x <= w_hsync; + r_hsync_x_i <= w_hsync_x_i; + r_blank_x <= w_active; + r_de <= w_active; + end + end + + + + // neg-edge registers for output timing adjustment + always @(negedge clk_vi or negedge rst_x) begin + if (~rst_x) begin + r_vsync_neg <= 1'b1; + r_hsync_neg <= 1'b1; + end else begin + r_vsync_neg <= r_vsync_x; + r_hsync_neg <= r_hsync_x; + end + end + + +endmodule
fm_hvc/fm_hvc_core.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: de0/d3d_top.v =================================================================== --- de0/d3d_top.v (nonexistent) +++ de0/d3d_top.v (revision 3) @@ -0,0 +1,104 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// d3d_top.v +// +// Abstract: +// DE0 RTL top module +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module d3d_top ( +// system +input CLK, +input RST, +// SDRAM +output DRAM_CLK, +output [11:0] DRAM_ADDR, +output [1:0] DRAM_BA, +output DRAM_CAS_N, +output DRAM_CKE, +output DRAM_CS_N, +inout[15:0] DRAM_DQ, +output [1:0] DRAM_DQM, +output DRAM_RAS_N, +output DRAM_WE_N, +input [3:0] SW, +// USB +//inout USB_DP, +//inout USB_DN, +// VGA +output [3:0] VGA_R, +output [3:0] VGA_G, +output [3:0] VGA_B, +output VGA_VS, +output VGA_HS, +// FLASH +output DCLK, +output SCE, +output SDO, +input DATA +); + +d3d_system u0 ( + .clk_clk(CLK), + .reset_reset_n(RST), + .altpll_0_c1_clk(DRAM_CLK), + .sdram0_wire_addr(DRAM_ADDR), + .sdram0_wire_ba(DRAM_BA), + .sdram0_wire_cas_n(DRAM_CAS_N), + .sdram0_wire_cke(DRAM_CKE), + .sdram0_wire_cs_n(DRAM_CS_N), + .sdram0_wire_dq(DRAM_DQ), + .sdram0_wire_dqm(DRAM_DQM), + .sdram0_wire_ras_n(DRAM_RAS_N), + .sdram0_wire_we_n(DRAM_WE_N), + .altpll_0_areset_conduit_export(), + .altpll_0_locked_conduit_export(), + .altpll_0_phasedone_conduit_export(), + .pio_0_in_export(SW[3:0]), + //.usb_inout_dp(USB_DP), + //.usb_inout_dn(USB_DN), + .vga_out_cr(VGA_R), + .vga_out_cg(VGA_G), + .vga_out_cb(VGA_B), + .vga_out_vsync_x(VGA_VS), + .vga_out_hsync_x(VGA_HS), + .epcs_flash_controller_0_external_dclk (DCLK), + .epcs_flash_controller_0_external_sce (SCE), + .epcs_flash_controller_0_external_sdo (SDO), + .epcs_flash_controller_0_external_data0 (DATA) +); + +endmodule \ No newline at end of file
de0/d3d_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: de0/fm_vga_wrapper.v =================================================================== --- de0/fm_vga_wrapper.v (nonexistent) +++ de0/fm_vga_wrapper.v (revision 3) @@ -0,0 +1,191 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_vga_wrapper.v +// +// Abstract: +// AVALON VGA Master +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_vga_wrapper ( + // Avalon-MM Slave Interface + input clk_core, + input rst_x, + input [3:0] i_avs_adr, + input [3:0] i_avs_be, + input i_avs_r, + output [31:0] o_avs_rd, + input i_avs_w, + input [31:0] i_avs_wd, + output o_avs_wait, + // Avalon-MM Master Interface + output [23:0] o_avm_adr, + output [3:0] o_avm_be, + output [5:0] o_avm_blen, + output o_avm_r, + input i_avm_wait, + input i_avm_rvalid, + input [31:0] i_avm_rd, + // Vsync int + output o_int, + // VGA output + input clk25m, + output [3:0] o_cr, + output [3:0] o_cg, + output [3:0] o_cb, + output o_vsync_x, + output o_hsync_x +); + +// bridge + wire w_req; + wire w_wr; + wire [3:0] w_adrs; + wire w_ack; + wire [3:0] w_be; + wire [31:0] w_wd; + wire w_rstr; + wire [31:0] w_rd; + + wire w_video_start; + wire [6:0] w_fb0_offset; + wire [6:0] w_fb1_offset; + wire [1:0] w_color_mode; + wire w_front_buffer; + + wire w_vint_x; + wire w_vint_edge; + + wire [7:0] w_cr; + wire [7:0] w_cg; + wire [7:0] w_cb; + wire [25:0] w_avm_adr; + + assign o_cr = w_cr[7:4]; + assign o_cg = w_cg[7:4]; + assign o_cb = w_cb[7:4]; + assign o_avm_adr = {w_avm_adr,2'b00}; // byte address + assign o_avm_be = 4'hf; + +fm_avalon #(.P_AVALON_ADR_WIDTH(4)) u_avalon ( + .clk_core(clk_core), + .rst_x(rst_x), + // AVALON slave bus + .i_av_adr(i_avs_adr), + .i_av_be(i_avs_be), + .i_av_r(i_avs_r), + .o_av_rd(o_avs_rd), + .i_av_w(i_avs_w), + .i_av_wd(i_avs_wd), + .o_av_wait(o_avs_wait), + // internal side + .o_req(w_req), + .o_wr(w_wr), + .o_adrs(w_adrs), + .i_ack(w_ack), + .o_be(w_be), + .o_wd(w_wd), + .i_rstr(w_rstr), + .i_rd(w_rd) +); + +// System controller +fm_hsys fm_hsys ( + .clk_core(clk_core), + .rst_x(rst_x), + // internal interface + .i_req(w_req), + .i_wr(w_wr), + .i_adrs(w_adrs), + .o_ack(w_ack), + .i_be(w_be), + .i_wd(w_wd), + .o_rstr(w_rstr), + .o_rd(w_rd), + // configuration output + // Video controller + .o_video_start(w_video_start), + .o_aa_en(), + .o_fb0_offset(w_fb0_offset), + .o_fb1_offset(w_fb1_offset), + .o_color_mode(w_color_mode), + .o_front_buffer(w_front_buffer), + .o_fb_blend_en(), + // vint + .i_vint_x(w_vint_x), + .i_vint_edge(w_vint_edge), + // vertex dma int + .i_vtx_int(1'b0), + // int out + .o_int(o_int) +); + +// Video controller +fm_hvc fm_hvc ( + .clk_core(clk_core), + .clk_vi(clk25m), + .rst_x(rst_x), + // configuration registers + .i_video_start(w_video_start), + .i_fb0_offset(w_fb0_offset), + .i_fb0_ms_offset(4'h0), + .i_fb1_offset(w_fb1_offset), + .i_fb1_ms_offset(4'h0), + .i_color_mode(w_color_mode), + .i_front_buffer(w_front_buffer), + .i_aa_en('d0), + .i_fb_blend_en(1'b0), + // status out + .o_vint_x(w_vint_x), + .o_vint_edge(w_vint_edge), + // dram if + .o_req(o_avm_r), + .o_adrs(w_avm_adr), + .o_len(o_avm_blen), + .i_ack(!i_avm_wait), + .i_rstr(i_avm_rvalid), + .i_rd(i_avm_rd), + // video out + .clk_vo(), + .o_r(w_cr), + .o_g(w_cg), + .o_b(w_cb), + .o_vsync_x(o_vsync_x), + .o_hsync_x(o_hsync_x), + .o_blank_x(), + .o_de() +); + +endmodule
de0/fm_vga_wrapper.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: de0/fm_avalon.v =================================================================== --- de0/fm_avalon.v (nonexistent) +++ de0/fm_avalon.v (revision 3) @@ -0,0 +1,230 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_3d_wrapper.v +// +// Abstract: +// Monophony core top module AVALON version +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_avalon( + clk_core, + rst_x, + // AVALON bus + i_av_adr, + i_av_be, + i_av_r, + o_av_rd, + i_av_w, + i_av_wd, + o_av_wait, + // internal side + o_req, + o_wr, + o_adrs, + i_ack, + o_be, + o_wd, + i_rstr, + i_rd +); +parameter P_AVALON_ADR_WIDTH='d10; +parameter P_AVALON_BE_WIDTH='d4; +parameter P_AVALON_DATA_WIDTH='d32; +parameter P_INTERNAL_ADR_WIDTH=P_AVALON_ADR_WIDTH; +parameter P_INTERNAL_BE_WIDTH=P_AVALON_BE_WIDTH; +parameter P_INTERNAL_DATA_WIDTH=P_AVALON_DATA_WIDTH; + + +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clk_core; + input rst_x; + // AVALON Bus + input [P_AVALON_ADR_WIDTH-1:0] + i_av_adr; + input [P_AVALON_BE_WIDTH-1:0] + i_av_be; + input i_av_r; + output [P_AVALON_DATA_WIDTH-1:0] + o_av_rd; + input i_av_w; + input [P_AVALON_DATA_WIDTH-1:0] + i_av_wd; + output o_av_wait; + // internal side + output o_req; + output o_wr; + output [P_INTERNAL_ADR_WIDTH-1:0] + o_adrs; + input i_ack; + output [P_INTERNAL_BE_WIDTH-1:0] + o_be; + output [P_INTERNAL_DATA_WIDTH-1:0] + o_wd; + input i_rstr; + input [P_INTERNAL_DATA_WIDTH-1:0] + i_rd; + +////////////////////////////////// +// parameter definition +////////////////////////////////// + localparam P_IDLE = 2'h0; + localparam P_WAIT_ACK = 2'h1; + localparam P_R_WAIT_RDATA = 2'h2; + localparam P_ACK_OUT = 2'h3; +////////////////////////////////// +// reg +////////////////////////////////// + reg [1:0] r_state; + reg r_req; + reg r_wr; + reg [P_INTERNAL_ADR_WIDTH-1:0] + r_adrs; + reg [P_INTERNAL_DATA_WIDTH-1:0] + r_rdata; + reg [P_INTERNAL_BE_WIDTH-1:0] + r_be; + reg [P_INTERNAL_DATA_WIDTH-1:0] + r_wd; + +////////////////////////////////// +// wire +////////////////////////////////// + wire [P_INTERNAL_ADR_WIDTH-1:0] + w_adrs; + wire [P_INTERNAL_DATA_WIDTH-1:0] + w_rdata; + wire [P_INTERNAL_BE_WIDTH-1:0] + w_be; + wire [P_INTERNAL_DATA_WIDTH-1:0] + w_wd; +////////////////////////////////// +// assign +////////////////////////////////// + generate + if (P_INTERNAL_DATA_WIDTH == 'd8) begin + wire [1:0] w_ba; + assign o_av_rd = {'d4{r_rdata}}; + assign w_ba = i_av_be[1] ? 2'd1 : + i_av_be[2] ? 2'd2 : + i_av_be[3] ? 2'd3 : + 2'd0 ; + assign w_adrs = {i_av_adr,w_ba}; + assign w_be = i_av_be[w_ba]; + assign w_wd = (w_ba == 'd1) ? i_av_wd[15:8]: + (w_ba == 'd2) ? i_av_wd[23:16]: + (w_ba == 'd3) ? i_av_wd[31:24]: + i_av_wd[7:0]; + + end else begin + assign o_av_rd = r_rdata; + assign w_adrs = i_av_adr; + assign w_be = i_av_be; + assign w_wd = i_av_wd; + end + endgenerate + assign o_req = r_req; + assign o_wr = r_wr; + assign o_adrs = r_adrs; + assign o_be = r_be; + assign o_wd = r_wd; + assign o_av_wait = !(!(i_av_r|i_av_w) & (r_state == P_IDLE) | + (r_state == P_ACK_OUT)); + + +////////////////////////////////// +// always +////////////////////////////////// + // core clock domain + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_state <= P_IDLE; + r_req <= 1'b0; + r_wr <= 1'b0; + r_adrs <= {P_INTERNAL_ADR_WIDTH{1'b0}}; + r_rdata <= {P_INTERNAL_DATA_WIDTH{1'b0}}; + r_be <= {P_INTERNAL_BE_WIDTH{1'b0}}; + r_wd <= {P_INTERNAL_DATA_WIDTH{1'b0}}; + end else begin + case (r_state) + P_IDLE: begin + if (i_av_w) begin + // write + r_req <= 1'b1; + r_wr <= 1'b1; + r_adrs <= w_adrs; + r_be <= w_be; + r_wd <= w_wd; + r_state <= P_WAIT_ACK; + end else if (i_av_r) begin + // read + r_req <= 1'b1; + r_wr <= 1'b0; + r_adrs <= w_adrs; + r_state <= P_WAIT_ACK; + end + end + P_WAIT_ACK: begin + if (i_ack) begin + r_req <= 1'b0; + if (r_wr) begin + // write + r_state <= P_ACK_OUT; + end else begin + if (i_rstr) begin + r_rdata <= i_rd; + r_state <= P_ACK_OUT; + end else begin + r_state <= P_R_WAIT_RDATA; + end + end + end + end + P_R_WAIT_RDATA: begin + if (i_rstr) begin + r_rdata <= i_rd; + r_state <= P_ACK_OUT; + end + end + P_ACK_OUT: begin + r_state <= P_IDLE; + end + endcase + end + end + +endmodule
de0/fm_avalon.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: de0/fm_hsys.v =================================================================== --- de0/fm_hsys.v (nonexistent) +++ de0/fm_hsys.v (revision 3) @@ -0,0 +1,322 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_hsys.v +// +// Abstract: +// System register module +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_hsys ( + clk_core, + rst_x, + // internal interface + i_req, + i_wr, + i_adrs, + o_ack, + i_be, + i_wd, + o_rstr, + o_rd, + // configuration output + // Video controller + o_video_start, + o_aa_en, + o_fb0_offset, + o_fb1_offset, + o_color_mode, + o_front_buffer, + o_fb_blend_en, + // status from Video controller + i_vint_x, + i_vint_edge, + // status from 3D core + i_vtx_int, + // int out + o_int +); +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clk_core; + input rst_x; + // internal interface + input i_req; + input i_wr; + input [3:0] i_adrs; + output o_ack; + input [3:0] i_be; + input [31:0] i_wd; + output o_rstr; + output [31:0] o_rd; + // configuration output + // Video controller + output o_video_start; + output [2:0] o_aa_en; + output [6:0] o_fb0_offset; + output [6:0] o_fb1_offset; + output [1:0] o_color_mode; + output o_front_buffer; + output o_fb_blend_en; + // status from Video controller + input i_vint_x; + input i_vint_edge; + // status from 3D core + input i_vtx_int; + // int out + output reg o_int; + +////////////////////////////////// +// regs +////////////////////////////////// + reg r_video_start; + reg [2:0] r_aa_en; + reg [6:0] r_fb0_offset; + reg [6:0] r_fb1_offset; + reg [1:0] r_color_mode; + reg r_fb_blend_en; + + reg r_rstr; + reg [31:0] r_rd; + + reg r_vint_x; + reg [2:0] r_mask; + reg r_front_buffer; + + reg r_vint_clear; +////////////////////////////////// +// wire +////////////////////////////////// + wire w_hit0; + wire w_hit1; + wire w_hit2; + wire w_hit3; + wire w_hit4; + wire w_hit5; + wire w_hit8; + wire w_hit9; + wire w_hitA; + wire w_hitB; + wire w_hitC; + wire w_hitD; + wire w_hitE; + wire w_hitF; + wire w_hit10; + wire w_hit11; + wire w_hit12; + wire w_hit13; + + wire w_hit0_w; + wire w_hit1_w; + wire w_hit2_w; + wire w_hit3_w; + wire w_hit4_w; + wire w_hit5_w; + wire w_hit9_w; + wire w_hitA_w; + wire w_hitB_w; + + wire [31:0] w_rd; + wire w_rstr; + wire w_vint_x; + wire w_vint_on; + wire [2:0] w_int; +////////////////////////////////// +// assign +////////////////////////////////// +assign w_hit0 = (i_adrs[3:0] == 4'h0); // 0 +assign w_hit1 = (i_adrs[3:0] == 4'h1); // 4 +assign w_hit2 = (i_adrs[3:0] == 4'h2); // 8 +assign w_hit3 = (i_adrs[3:0] == 4'h3); // c +assign w_hit4 = (i_adrs[3:0] == 4'h4); // 10 +assign w_hit5 = (i_adrs[3:0] == 4'h5); // 14 +assign w_hit8 = (i_adrs[3:0] == 4'h8); // 20 +assign w_hit9 = (i_adrs[3:0] == 4'h9); // 24 +assign w_hitA = (i_adrs[3:0] == 4'ha); // 28 +assign w_hitB = (i_adrs[3:0] == 4'hb); // 2c + +assign w_hit0_w = w_hit0 & i_wr & i_req; +assign w_hit1_w = w_hit1 & i_wr & i_req; +assign w_hit2_w = w_hit2 & i_wr & i_req; +assign w_hit3_w = w_hit3 & i_wr & i_req; +assign w_hit4_w = w_hit4 & i_wr & i_req; +assign w_hit5_w = w_hit5 & i_wr & i_req; +assign w_hit9_w = w_hit9 & i_wr & i_req; +assign w_hitA_w = w_hitA & i_wr & i_req; +assign w_hitB_w = w_hitB & i_wr & i_req; + +assign w_rstr = i_req & !i_wr; +assign w_rd = (w_hit0) ? {16'hbeef,5'b0,r_aa_en,7'b0,r_video_start} : + (w_hit1) ? {6'b0,r_fb0_offset,19'b0} : + (w_hit2) ? {6'b0,r_fb1_offset,19'b0} : + (w_hit5) ? {30'b0,r_color_mode} : + (w_hit8) ? {29'b0,i_vtx_int,!i_vint_x,!r_vint_x} : + (w_hit9) ? {31'b0,r_vint_clear} : + (w_hitA) ? {29'b0,r_mask} : + {31'b0,r_front_buffer}; + + +assign w_vint_on = i_vint_edge; // falling edge detect +assign w_vint_x = ~r_vint_clear | i_vint_x; + +assign w_int[0] = (r_mask[0]) ? 1'b0 : ~r_vint_x; +assign w_int[1] = 1'b0; +assign w_int[2] = (r_mask[2]) ? 1'b0 : i_vtx_int; + +assign o_rstr = r_rstr; +assign o_rd = r_rd; +assign o_ack = i_req; + +assign o_video_start = r_video_start; +assign o_aa_en = r_aa_en; +assign o_fb0_offset = r_fb0_offset; +assign o_fb1_offset = r_fb1_offset; +assign o_color_mode = r_color_mode; +assign o_front_buffer = r_front_buffer; +assign o_fb_blend_en = r_fb_blend_en; + +////////////////////////////////// +// always +////////////////////////////////// + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_video_start <= 1'b0; + end else begin + if (w_hit0_w) begin + if (i_be[0]) r_video_start <= i_wd[0]; + if (i_be[1]) r_aa_en <= i_wd[10:8]; + if (i_be[2]) r_fb_blend_en <= i_wd[16]; + end + end +end + +// register holds 32-bit address +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_fb0_offset <= 7'b0; + end else begin + if (w_hit1_w) begin + if (i_be[2]) r_fb0_offset[4:0] <= i_wd[23:19]; + if (i_be[3]) r_fb0_offset[6:5] <= i_wd[25:24]; + end + end +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_fb1_offset <= 7'b0; + end else begin + if (w_hit2_w) begin + if (i_be[2]) r_fb1_offset[4:0] <= i_wd[23:19]; + if (i_be[3]) r_fb1_offset[6:5] <= i_wd[25:24]; + end + end +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_color_mode <= 2'b0; + end else begin + if (w_hit5_w) begin + if (i_be[0]) r_color_mode <= i_wd[1:0]; + end + end +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_vint_clear <= 1'b0; + end else begin + if (w_hit9_w) begin + if (i_be[0]) r_vint_clear <= i_wd[0]; + end else if (w_vint_on) begin + r_vint_clear <= 1'b1; + end + end +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_mask <= 2'b11; + end else begin + if (w_hitA_w) begin + if (i_be[0]) r_mask <= i_wd[1:0]; + end + end +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_front_buffer <= 1'b0; + end else begin + if (w_hitB_w) begin + if (i_be[0]) r_front_buffer <= i_wd[0]; + end + end +end + + +always @(posedge clk_core) begin + r_rd <= w_rd; +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_rstr <= 1'b0; + end else begin + r_rstr <= w_rstr; + end +end + + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_vint_x <= 1'b1; + end else begin + r_vint_x <= w_vint_x; + end +end + +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + o_int <= 1'b0; + end else begin + o_int <= |w_int; + end +end + +endmodule
de0/fm_hsys.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: de0/fm_3d_wrapper.v =================================================================== --- de0/fm_3d_wrapper.v (nonexistent) +++ de0/fm_3d_wrapper.v (revision 3) @@ -0,0 +1,182 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_avalon.v +// +// Abstract: +// AVALON interface +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +`include "fm_3d_define.v" +module fm_3d_wrapper ( + // system + input clk_core, + input rst_x, + output o_int, + // avalon slave I/F + input [5:0] i_avs_adr, + input [3:0] i_avs_be, + input i_avs_r, + output [31:0] o_avs_rd, + input i_avs_w, + input [31:0] i_avs_wd, + output o_avs_wait, + // avalon geometry DMA I/F + output [25:0] o_avm_adr, + output [3:0] o_avm_be, + output [31:0] o_avm_wd, + output [2:0] o_avm_blen, + output o_avm_r, + output o_avm_w, + input i_avm_wait, + input i_avm_rvalid, + input [31:0] i_avm_rd +); + +wire w_req; +wire w_wr; +wire [5:0] w_adrs; +wire w_ack; +wire [3:0] w_be; +wire [31:0] w_wd; +wire w_rstr; +wire [31:0] w_rd; +wire [3:0] w_avm_be; +wire w_avm_ack; + +wire w_req_m; +wire w_wr_m; +`ifdef D3D_WISHBONE +reg r_state; +assign o_avm_r = w_req_m & (~w_wr_m) & (r_state == P_IDLE); +assign w_avm_ack = (r_state == P_READ) ? i_avm_rvalid : + (!i_avm_wait & w_wr_m); +localparam P_IDLE = 1'b0; +localparam P_READ = 1'b1; +always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_state <= P_IDLE; + end else begin + case (r_state) + P_IDLE: if (w_req_m & !i_avm_wait & !w_wr_m) r_state <= P_READ; + P_READ: if (i_avm_rvalid ) r_state <= P_IDLE; + endcase + end +end +`else +assign o_avm_r = w_req_m & (~w_wr_m); +`endif +assign o_avm_w = w_req_m & (w_wr_m); +assign o_avm_be = (~w_wr_m) ? 4'hff: w_avm_be; // byte enable must be 'hff in read mode to get right data + +`ifdef D3D_WISHBONE +fm_avalon_wb #(.P_AVALON_ADR_WIDTH(6)) u_avalon_wb ( +`else +fm_avalon #(.P_AVALON_ADR_WIDTH(6)) u_avalon ( +`endif + .clk_core(clk_core), + .rst_x(rst_x), + // AVALON slave bus + .i_av_adr(i_avs_adr), + .i_av_be(i_avs_be), + .i_av_r(i_avs_r), + .o_av_rd(o_avs_rd), + .i_av_w(i_avs_w), + .i_av_wd(i_avs_wd), + .o_av_wait(o_avs_wait), + // internal side + .o_req(w_req), + .o_wr(w_wr), + .o_adrs(w_adrs), + .i_ack(w_ack), + .o_be(w_be), + .o_wd(w_wd), +`ifdef D3D_WISHBONE +`else + .i_rstr(w_rstr), +`endif + .i_rd(w_rd) +); +`ifdef D3D_WISHBONE +assign o_avm_blen = 3'd1; +wire [25:2] w_avm_adr_t; +assign o_avm_adr = {w_avm_adr_t,2'b00}; +`endif + +fm_3d_core u_3d_core ( + .clk_i(clk_core), + .rst_i(~rst_x), + .int_o(o_int), +`ifdef D3D_WISHBONE + // internal side + .s_wb_stb_i(w_req), + .s_wb_we_i(w_wr), + .s_wb_adr_i(w_adrs), + .s_wb_ack_o(w_ack), + .s_wb_sel_i(w_be), + .s_wb_dat_i(w_wd), + .s_wb_dat_o(w_rd), + // geometry DMA, pixel write + .m_wb_stb_o(w_req_m), + .m_wb_we_o(w_wr_m), + .m_wb_adr_o(w_avm_adr_t), + .m_wb_ack_i(w_avm_ack), + .m_wb_sel_o(w_avm_be), + .m_wb_dat_o(o_avm_wd), + .m_wb_dat_i(i_avm_rd), +`else + // internal side + .i_req_s(w_req), + .i_wr_s(w_wr), + .i_adrs_s({w_adrs,2'b0}), + .o_ack_s(w_ack), + .i_be_s(w_be), + .i_dbw_s(w_wd), + .o_strr_s(w_rstr), + .o_dbr_s(w_rd), + // geometry DMA, pixel write + .o_req_m(w_req_m), + .o_wr_m(w_wr_m), + .o_adrs_m(o_avm_adr), + .o_len_m(o_avm_blen), + .i_ack_m(!i_avm_wait), + .o_be_m(w_avm_be), + .o_dbw_m(o_avm_wd), + .i_strr_m(i_avm_rvalid), + .i_dbr_m(i_avm_rd) +`endif +); + +endmodule
de0/fm_3d_wrapper.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: de0/fm_avalon_wb.v =================================================================== --- de0/fm_avalon_wb.v (nonexistent) +++ de0/fm_avalon_wb.v (revision 3) @@ -0,0 +1,218 @@ +//======================================================================= +// Project Monophony +// Wire-Frame 3D Graphics Accelerator IP Core +// +// File: +// fm_avalon_wb.v +// +// Abstract: +// AVALON-WISHBOBE bus bridge +// +// Author: +// Kenji Ishimaru (kenji.ishimaru@prtissimo.com) +// +//====================================================================== +// +// Copyright (c) 2015, Kenji Ishimaru +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// -Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// -Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Revision History + +module fm_avalon_wb( + clk_core, + rst_x, + // AVALON bus + i_av_adr, + i_av_be, + i_av_r, + o_av_rd, + i_av_w, + i_av_wd, + o_av_wait, + // internal side + o_req, + o_wr, + o_adrs, + i_ack, + o_be, + o_wd, + i_rd +); +parameter P_AVALON_ADR_WIDTH='d10; +parameter P_AVALON_BE_WIDTH='d4; +parameter P_AVALON_DATA_WIDTH='d32; +parameter P_INTERNAL_ADR_WIDTH=P_AVALON_ADR_WIDTH; +parameter P_INTERNAL_BE_WIDTH=P_AVALON_BE_WIDTH; +parameter P_INTERNAL_DATA_WIDTH=P_AVALON_DATA_WIDTH; + + +////////////////////////////////// +// I/O port definition +////////////////////////////////// + input clk_core; + input rst_x; + // AVALON Bus + input [P_AVALON_ADR_WIDTH-1:0] + i_av_adr; + input [P_AVALON_BE_WIDTH-1:0] + i_av_be; + input i_av_r; + output [P_AVALON_DATA_WIDTH-1:0] + o_av_rd; + input i_av_w; + input [P_AVALON_DATA_WIDTH-1:0] + i_av_wd; + output o_av_wait; + // internal side + output o_req; + output o_wr; + output [P_INTERNAL_ADR_WIDTH-1:0] + o_adrs; + input i_ack; + output [P_INTERNAL_BE_WIDTH-1:0] + o_be; + output [P_INTERNAL_DATA_WIDTH-1:0] + o_wd; + input [P_INTERNAL_DATA_WIDTH-1:0] + i_rd; + +////////////////////////////////// +// parameter definition +////////////////////////////////// + localparam P_IDLE = 2'h0; + localparam P_WAIT_ACK = 2'h1; + localparam P_R_WAIT_RDATA = 2'h2; + localparam P_ACK_OUT = 2'h3; +////////////////////////////////// +// reg +////////////////////////////////// + reg [1:0] r_state; + reg r_req; + reg r_wr; + reg [P_INTERNAL_ADR_WIDTH-1:0] + r_adrs; + reg [P_INTERNAL_DATA_WIDTH-1:0] + r_rdata; + reg [P_INTERNAL_BE_WIDTH-1:0] + r_be; + reg [P_INTERNAL_DATA_WIDTH-1:0] + r_wd; + +////////////////////////////////// +// wire +////////////////////////////////// + wire [P_INTERNAL_ADR_WIDTH-1:0] + w_adrs; + wire [P_INTERNAL_DATA_WIDTH-1:0] + w_rdata; + wire [P_INTERNAL_BE_WIDTH-1:0] + w_be; + wire [P_INTERNAL_DATA_WIDTH-1:0] + w_wd; +////////////////////////////////// +// assign +////////////////////////////////// + generate + if (P_INTERNAL_DATA_WIDTH == 'd8) begin + wire [1:0] w_ba; + assign o_av_rd = {'d4{r_rdata}}; + assign w_ba = i_av_be[1] ? 2'd1 : + i_av_be[2] ? 2'd2 : + i_av_be[3] ? 2'd3 : + 2'd0 ; + assign w_adrs = {i_av_adr,w_ba}; + assign w_be = i_av_be[w_ba]; + assign w_wd = (w_ba == 'd1) ? i_av_wd[15:8]: + (w_ba == 'd2) ? i_av_wd[23:16]: + (w_ba == 'd3) ? i_av_wd[31:24]: + i_av_wd[7:0]; + + end else begin + assign o_av_rd = r_rdata; + assign w_adrs = i_av_adr; + assign w_be = i_av_be; + assign w_wd = i_av_wd; + end + endgenerate + assign o_req = r_req; + assign o_wr = r_wr; + assign o_adrs = r_adrs; + assign o_be = r_be; + assign o_wd = r_wd; + assign o_av_wait = !(!(i_av_r|i_av_w) & (r_state == P_IDLE) | + (r_state == P_ACK_OUT)); + + +////////////////////////////////// +// always +////////////////////////////////// + // core clock domain + always @(posedge clk_core or negedge rst_x) begin + if (~rst_x) begin + r_state <= P_IDLE; + r_req <= 1'b0; + r_wr <= 1'b0; + r_adrs <= {P_INTERNAL_ADR_WIDTH{1'b0}}; + r_rdata <= {P_INTERNAL_DATA_WIDTH{1'b0}}; + r_be <= {P_INTERNAL_BE_WIDTH{1'b0}}; + r_wd <= {P_INTERNAL_DATA_WIDTH{1'b0}}; + end else begin + case (r_state) + P_IDLE: begin + if (i_av_w) begin + // write + r_req <= 1'b1; + r_wr <= 1'b1; + r_adrs <= w_adrs; + r_be <= w_be; + r_wd <= w_wd; + r_state <= P_WAIT_ACK; + end else if (i_av_r) begin + // read + r_req <= 1'b1; + r_wr <= 1'b0; + r_adrs <= w_adrs; + r_state <= P_WAIT_ACK; + end + end + P_WAIT_ACK: begin + if (i_ack) begin + r_req <= 1'b0; + if (r_wr) begin + // write + r_state <= P_ACK_OUT; + end else begin + r_rdata <= i_rd; + r_state <= P_ACK_OUT; + end + end + end + P_ACK_OUT: begin + r_state <= P_IDLE; + end + endcase + end + end + +endmodule
de0/fm_avalon_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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