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/sram_slave.v
0,0 → 1,241
//======================================================================= |
// Project Monophony |
// Wire-Frame 3D Graphics Accelerator IP Core |
// |
// File: |
// sram_slave.v |
// |
// Abstract: |
// SRAM slave model with random read data delay. |
// |
// Author: |
// Kenji Ishimaru (info.wf3d@gmail.com) |
// |
//====================================================================== |
// |
// Copyright (c) 2015, Kenji Ishimaru |
// All rights reserved. |
// |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// -Redistributions of source code must retain the above copyright notice, |
// this list of conditions and the following disclaimer. |
// -Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR |
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// Revision History |
|
module sram_slave #( |
parameter P_ADRS_WIDTH = 24, |
parameter P_BE_WIDTH = 4, |
parameter P_DATA_WIDTH = 32, |
parameter P_BLEN_WIDTH = 6, |
parameter P_SEED = 'd0 |
) |
( |
input clk_core, |
input rst_x, |
input i_req, |
input i_wr, |
input [P_ADRS_WIDTH-1:0] i_adrs, |
input [P_BLEN_WIDTH-1:0] i_blen, |
output o_ack, |
input i_strw, |
input [P_BE_WIDTH-1:0] i_be, |
input [P_DATA_WIDTH-1:0] i_dbw, |
output o_ackw, |
output o_strr, |
output [P_DATA_WIDTH-1:0] o_dbr |
); |
|
////////////////////////////////// |
// parameter |
////////////////////////////////// |
localparam P_IDLE = 2'h0; |
localparam P_IN_WRITE = 2'h1; |
localparam P_IN_READ = 2'h2; |
|
localparam P_READ_DELAY = 'd15; |
|
////////////////////////////////// |
// wire |
////////////////////////////////// |
wire w_req; |
wire [29:0] |
w_fifo_cin; |
wire [29:0] |
w_fifo_cout; |
wire [32+4-1:0] |
w_fifo_din; |
wire [32+4-1:0] |
w_fifo_dout; |
wire w_cfifo_ack; |
wire w_dfifo_ack; |
wire w_read_req; |
wire [1:0] w_mcmd_f; |
wire [P_ADRS_WIDTH-1:0] |
w_maddr_f; |
wire [P_BLEN_WIDTH-1:0] |
w_mburst_length_f; |
wire w_command_valid; |
wire w_burst_end; |
wire [P_ADRS_WIDTH-1:0] |
w_sram_addr; |
wire [P_BE_WIDTH-1:0] |
w_sram_byte_en; |
wire [P_DATA_WIDTH-1:0] |
w_sram_wdata; |
wire [P_DATA_WIDTH-1:0] |
w_sram_rdata; |
wire w_sram_write; |
wire w_datain_valid; |
wire w_dfifi_idle_ack; |
wire [P_DATA_WIDTH-1:0] w_dbr; |
wire w_act; |
////////////////////////////////// |
// reg |
////////////////////////////////// |
reg [1:0] r_state; |
reg [P_ADRS_WIDTH-1:0] |
r_maddr; |
reg [P_BLEN_WIDTH-1:0] |
r_clength; |
reg [P_BLEN_WIDTH-1:0] |
r_mburst_length; |
reg r_read_req_1z; |
reg r_read_req_2z; |
reg [7:0] r_rand; |
reg [7:0] r_rand_rd; |
reg [31:0] r_rand_seed; |
reg [31:0] r_rand_rd_seed; |
////////////////////////////////// |
// assign |
////////////////////////////////// |
// assign o_strr = r_read_req_2z; |
assign w_burst_end = (r_mburst_length == r_clength); |
assign w_sram_addr = (r_state == P_IDLE) ? i_adrs : r_maddr; |
assign w_sram_write = ((r_state == P_IN_WRITE)&i_strw) | |
(i_req & i_wr & o_ack & w_act); |
assign o_ack = (r_state == P_IDLE) & w_act; |
assign o_ackw = 1'b1; |
assign w_read_req = (i_req & !i_wr & o_ack & w_act) | (r_state == P_IN_READ); |
assign w_act = (r_rand < 'h80); |
////////////////////////////////// |
// always |
////////////////////////////////// |
|
initial begin |
$display("RANDOM SEED = %d %m",P_SEED); |
r_rand_seed = P_SEED; |
r_rand_rd_seed = P_SEED; |
end |
always @(negedge clk_core) begin |
r_rand <= $random(r_rand_seed); |
//r_rand <= 1; |
end |
|
always @(posedge clk_core or negedge rst_x) begin |
if (~rst_x) begin |
r_state <= P_IDLE; |
end else begin |
case (r_state) |
P_IDLE : begin |
if (i_req & (i_blen != 'd1) & w_act) begin |
if (i_wr == 'd1) begin |
r_state <= P_IN_WRITE; |
end else begin |
r_rand_rd <= $random(r_rand_rd_seed); |
//r_rand_rd <= 0; |
r_state <= P_IN_READ; |
end |
end |
end |
P_IN_WRITE : begin |
if ((w_burst_end)&i_strw) r_state <= P_IDLE; |
end |
P_IN_READ : begin |
if (w_burst_end) r_state <= P_IDLE; |
end |
endcase |
end |
end |
|
always @(posedge clk_core) begin |
if ((r_state == P_IDLE)&i_req & w_act) begin |
r_maddr <= i_adrs + 1'b1; |
r_mburst_length <= i_blen; |
r_clength <= 'd2; |
end else if (r_state == P_IN_WRITE) begin |
if (i_strw) begin |
r_maddr <= r_maddr + 1'b1; |
r_clength <= r_clength + 1'b1; |
end |
end else begin |
r_maddr <= r_maddr + 1'b1; |
r_clength <= r_clength + 1'b1; |
end |
end |
|
|
always @(posedge clk_core or negedge rst_x) begin |
if (~rst_x) begin |
r_read_req_1z <= 1'b0; |
r_read_req_2z <= 1'b0; |
end else begin |
r_read_req_1z <= w_read_req; |
r_read_req_2z <= r_read_req_1z; |
end |
end |
|
////////////////////////////////// |
// module instantiation |
////////////////////////////////// |
// delay module |
|
rand_delay # (1,16) u_delay_strr ( |
.clk_core(clk_core), |
.rst_x(rst_x), |
.i_en(r_read_req_2z), |
.i_delay(r_rand_rd), |
.i_data(r_read_req_2z), |
.o_data(), |
.o_en(o_strr) |
); |
|
rand_delay #(P_DATA_WIDTH,16) u_delay_dbr ( |
.clk_core(clk_core), |
.rst_x(rst_x), |
.i_en(r_read_req_2z), |
.i_delay(r_rand_rd), |
.i_data(w_dbr), |
.o_data(o_dbr), |
.o_en() |
); |
|
|
memory_sram #(P_ADRS_WIDTH) u_memory ( |
.clk(clk_core), |
.adr(w_sram_addr), |
.din(i_dbw), |
.be(i_be), |
.dout(w_dbr), |
.rdb(~w_read_req), |
.wrb(~w_sram_write), |
.rstb(rst_x) |
); |
|
endmodule |
sram_slave.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: simple_triangle.v
===================================================================
--- simple_triangle.v (nonexistent)
+++ simple_triangle.v (revision 6)
@@ -0,0 +1,698 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// simple_triangle.v
+//
+// Abstract:
+// simple cube rendering
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+`timescale 1ns/1ns
+`include "fm_3d_define.v"
+module top();
+
+`define VERBOSE
+//`define WAVE_OUT
+`ifdef D3D_WISHBONE
+`include "tb_instance_wb.v"
+`else
+`include "tb_instance.v"
+`endif
+`include "tb_init.v"
+`include "tb_task.v"
+
+`define PP_BASE_ADDR 'h0
+
+`ifdef WAVE_OUT
+initial begin
+ $dumpvars;
+end
+`endif
+
+reg [31:0] rd;
+
+// VGA
+localparam P_SCREEN_WIDTH=640;
+localparam P_SCREEN_HEIGHT=480;
+// SVGA
+//localparam P_SCREEN_WIDTH=800;
+//localparam P_SCREEN_HEIGHT=600;
+// XGA
+//localparam P_SCREEN_WIDTH=1024;
+//localparam P_SCREEN_HEIGHT=768;
+// SXGA
+//localparam P_SCREEN_WIDTH=1280;
+//localparam P_SCREEN_HEIGHT=1024;
+// UXGA
+//localparam P_SCREEN_WIDTH=1600;
+//localparam P_SCREEN_HEIGHT=1200;
+// QXGA
+//localparam P_SCREEN_WIDTH=2048;
+//localparam P_SCREEN_HEIGHT=1536;
+
+
+localparam P_FB_TOP_ADDR='h8_0000;
+
+
+/***********************************************
+ Main test routine
+***********************************************/
+
+integer i,j;
+integer pm;
+initial pm = 0;
+
+initial begin
+ reset;
+ repeat (100) @(posedge clk_core);
+ for (i=0;i<3;i=i+1) begin
+ for (j=0;j<3;j=j+1) begin
+ render_triangle(j,i);
+ end
+ end
+ save_frame_buffer(P_FB_TOP_ADDR, P_SCREEN_WIDTH,P_SCREEN_HEIGHT,"frame_buffer.dat");
+ repeat (100) @(posedge clk_core);
+ $finish;
+end
+
+
+task reset;
+ begin
+ rst_x = 0;
+ repeat (10) @(posedge clk_core);
+ @(negedge clk_core);
+ rst_x = 1;
+ @(posedge clk_core);
+ end
+endtask
+
+task render_triangle;
+ input [1:0] x_pos;
+ input [1:0] y_pos;
+ real x_bias;
+ real y_bias;
+ real z_bias;
+ reg [31:0] r_32;
+ reg [21:0] r_22;
+ begin
+ reg_write('h08,'hf,'h000_0000); // DMA top address
+ $to_float32(rd,2.79903817);
+ reg_write('h10,'hf,rd); // m00
+ $to_float32(rd,0.0);
+ reg_write('h14,'hf,rd); // m01
+ $to_float32(rd,0.0);
+ reg_write('h18,'hf,rd); // m02
+ $to_float32(rd,0.0);
+ reg_write('h1c,'hf,rd); // m03
+ $to_float32(rd,0.0);
+ reg_write('h20,'hf,rd); // m10
+ $to_float32(rd,3.73205090);
+ reg_write('h24,'hf,rd); // m11
+ $to_float32(rd,0.0);
+ reg_write('h28,'hf,rd); // m12
+ $to_float32(rd,0.0);
+ reg_write('h2c,'hf,rd); // m13
+ $to_float32(rd,0.0);
+ reg_write('h30,'hf,rd); // m20
+ $to_float32(rd,0.0);
+ reg_write('h34,'hf,rd); // m21
+ $to_float32(rd,-1.02020204);
+ reg_write('h38,'hf,rd); // m22
+ $to_float32(rd,1.04040408);
+ reg_write('h3c,'hf,rd); // m23
+ $to_float32(rd,0.0);
+ reg_write('h40,'hf,rd); // m30
+ $to_float32(rd,0.0);
+ reg_write('h44,'hf,rd); // m31
+ $to_float32(rd,-1.00000000);
+ reg_write('h48,'hf,rd); // m32
+ $to_float32(rd,3.0);
+ reg_write('h4c,'hf,rd); // m33
+ reg_write('h64,'hf,P_FB_TOP_ADDR); // Pixel top address
+ reg_write('h68,'hf,'hff); // Pixel color
+
+ // screen width/height
+ $to_float32(rd,P_SCREEN_WIDTH);
+ reg_write('h50,'hf,rd); // Screen Width (Floating point)
+ $to_float32(rd,P_SCREEN_HEIGHT);
+ reg_write('h54,'hf,rd); // Screen Height (Floating point)
+
+ reg_write('h58,'hf,P_SCREEN_WIDTH-1); // Screen Width-1 (Integer)
+ reg_write('h5c,'hf,P_SCREEN_HEIGHT-1); // Screen Width-1 (Integer)
+ reg_write('h60,'hf,P_SCREEN_WIDTH); // Screen Width (Integer)
+ // simple test
+ x_bias = 0.0;
+ y_bias = 0.0;
+ z_bias = 0.0;
+ // bias
+ case (x_pos)
+ 'd0: x_bias = -0.7;
+ 'd1: x_bias = 0.0;
+ 'd2: x_bias = 0.7;
+ endcase
+ case (y_pos)
+ 'd0: y_bias = -0.7;
+ 'd1: y_bias = 0.0;
+ 'd2: y_bias = 0.7;
+ endcase
+ // pixel color RGB = 2:3:3
+ case (y_pos)
+ 'd0: reg_write('h68,'hf,'h0c0); // R y-flip:bit8
+ 'd1: reg_write('h68,'hf,'h038); // G
+ 'd2: reg_write('h68,'hf,'h007); // B
+ endcase
+
+
+ pm = 0;
+
+ // triangle0
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle1
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle2
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle3
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle4
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle5
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle6
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle7
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle8
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle9
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle10
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ // triangle11
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+x_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,-0.25+y_bias);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ $to_float32(rd,0.0);
+ $display("rd %h",rd);
+ u_sram_slave.u_memory.mem[pm] = rd;
+ pm = pm + 1;
+ reg_write('h0c,'hf,12*3*3); // DMA size 12triangle *3vertex*3
+ reg_write('h04,'hf,'h10); // DMA mask
+ reg_write('h01,'hf,1); // DMA start
+ while (!o_int)
+ @(posedge clk_core);
+ reg_write('h04,'hf,0); // int clear
+ end
+endtask
+
+
+task save_frame_buffer;
+ input [25:0] adrs;
+ input [15:0] width;
+ input [15:0] height;
+ input [64*8:1] file_name;
+ integer x;
+ integer y;
+ integer fp;
+ reg [1:0] stat;
+ reg hw_sel;
+ reg [1:0] bank_sel;
+ reg [25:0] adr_pix;
+
+ reg [31:0] tmp_data32;
+ reg [7:0] tmp_data;
+ reg [7:0] cr;
+ reg [7:0] cg;
+ reg [7:0] cb;
+ reg [7:0] ca;
+ begin
+ $display("saving rendering result...");
+ fp = $fopen(file_name);
+ for (y = 0; y < height; y = y + 1) begin
+ for (x = 0; x < width; x = x + 1) begin
+ adr_pix = adrs + width * y + x; // per 8bit (per pixel)
+
+ tmp_data32 = top.u_sram_slave.u_memory.mem[adr_pix[25:2]];
+ case (adr_pix[1:0])
+ 2'b00:tmp_data = tmp_data32[7:0];
+ 2'b01:tmp_data = tmp_data32[15:8];
+ 2'b10:tmp_data = tmp_data32[23:16];
+ 2'b11:tmp_data = tmp_data32[31:24];
+ endcase // case (adr_pix[1:0])
+ //RGB = 2:3:3
+ cr = {4{tmp_data[7:6]}};
+ cg = {tmp_data[5:3],tmp_data[5:3],tmp_data[5:2]};
+ cb = {tmp_data[2:0],tmp_data[2:0],tmp_data[2:1]};
+ ca = 8'hff;
+ $fwrite(fp,"%h\n", {ca,cb,cg,cr});
+ end
+ end
+ $fclose(fp);
+ end
+endtask
+endmodule
simple_triangle.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mfifo.v
===================================================================
--- mfifo.v (nonexistent)
+++ mfifo.v (revision 6)
@@ -0,0 +1,143 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// mfifo.v
+//
+// Abstract:
+// fifo module for simulation
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+module mfifo (
+ i_wstrobe,
+ i_dt,
+ o_full,
+ i_renable,
+ o_dt,
+ o_empty,
+ o_dnum,
+ clk,
+ rst_x
+);
+
+// set default parameters
+parameter WIDTH = 32;
+parameter RANGE = 2;
+parameter DEPTH = 1 << RANGE;
+////////////////////////////
+// I/O definitions
+////////////////////////////
+input i_wstrobe; // write strobe
+input [WIDTH-1:0] i_dt; // write data
+output o_full; // write data full
+input i_renable; // read enable
+output [WIDTH-1:0] o_dt; // read data
+output o_empty; // read data empty
+output [RANGE:0] o_dnum; // written data number
+input clk; // system clock
+input rst_x; // system reset
+
+/////////////////////////
+// Register definitions
+/////////////////////////
+reg [RANGE-1:0] rs_write_counter;
+reg [RANGE-1:0] rs_read_counter;
+// data registers
+reg [WIDTH-1:0] rs_data_buffer[0:DEPTH-1];
+reg [RANGE:0] rs_status;
+/////////////////////////
+// wire definitions
+/////////////////////////
+wire o_full;
+wire o_empty;
+wire [WIDTH-1:0] o_dt;
+wire [1:0] w_status;
+wire w_we;
+wire w_re;
+/////////////////////////
+// assign statements
+/////////////////////////
+assign o_full = (rs_status == DEPTH);
+assign o_empty = (rs_status == 0);
+assign o_dt = rs_data_buffer[rs_read_counter];
+assign o_dnum = rs_status;
+assign w_we = !o_full & i_wstrobe;
+assign w_re = i_renable & !o_empty;
+assign w_status = {w_re,w_we};
+////////////////////////
+// Behaviour
+///////////////////////
+ // write side
+ always @(posedge clk or negedge rst_x) begin
+ if (~rst_x) begin
+ rs_write_counter <= 'd0;
+ end else begin
+ if (w_we) begin
+ rs_write_counter <= rs_write_counter + 1'b1;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ if (w_we) begin
+ rs_data_buffer[rs_write_counter] <= i_dt;
+ end
+ end
+
+ // read side
+ always @(posedge clk or negedge rst_x) begin
+ if (~rst_x) begin
+ rs_read_counter <= 'd0;
+ end else begin
+ if (w_re) begin
+ rs_read_counter <= rs_read_counter + 1'b1;
+ end
+ end
+ end
+ // status counter
+ always @(posedge clk or negedge rst_x) begin
+ if (~rst_x) begin
+ rs_status <= 'd0;
+ end else begin
+ case (w_status)
+ 2'b01: rs_status <= rs_status + 1'b1; // write
+ 2'b10: rs_status <= rs_status - 1'b1; // read
+ //default: rs_status <= rs_status; // nothing to do
+ endcase
+ end
+ end
+
+endmodule
+
+
mfifo.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tb_instance_wb.v
===================================================================
--- tb_instance_wb.v (nonexistent)
+++ tb_instance_wb.v (revision 6)
@@ -0,0 +1,128 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// tb_instance_wb.v
+//
+// Abstract:
+// module instantiation
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+// 3D Core
+parameter P_SEED = 'd0;
+initial $display("P_SEED %d",P_SEED);
+
+ // system
+ reg clk_core;
+ reg rst_x;
+ wire o_int;
+ // register I/F
+ reg s_wb_stb_i;
+ reg s_wb_we_i;
+ reg [7:0] s_wb_adr_i;
+ reg s_wb_ack_o;
+ reg [3:0] s_wb_sel_i;
+ reg [31:0] s_wb_dat_i;
+ reg [31:0] s_wb_dat_o;
+ reg s_wb_stb_i_d;
+ reg s_wb_we_i_d;
+ reg [7:0] s_wb_adr_i_d;
+ wire s_wb_ack_o_d;
+ reg [3:0] s_wb_sel_i_d;
+ reg [31:0] s_wb_dat_i_d;
+ wire [31:0] s_wb_dat_o_d;
+ // Master I/F
+ wire w_req_m;
+ wire w_wr_m;
+ wire [31:2] w_adrs_m;
+ wire [2:0] w_len_m;
+ wire w_ack_m;
+ wire [3:0] w_be_m;
+ wire [31:0] w_dbw_m;
+ wire w_strr_m;
+ wire [31:0] w_dbr_m;
+
+always @* begin
+ s_wb_stb_i_d <= #1 s_wb_stb_i;
+ s_wb_we_i_d <= #1 s_wb_we_i;
+ s_wb_adr_i_d <= #1 s_wb_adr_i;
+ s_wb_ack_o <= #1 s_wb_ack_o_d;
+ s_wb_sel_i_d <= #1 s_wb_sel_i;
+ s_wb_dat_i_d <= #1 s_wb_dat_i;
+ s_wb_dat_o <= #1 s_wb_dat_o_d;
+end
+
+fm_3d_core u_3d_core (
+ // system
+ .clk_i(clk_core),
+ .rst_i(~rst_x),
+ .int_o(o_int),
+ // register I/F
+ .s_wb_stb_i(s_wb_stb_i_d),
+ .s_wb_we_i(s_wb_we_i_d),
+ .s_wb_adr_i(s_wb_adr_i_d[7:2]),
+ .s_wb_ack_o(s_wb_ack_o_d),
+ .s_wb_sel_i(s_wb_sel_i_d),
+ .s_wb_dat_i(s_wb_dat_i_d),
+ .s_wb_dat_o(s_wb_dat_o_d),
+ // Master I/F
+ .m_wb_stb_o(w_req_m),
+ .m_wb_we_o(w_wr_m),
+ .m_wb_adr_o(w_adrs_m),
+ .m_wb_ack_i(w_ack_m),
+ .m_wb_sel_o(w_be_m),
+ .m_wb_dat_o(w_dbw_m),
+ .m_wb_dat_i(w_dbr_m)
+);
+
+sram_slave_wb #(
+ .P_ADRS_WIDTH(24),
+ .P_BE_WIDTH(4),
+ .P_DATA_WIDTH(32),
+ .P_BLEN_WIDTH(3),
+ .P_SEED(P_SEED)) u_sram_slave (
+ .clk_core(clk_core),
+ .rst_x(rst_x),
+ .i_req(w_req_m),
+ .i_adrs(w_adrs_m[25:2]), // word address
+ .i_wr(w_wr_m),
+ .i_blen(3'd1),
+ .o_ack(w_ack_m),
+ .i_strw(w_req_m & w_wr_m),
+ .i_be(w_be_m),
+ .i_dbw(w_dbw_m),
+ .o_ackw(),
+ .o_strr(w_strr_m),
+ .o_dbr(w_dbr_m)
+ );
tb_instance_wb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rand_delay.v
===================================================================
--- rand_delay.v (nonexistent)
+++ rand_delay.v (revision 6)
@@ -0,0 +1,134 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// rand_delay.v
+//
+// Abstract:
+// Pipeline delay module (without reset)
+// parameters :
+// WIDTH data width (default value is 8)
+// NUM_DELAY number of delay cycle (default value is 8)
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+module rand_delay (
+ clk_core,
+ rst_x,
+ i_en,
+ i_delay,
+ i_data,
+ o_data,
+ o_en
+);
+
+////////////////////////////
+// parameter
+////////////////////////////
+ parameter P_WIDTH = 8;
+ parameter P_NUM_DELAY = 8;
+////////////////////////////
+// I/O definition
+////////////////////////////
+ input clk_core;
+ input rst_x;
+ input i_en;
+ input [7:0] i_delay;
+ input [P_WIDTH-1:0] i_data;
+ output [P_WIDTH-1:0] o_data;
+ output o_en;
+////////////////////////////
+// wire
+////////////////////////////
+ wire w_full;
+ wire w_ren;
+ wire [P_WIDTH-1:0] w_dt;
+ wire w_empty;
+
+////////////////////////////
+// reg
+////////////////////////////
+localparam P_IDLE = 'd0;
+localparam P_WAIT = 'd1;
+ reg [1:0] r_state;
+ reg [7:0] r_cnt;
+ reg [7:0] r_end;
+
+////////////////////////////
+// assign
+////////////////////////////
+ assign w_ren = ((r_state == P_IDLE) & (i_delay == 'd0))|
+ ((r_state == P_WAIT) & (r_end == r_cnt));
+ // in/out port connection
+ assign o_data = (w_empty) ? 'd0 : w_dt;
+ assign o_en = w_ren & !w_empty;
+////////////////////////////
+// always
+////////////////////////////
+ always @(posedge clk_core or negedge rst_x) begin
+ if (~rst_x) begin
+ r_state <= P_IDLE;
+ end else begin
+ case (r_state)
+ P_IDLE:begin
+ if (~w_empty) begin
+ if (i_delay != 0) begin
+ r_end <= i_delay;
+ r_cnt <= 'd0;
+ r_state <= P_WAIT;
+ end
+ end
+ end
+ P_WAIT:begin
+ r_cnt <= r_cnt + 1;
+ if (r_end == r_cnt) begin
+ r_state <= P_IDLE;
+ end
+ end
+ endcase
+ end
+ end
+
+mfifo #(P_WIDTH,8) u_fifo (
+ .i_wstrobe(i_en),
+ .i_dt(i_data),
+ .o_full(w_full),
+ .i_renable(w_ren),
+ .o_dt(w_dt),
+ .o_empty(w_empty),
+ .o_dnum(),
+ .clk(clk_core),
+ .rst_x(rst_x)
+);
+
+endmodule
rand_delay.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rand_delay_r.v
===================================================================
--- rand_delay_r.v (nonexistent)
+++ rand_delay_r.v (revision 6)
@@ -0,0 +1,106 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// rand_delay_r.v
+//
+// Abstract:
+// Pipeline delay module with reset
+// parameters :
+// WIDTH data width (default value is 8)
+// NUM_DELAY number of delay cycle (default value is 8)
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+module rand_delay_r (
+ clk_core,
+ rst_x,
+ i_en,
+ i_delay,
+ i_data,
+ o_data
+);
+
+////////////////////////////
+// parameter
+////////////////////////////
+ parameter P_WIDTH = 8;
+ parameter P_NUM_DELAY = 8;
+////////////////////////////
+// I/O definition
+////////////////////////////
+ input clk_core;
+ input rst_x;
+ input i_en;
+ input [7:0] i_delay;
+ input [P_WIDTH-1:0] i_data;
+ output [P_WIDTH-1:0] o_data;
+
+
+////////////////////////////
+// reg
+////////////////////////////
+ reg [P_WIDTH-1:0] r_delay[0:P_NUM_DELAY-1];
+
+////////////////////////////
+// assign
+////////////////////////////
+ // in/out port connection
+ assign o_data = (i_delay < P_NUM_DELAY) ? r_delay[i_delay] :
+ r_delay[P_NUM_DELAY-1];
+////////////////////////////
+// always
+////////////////////////////
+ always @(posedge clk_core) begin
+ if (i_en) r_delay[0] <= i_data;
+ end
+
+ // delay register connection
+ integer i;
+ always @(posedge clk_core or negedge rst_x) begin
+ if (!rst_x) begin
+ if ( P_NUM_DELAY > 1 ) begin
+ for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
+ r_delay[i] <= 0;
+ end
+ end
+ end else begin
+ if ( P_NUM_DELAY > 1 ) begin
+ for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
+ if (i_en) r_delay[i] <= r_delay[i-1];
+ end
+ end
+ end
+ end
+
+endmodule
rand_delay_r.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sram_slave_wb.v
===================================================================
--- sram_slave_wb.v (nonexistent)
+++ sram_slave_wb.v (revision 6)
@@ -0,0 +1,230 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// sram_slave_wb.v
+//
+// Abstract:
+// SRAM slave model with random read data delay.
+// for WISHBONE bus simulation
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+module sram_slave_wb #(
+ parameter P_ADRS_WIDTH = 24,
+ parameter P_BE_WIDTH = 4,
+ parameter P_DATA_WIDTH = 32,
+ parameter P_BLEN_WIDTH = 6,
+ parameter P_SEED = 'd0
+)
+ (
+ input clk_core,
+ input rst_x,
+ input i_req,
+ input i_wr,
+ input [P_ADRS_WIDTH-1:0] i_adrs,
+ input [P_BLEN_WIDTH-1:0] i_blen,
+ output o_ack,
+ input i_strw,
+ input [P_BE_WIDTH-1:0] i_be,
+ input [P_DATA_WIDTH-1:0] i_dbw,
+ output o_ackw,
+ output o_strr,
+ output [P_DATA_WIDTH-1:0] o_dbr
+ );
+
+//////////////////////////////////
+// parameter
+//////////////////////////////////
+ localparam P_IDLE = 2'h0;
+ localparam P_IN_WRITE = 2'h1;
+ localparam P_IN_READ = 2'h2;
+
+ localparam P_READ_DELAY = 'd15;
+
+//////////////////////////////////
+// wire
+//////////////////////////////////
+ wire w_req;
+ wire [29:0]
+ w_fifo_cin;
+ wire [29:0]
+ w_fifo_cout;
+ wire [32+4-1:0]
+ w_fifo_din;
+ wire [32+4-1:0]
+ w_fifo_dout;
+ wire w_cfifo_ack;
+ wire w_dfifo_ack;
+ wire w_read_req;
+ wire [1:0] w_mcmd_f;
+ wire [P_ADRS_WIDTH-1:0]
+ w_maddr_f;
+ wire [P_BLEN_WIDTH-1:0]
+ w_mburst_length_f;
+ wire w_command_valid;
+ wire w_burst_end;
+ wire [P_ADRS_WIDTH-1:0]
+ w_sram_addr;
+ wire [P_BE_WIDTH-1:0]
+ w_sram_byte_en;
+ wire [P_DATA_WIDTH-1:0]
+ w_sram_wdata;
+ wire [P_DATA_WIDTH-1:0]
+ w_sram_rdata;
+ wire w_sram_write;
+ wire w_datain_valid;
+ wire w_dfifi_idle_ack;
+ wire [P_DATA_WIDTH-1:0] w_dbr;
+ wire w_act;
+//////////////////////////////////
+// reg
+//////////////////////////////////
+ reg [1:0] r_state;
+ reg [P_ADRS_WIDTH-1:0]
+ r_maddr;
+ reg [P_BLEN_WIDTH-1:0]
+ r_mburst_length;
+ reg r_read_req_1z;
+ reg r_read_req_2z;
+ reg [7:0] r_rand;
+ reg [7:0] r_rand_rd;
+ reg [31:0] r_rand_seed;
+ reg [31:0] r_rand_rd_seed;
+ wire w_ack;
+
+//////////////////////////////////
+// assign
+//////////////////////////////////
+ assign w_sram_addr = (r_state == P_IDLE) ? i_adrs : r_maddr;
+ assign w_sram_write = ((r_state == P_IN_WRITE)&i_strw);
+ assign w_ack = (r_state == P_IDLE) & w_act;
+ assign o_ack = (r_state == P_IN_WRITE) | ((r_state == P_IN_READ) & o_strr);
+
+ assign o_ackw = 1'b1;
+ assign w_read_req = (i_req & !i_wr & w_ack & w_act) ;
+ assign w_act = (r_rand < 'h80);
+//////////////////////////////////
+// always
+//////////////////////////////////
+
+ initial begin
+ $display("RANDOM SEED = %d %m",P_SEED);
+ r_rand_seed = P_SEED;
+ r_rand_rd_seed = P_SEED;
+ end
+ always @(negedge clk_core) begin
+ r_rand <= $random(r_rand_seed);
+ //r_rand <= 1;
+ end
+
+ always @(posedge clk_core or negedge rst_x) begin
+ if (~rst_x) begin
+ r_state <= P_IDLE;
+ end else begin
+ case (r_state)
+ P_IDLE : begin
+ if (i_req & w_act) begin
+ if (i_wr == 'd1) begin
+ r_state <= P_IN_WRITE;
+ end else begin
+ //r_rand_rd <= 0;
+ r_rand_rd <= $random(r_rand_rd_seed);
+ r_state <= P_IN_READ;
+ end
+ end
+ end
+ P_IN_WRITE : begin
+ if (i_strw) r_state <= P_IDLE;
+ end
+ P_IN_READ : begin
+ if (o_strr) r_state <= P_IDLE;
+ end
+ endcase
+ end
+ end
+
+always @(posedge clk_core) begin
+ if ((r_state == P_IDLE)&i_req & w_act) begin
+ r_maddr <= i_adrs;
+ end
+end
+
+
+ always @(posedge clk_core or negedge rst_x) begin
+ if (~rst_x) begin
+ r_read_req_1z <= 1'b0;
+ r_read_req_2z <= 1'b0;
+ end else begin
+ r_read_req_1z <= w_read_req;
+ r_read_req_2z <= r_read_req_1z;
+ end
+ end
+
+//////////////////////////////////
+// module instantiation
+//////////////////////////////////
+// delay module
+
+rand_delay # (1,16) u_delay_strr (
+ .clk_core(clk_core),
+ .rst_x(rst_x),
+ .i_en(r_read_req_2z),
+ .i_delay(r_rand_rd),
+ .i_data(r_read_req_2z),
+ .o_data(),
+ .o_en(o_strr)
+);
+
+rand_delay #(P_DATA_WIDTH,16) u_delay_dbr (
+ .clk_core(clk_core),
+ .rst_x(rst_x),
+ .i_en(r_read_req_2z),
+ .i_delay(r_rand_rd),
+ .i_data(w_dbr),
+ .o_data(o_dbr),
+ .o_en()
+);
+
+
+memory_sram #(P_ADRS_WIDTH) u_memory (
+ .clk(clk_core),
+ .adr(w_sram_addr),
+ .din(i_dbw),
+ .be(i_be),
+ .dout(w_dbr),
+ .rdb(~w_read_req),
+ .wrb(~w_sram_write),
+ .rstb(rst_x)
+);
+
+endmodule
sram_slave_wb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tb_task.v
===================================================================
--- tb_task.v (nonexistent)
+++ tb_task.v (revision 6)
@@ -0,0 +1,115 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// tb_task.v
+//
+// Abstract:
+// simulation tasks
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+`ifdef D3D_WISHBONE
+task reg_write;
+ input [7:0] adrs;
+ input [3:0] be;
+ input [31:0] wd;
+ begin
+ s_wb_stb_i = 1;
+ s_wb_we_i = 1;
+ s_wb_adr_i = adrs;
+ s_wb_sel_i = be;
+ s_wb_dat_i = wd;
+ @(posedge clk_core);
+ while (!s_wb_ack_o)
+ @(posedge clk_core);
+ s_wb_stb_i = 0;
+ @(posedge clk_core);
+ end
+endtask
+
+task reg_read;
+ input [7:0] adrs;
+ output [31:0] rd;
+ begin
+ s_wb_stb_i = 1;
+ s_wb_we_i = 0;
+ s_wb_adr_i = adrs;
+ @(posedge clk_core);
+ while (!s_wb_ack_o)
+ @(posedge clk_core);
+ s_wb_stb_i = 0;
+ rd = s_wb_dat_o;
+ @(posedge clk_core);
+ end
+endtask
+`else
+task reg_write;
+ input [7:0] adrs;
+ input [3:0] be;
+ input [31:0] wd;
+ begin
+ i_req_s = 1;
+ i_wr_s = 1;
+ i_adrs_s = adrs;
+ i_be_s = be;
+ i_dbw_s = wd;
+ @(posedge clk_core);
+ while (!o_ack_s)
+ @(posedge clk_core);
+ i_req_s = 0;
+ @(posedge clk_core);
+ end
+endtask
+
+task reg_read;
+ input [7:0] adrs;
+ output [31:0] rd;
+ begin
+ i_req_s = 1;
+ i_wr_s = 0;
+ i_adrs_s = adrs;
+ @(posedge clk_core);
+ while (!o_ack_s)
+ @(posedge clk_core);
+ while (!o_strr_s) begin
+ i_req_s = 0;
+ @(posedge clk_core);
+ end
+ rd = o_dbr_s;
+ @(posedge clk_core);
+ end
+endtask
+
+`endif
+
tb_task.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tb_init.v
===================================================================
--- tb_init.v (nonexistent)
+++ tb_init.v (revision 6)
@@ -0,0 +1,83 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// tb_init.v
+//
+// Abstract:
+// Initialize simulation registers
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+initial begin
+ clk_core = 1;
+ forever begin
+ #5 clk_core = ~clk_core;
+ end
+end
+`ifdef D3D_WISHBONE
+initial begin
+ s_wb_stb_i = 0;
+ s_wb_we_i = 0;
+ s_wb_adr_i = 0;
+ s_wb_ack_o = 0;
+ s_wb_sel_i = 0;
+ s_wb_dat_i = 0;
+ s_wb_dat_o = 0;
+ s_wb_stb_i_d = 0;
+ s_wb_we_i_d = 0;
+ s_wb_adr_i_d = 0;
+ s_wb_sel_i_d = 0;
+ s_wb_dat_i_d = 0;
+end
+`else
+initial begin
+ i_req_s = 0;
+ i_wr_s = 0;
+ i_adrs_s = 0;
+ o_ack_s = 0;
+ i_be_s = 0;
+ i_dbw_s = 0;
+ o_strr_s = 0;
+ o_dbr_s = 0;
+ i_req_s_d = 0;
+ i_wr_s_d = 0;
+ i_adrs_s_d = 0;
+ i_be_s_d = 0;
+ i_dbw_s_d = 0;
+end
+`endif
+
+
+
+
tb_init.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tb_instance.v
===================================================================
--- tb_instance.v (nonexistent)
+++ tb_instance.v (revision 6)
@@ -0,0 +1,137 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// tb_instance.v
+//
+// Abstract:
+// module instantiation
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+// 3D Core
+parameter P_SEED = 'd0;
+initial $display("P_SEED %d",P_SEED);
+
+ // system
+ reg clk_core;
+ reg rst_x;
+ wire o_int;
+ // register I/F
+ reg i_req_s;
+ reg i_wr_s;
+ reg [7:0] i_adrs_s;
+ reg o_ack_s;
+ reg [3:0] i_be_s;
+ reg [31:0] i_dbw_s;
+ reg o_strr_s;
+ reg [31:0] o_dbr_s;
+
+ reg i_req_s_d;
+ reg i_wr_s_d;
+ reg [7:0] i_adrs_s_d;
+ wire o_ack_s_d;
+ reg [3:0] i_be_s_d;
+ reg [31:0] i_dbw_s_d;
+ wire o_strr_s_d;
+ wire [31:0] o_dbr_s_d;
+
+ // Master I/F
+ wire w_req_m;
+ wire w_wr_m;
+ wire [31:0] w_adrs_m;
+ wire [2:0] w_len_m;
+ wire w_ack_m;
+ wire [3:0] w_be_m;
+ wire [31:0] w_dbw_m;
+ wire w_strr_m;
+ wire [31:0] w_dbr_m;
+
+always @* begin
+ i_req_s_d <= #1 i_req_s;
+ i_wr_s_d <= #1 i_wr_s;
+ i_adrs_s_d <= #1 i_adrs_s;
+ o_ack_s <= #1 o_ack_s_d;
+ i_be_s_d <= #1 i_be_s;
+ i_dbw_s_d <= #1 i_dbw_s;
+ o_strr_s <= #1 o_strr_s_d;
+ o_dbr_s <= #1 o_dbr_s_d;
+
+end
+
+fm_3d_core u_3d_core (
+ // system
+ .clk_i(clk_core),
+ .rst_i(~rst_x),
+ .int_o(o_int),
+ // register I/F
+ .i_req_s(i_req_s_d),
+ .i_wr_s(i_wr_s_d),
+ .i_adrs_s(i_adrs_s_d),
+ .o_ack_s(o_ack_s_d),
+ .i_be_s(i_be_s_d),
+ .i_dbw_s(i_dbw_s_d),
+ .o_strr_s(o_strr_s_d),
+ .o_dbr_s(o_dbr_s_d),
+ // Master I/F
+ .o_req_m(w_req_m),
+ .o_wr_m(w_wr_m),
+ .o_adrs_m(w_adrs_m),
+ .o_len_m(w_len_m),
+ .i_ack_m(w_ack_m),
+ .o_be_m(w_be_m),
+ .o_dbw_m(w_dbw_m),
+ .i_strr_m(w_strr_m),
+ .i_dbr_m(w_dbr_m)
+);
+
+sram_slave #(
+ .P_ADRS_WIDTH(22),
+ .P_BE_WIDTH(4),
+ .P_DATA_WIDTH(32),
+ .P_BLEN_WIDTH(3),
+ .P_SEED(P_SEED)) u_sram_slave (
+ .clk_core(clk_core),
+ .rst_x(rst_x),
+ .i_req(w_req_m),
+ .i_adrs(w_adrs_m[23:2]), // word address
+ .i_wr(w_wr_m),
+ .i_blen(w_len_m),
+ .o_ack(w_ack_m),
+ .i_strw(w_req_m & w_wr_m),
+ .i_be(w_be_m),
+ .i_dbw(w_dbw_m),
+ .o_ackw(),
+ .o_strr(w_strr_m),
+ .o_dbr(w_dbr_m)
+ );
tb_instance.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: memory_sram.v
===================================================================
--- memory_sram.v (nonexistent)
+++ memory_sram.v (revision 6)
@@ -0,0 +1,142 @@
+//=======================================================================
+// Project Monophony
+// Wire-Frame 3D Graphics Accelerator IP Core
+//
+// File:
+// memory_sram.v
+//
+// Abstract:
+// sram memory for simulation
+//
+// Author:
+// Kenji Ishimaru (info.wf3d@gmail.com)
+//
+//======================================================================
+//
+// Copyright (c) 2015, Kenji Ishimaru
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// -Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// -Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Revision History
+
+module memory_sram (
+ clk,
+ adr,
+ din,
+ be,
+ dout,
+ rdb,
+ wrb,
+ rstb
+);
+
+/////////////////////////////////////
+// parameter
+////////////////////////////////////
+ parameter P_ADRS_WIDTH = 22;
+ parameter P_DATA_WIDTH = 32;
+ parameter P_BE_WIDTH = P_DATA_WIDTH/8;
+/////////////////////////////////////
+// Port Definition
+////////////////////////////////////
+ input clk;
+ input [P_ADRS_WIDTH-1:0]
+ adr;
+ input [P_DATA_WIDTH-1:0]
+ din;
+ input [P_BE_WIDTH-1:0]
+ be;
+ output [P_DATA_WIDTH-1:0]
+ dout;
+ input rdb;
+ input wrb;
+ input rstb;
+/////////////////////////////////////
+// reg
+////////////////////////////////////
+// memory instance
+ reg [31:0] mem[0:(1 << P_ADRS_WIDTH)-1];
+
+ reg [P_DATA_WIDTH-1:0]
+ r_dout_1z;
+ reg [P_DATA_WIDTH-1:0]
+ r_dout_2z;
+/////////////////////////////////////
+// wire
+////////////////////////////////////
+ wire [P_DATA_WIDTH-1:0]
+ w_dout;
+ wire [P_DATA_WIDTH-1:0]
+ w_din;
+/////////////////////////////////////
+// assign
+////////////////////////////////////
+ assign w_dout = mem[adr];
+ assign w_din = f_new_data(din,be,mem[adr]);
+ assign dout = r_dout_2z;
+/////////////////////////////////////
+// always
+////////////////////////////////////
+ integer i;
+ initial begin
+ for (i=0;i<(1 << P_ADRS_WIDTH);i=i+1)
+ mem[i] = 32'h00000000;
+ end
+ always @(posedge clk) begin
+ if (wrb == 1'b0) begin
+ mem[adr] <= w_din;
+ end
+ end
+
+//`ifdef RTL_DEBUG
+// always @(posedge clk) begin
+// if (wrb == 1'b0) begin
+// $display("a4 a d = %h %h",adr,adr<<2,w_din);
+// end
+// end
+//`endif
+
+ always @(posedge clk) begin
+ r_dout_1z <= w_dout;
+ r_dout_2z <= r_dout_1z;
+ end
+
+
+ function [P_DATA_WIDTH-1:0] f_new_data;
+ input [P_DATA_WIDTH-1:0] new_data;
+ input [P_BE_WIDTH-1:0] be;
+ input [P_DATA_WIDTH-1:0] cur_data;
+ reg [P_DATA_WIDTH-1:0] result;
+ begin
+ result = cur_data;
+ if (be[0]) result[7:0] = new_data[7:0];
+ if (be[1]) result[15:8] = new_data[15:8];
+ if (be[2]) result[23:16] = new_data[23:16];
+ if (be[3]) result[31:24] = new_data[31:24];
+ f_new_data = result;
+ end
+ endfunction
+
+
+endmodule
+
memory_sram.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property