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    /wf3d/trunk/implement/rtl
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Rev 2 → Rev 4

/fm_hvc/fm_hvc_data.v
9,7 → 9,7
// LCD output color data construction
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
75,7 → 75,11
input rst_x;
// sdram interface
input i_rstr;
`ifdef PP_BUSWIDTH_64
input [63:0] i_rd;
`else
input [31:0] i_rd;
`endif
// timing input
input i_h_active;
input i_first_line;
/fm_hvc/fm_cmn_ram.v
10,7 → 10,7
// with different clocks
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
39,46 → 39,6
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
//=======================================================================
// Project Polyphony
//
// File:
// fm_cmn_bram_02.v
//
// Abstract:
// Dualport RAM, this will be mapped onto block ram
// with different clocks
// Created:
// 5 November 2008
//======================================================================
//
// Copyright (c) 2013, Kenji Ishimaru
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// -Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// -Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
// $Date: 2014-12-09 16:38:37 +0900 (Tue, 09 Dec 2014) $
// $Rev: 14 $
 
module fm_cmn_ram (
clka,
/fm_hvc/fm_hvc.v
9,7 → 9,7
// VGA LCD Controller
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
38,6 → 38,7
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
// 2016/08/14 64-bit bus support
 
module fm_hvc (
clk_core,
46,13 → 47,9
// configuration registers
i_video_start,
i_fb0_offset,
i_fb0_ms_offset,
i_fb1_offset,
i_fb1_ms_offset,
i_color_mode,
i_front_buffer,
i_aa_en,
i_fb_blend_en,
// status out
o_vint_x,
o_vint_edge,
73,7 → 70,16
o_blank_x,
o_de
);
 
localparam P_IB_LEN_WIDTH = 'd6;
`ifdef PP_BUSWIDTH_64
localparam P_IB_BASE_WIDTH = 'd12;
localparam P_IB_ADDR_WIDTH = 'd29;
localparam P_IB_DATA_WIDTH = 'd64;
`else
localparam P_IB_BASE_WIDTH = 'd7;
localparam P_IB_ADDR_WIDTH = 'd24;
localparam P_IB_DATA_WIDTH = 'd32;
`endif
//////////////////////////////////
// I/O port definition
//////////////////////////////////
82,24 → 88,23
input rst_x;
// configuration registers
input i_video_start;
input [6:0] i_fb0_offset;
input [3:0] i_fb0_ms_offset;
input [6:0] i_fb1_offset;
input [3:0] i_fb1_ms_offset;
input [P_IB_BASE_WIDTH-1:0] i_fb0_offset;
input [P_IB_BASE_WIDTH-1:0] i_fb1_offset;
input [1:0] i_color_mode;
input i_front_buffer;
input [2:0] i_aa_en;
input i_fb_blend_en;
// status out
output o_vint_x;
output o_vint_edge;
// dram if
output o_req;
output [23:0] o_adrs;
output [5:0] o_len;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
output [P_IB_LEN_WIDTH-1:0]
o_len;
input i_ack;
input i_rstr;
input [31:0] i_rd;
input [P_IB_DATA_WIDTH-1:0]
i_rd;
 
output clk_vo;
output [7:0] o_r;
151,28 → 156,66
.o_de(o_de)
);
 
fm_hvc_dma fm_hvc_dma (
`ifdef PP_USE_AXI
`ifdef PP_BUSWIDTH_64
`else
wire w_req;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs;
wire [P_IB_LEN_WIDTH-1:0]
w_len;
wire w_ack;
fm_rd_split fm_rd_split (
.clk_core(clk_core),
.rst_x(rst_x),
.i_req(w_req),
.i_adrs(w_adrs),
.i_len(w_len),
.o_ack(w_ack),
// dram if
.o_req(o_req),
.o_adrs(o_adrs),
.o_len(o_len),
.i_ack(i_ack)
);
`endif
`endif
fm_hvc_dma #(.P_IB_ADDR_WIDTH(P_IB_ADDR_WIDTH),
.P_IB_LEN_WIDTH(P_IB_LEN_WIDTH))
fm_hvc_dma (
.clk_core(clk_core),
.rst_x(rst_x),
.i_color_mode(i_color_mode),
.i_video_start(i_video_start),
.i_vsync(w_vsync_i),
.i_hsync(w_hsync_i),
.i_fb0_offset(i_fb0_offset),
.i_fb0_ms_offset(i_fb0_ms_offset),
.i_fb1_offset(i_fb1_offset),
.i_fb1_ms_offset(i_fb1_ms_offset),
.i_front_buffer(i_front_buffer),
.i_aa_en(i_aa_en[0]),
.i_fifo_available(w_fifo_available),
.o_fifo_available_ack(w_fifo_available_ack),
.o_vsync(o_vint_x),
.o_vsync_edge(o_vint_edge),
// dram if
`ifdef PP_USE_AXI
`ifdef PP_BUSWIDTH_64
.o_req(o_req),
.o_adrs(o_adrs),
.o_len(o_len),
.i_ack(i_ack)
`else
.o_req(w_req),
.o_adrs(w_adrs),
.o_len(w_len),
.i_ack(w_ack)
`endif
`else
.o_req(o_req),
.o_adrs(o_adrs),
.o_len(o_len),
.i_ack(i_ack)
`endif
);
 
fm_hvc_data fm_hvc_data (
/fm_hvc/fm_hvc_dma.v
9,7 → 9,7
// VGA LCD Controller DMAC
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
47,11 → 47,8
i_vsync,
i_hsync,
i_fb0_offset,
i_fb0_ms_offset,
i_fb1_offset,
i_fb1_ms_offset,
i_front_buffer,
i_aa_en,
i_fifo_available,
o_fifo_available_ack,
o_vsync,
66,14 → 63,22
////////////////////////////
// Parameter definition
////////////////////////////
parameter P_IDLE = 3'd0;
parameter P_REQ = 3'd1;
parameter P_REQ_AA = 3'd2;
parameter P_WAIT_FIFO_AVL = 3'd3;
parameter P_WAIT_AVL_FALL = 3'd4;
parameter P_IB_ADDR_WIDTH ='d24;
parameter P_IB_LEN_WIDTH = 'd6;
 
parameter P_BURST_SIZE = 6'd32;
parameter P_BURST_SIZE_H = 6'd16;
localparam P_IDLE = 3'd0;
localparam P_REQ = 3'd1;
localparam P_REQ_AA = 3'd2;
localparam P_WAIT_FIFO_AVL = 3'd3;
localparam P_WAIT_AVL_FALL = 3'd4;
 
`ifdef PP_BUSWIDTH_64
localparam P_BURST_SIZE = 6'd16;
localparam P_BURST_SIZE_H = 6'd8;
`else
localparam P_BURST_SIZE = 6'd32;
localparam P_BURST_SIZE_H = 6'd16;
`endif
//////////////////////////////////
// I/O port definition
//////////////////////////////////
83,12 → 88,14
input i_video_start;
input i_vsync;
input i_hsync;
`ifdef PP_BUSWIDTH_64
input [11:0] i_fb0_offset;
input [11:0] i_fb1_offset;
`else
input [6:0] i_fb0_offset;
input [3:0] i_fb0_ms_offset;
input [6:0] i_fb1_offset;
input [3:0] i_fb1_ms_offset;
`endif
input i_front_buffer;
input i_aa_en;
input i_fifo_available;
output o_fifo_available_ack;
output o_vsync;
95,8 → 102,10
output o_vsync_edge;
// dram if
output o_req;
output [23:0] o_adrs;
output [5:0] o_len; // 32 burst x 10
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
output [P_IB_LEN_WIDTH-1:0]
o_len; // 32 burst x 10
input i_ack;
 
//////////////////////////////////
104,9 → 113,11
//////////////////////////////////
reg [2:0] r_state;
reg r_req;
// reg [13:0] r_cur_adrs_l;
`ifdef PP_BUSWIDTH_64
reg [13:0] r_cur_adrs_l;
`else
reg [12:0] r_cur_adrs_l;
 
`endif
reg [3:0] r_req_cnt;
// syncro register
reg r_vsync_1z;
131,10 → 142,14
wire w_line_end;
wire w_req_cnt_clear;
 
`ifdef PP_BUSWIDTH_64
wire [11:0] w_fb_offset;
wire [11:0] w_offset;
`else
wire [6:0] w_fb_offset;
wire [6:0] w_fb_ms_offset;
wire [6:0] w_offset;
wire w_hburst;
`endif
wire w_hburst;
//////////////////////////////////
// assign
//////////////////////////////////
144,25 → 159,26
assign o_fifo_available_ack = r_fifo_available_ack;
 
assign w_set_initial_adrs = w_v_rise;
assign w_adrs_inc = (i_aa_en) ? (r_state == P_REQ_AA) & i_ack:
(r_state == P_REQ) & i_ack;
assign w_adrs_inc = (r_state == P_REQ) & i_ack;
 
assign w_h_start = i_video_start & r_hsync_2z & !r_hsync_3z; // rise of hsync
assign w_v_rise = r_vsync_2z & !r_vsync_3z; // rising edge of vsync
assign w_line_end = (i_color_mode == 2'd3) ? (r_req_cnt == 4'd3) :// 80 times:
(i_color_mode == 2'd2) ? (r_req_cnt == 4'd5) :// 160 times
(r_req_cnt == 4'd10); // 320 times
 
assign w_line_end = (i_color_mode == 2'd3) ? (r_req_cnt == 4'd3) :// 80 times, 32burstx2, 16burstx1
(i_color_mode == 2'd2) ? (r_req_cnt == 4'd5) :// 160 times, 32burstx5
(r_req_cnt == 4'd10); // 320 times, 32burstx10
// 80 times, 16burstx2, 8burstx1 (64)
assign w_req_cnt_clear = (w_line_end & !r_fifo_available_2z &
(r_state == P_WAIT_AVL_FALL)) |
(w_line_end & (r_state == P_WAIT_FIFO_AVL) & (i_color_mode == 'd3));
(r_state == P_WAIT_AVL_FALL)) |
(w_line_end & (r_state == P_WAIT_FIFO_AVL) & (i_color_mode == 'd3));
 
// assign o_adrs = {w_offset, r_cur_adrs_l,4'b0}; // w_offset[21:18]
assign o_adrs = {w_offset,r_cur_adrs_l,4'b0}; // w_offset[23:17]
`ifdef PP_BUSWIDTH_64
assign o_adrs = {w_offset, r_cur_adrs_l,3'b0};
`else
assign o_adrs = {w_offset, r_cur_adrs_l,4'b0};
`endif
 
assign w_fb_offset = (i_front_buffer) ? i_fb1_offset : i_fb0_offset;
assign w_fb_ms_offset = (i_front_buffer) ? i_fb1_ms_offset : i_fb0_ms_offset;
assign w_offset = (r_state == P_REQ_AA) ? w_fb_ms_offset : w_fb_offset;
assign w_offset = w_fb_offset;
 
assign o_vsync = r_vsync_2z;
assign o_vsync_edge = !r_vsync_2z & r_vsync_3z; // falling edge
186,26 → 202,15
end
P_REQ: begin
if (i_ack) begin
if (i_aa_en) begin
r_req <= 1'b1;
r_state <= P_REQ_AA;
end else begin
r_req <= 1'b0;
r_state <= P_WAIT_FIFO_AVL;
end
r_req <= 1'b0;
r_state <= P_WAIT_FIFO_AVL;
end
end
P_REQ_AA: begin
if (i_ack) begin
r_req <= 1'b0;
r_state <= P_WAIT_FIFO_AVL;
end
end
P_WAIT_FIFO_AVL: begin
if (r_req_cnt < 4'd4) begin
if (w_line_end) begin
if (w_line_end) begin
r_state <= P_IDLE;
end else begin
end else begin
r_req <= 1'b1;
r_state <= P_REQ;
end
234,14 → 239,14
// current address
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_cur_adrs_l <= 13'h0; // for simulation
r_cur_adrs_l <= 'h0; // for simulation
end else begin
if (w_set_initial_adrs) begin
r_cur_adrs_l <= 13'h0;
r_cur_adrs_l <= 'h0;
end else if (w_adrs_inc) begin
if (w_hburst)
r_cur_adrs_l <= r_cur_adrs_l + 1'b1; // same as + 16
else
else
r_cur_adrs_l <= r_cur_adrs_l + 2'b10; // same as + 32
end
end
/fm_hvc/fm_afifo.v
9,7 → 9,7
// Asynchronus FIFO
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
56,6 → 56,11
// set default parameters
parameter P_RANGE = 7;
parameter P_DEPTH = 1 << P_RANGE; // 128
`ifdef PP_BUSWIDTH_64
localparam P_IB_DATA_WIDTH = 'd64;
`else
localparam P_IB_DATA_WIDTH = 'd32;
`endif
////////////////////////////
// I/O definition
////////////////////////////
64,7 → 69,8
input rst_x; // system reset
input [1:0] i_color_mode;
input i_wstrobe; // write strobe
input [31:0] i_dt; // write data
input [P_IB_DATA_WIDTH-1:0]
i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [15:0] o_dt; // read data
77,7 → 83,11
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
// data registers
`ifdef PP_BUSWIDTH_64
reg [3:0] r_select_hw;
`else
reg [2:0] r_select_hw;
`endif
/////////////////////////
// wire definition
/////////////////////////
86,7 → 96,8
wire [15:0] o_dt;
wire w_we;
wire w_re;
wire [31:0] w_dt32;
wire [P_IB_DATA_WIDTH-1:0]
w_dt;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
wire [15:0] w_dt16;
95,21 → 106,63
// /////////////////////////
// assign statement
/////////////////////////
assign w_dt16 = (r_select_hw[0]) ? w_dt32[31:16] : w_dt32[15:0];
assign w_dt8 = (r_select_hw[1:0] == 'd3) ? w_dt32[31:24] :
(r_select_hw[1:0] == 'd2) ? w_dt32[23:16] :
(r_select_hw[1:0] == 'd1) ? w_dt32[15:8] :
w_dt32[7:0];
`ifdef PP_BUSWIDTH_64
assign w_dt16 = (r_select_hw[1:0] == 'd3) ? w_dt[63:48] :
(r_select_hw[1:0] == 'd2) ? w_dt[47:32] :
(r_select_hw[1:0] == 'd1) ? w_dt[31:16] :
w_dt[15:0];
 
assign w_dt8 = (r_select_hw[2:0] == 'd7) ? w_dt[63:56] :
(r_select_hw[2:0] == 'd6) ? w_dt[55:48] :
(r_select_hw[2:0] == 'd5) ? w_dt[47:40] :
(r_select_hw[2:0] == 'd4) ? w_dt[39:32] :
(r_select_hw[2:0] == 'd3) ? w_dt[31:24] :
(r_select_hw[2:0] == 'd2) ? w_dt[23:16] :
(r_select_hw[2:0] == 'd1) ? w_dt[15:8] :
w_dt[7:0];
 
assign w_dt4 = (r_select_hw[3:0] == 'd15) ? w_dt[63:60] :
(r_select_hw[3:0] == 'd14) ? w_dt[59:56] :
(r_select_hw[3:0] == 'd13) ? w_dt[55:52] :
(r_select_hw[3:0] == 'd12) ? w_dt[51:48] :
(r_select_hw[3:0] == 'd11) ? w_dt[47:44] :
(r_select_hw[3:0] == 'd10) ? w_dt[43:40] :
(r_select_hw[3:0] == 'd9) ? w_dt[39:36] :
(r_select_hw[3:0] == 'd8) ? w_dt[35:32] :
(r_select_hw[3:0] == 'd7) ? w_dt[31:28] :
(r_select_hw[3:0] == 'd6) ? w_dt[27:24] :
(r_select_hw[3:0] == 'd5) ? w_dt[23:20] :
(r_select_hw[3:0] == 'd4) ? w_dt[19:16] :
(r_select_hw[3:0] == 'd3) ? w_dt[15:12] :
(r_select_hw[3:0] == 'd2) ? w_dt[11:8] :
(r_select_hw[3:0] == 'd1) ? w_dt[7:4] :
w_dt[3:0];
 
assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw[3:0] == 'd15) :
(i_color_mode == 'd2) ? (r_select_hw[2:0] == 'd7) :
(r_select_hw[1:0] == 'd3)
);
`else
assign w_dt16 = (r_select_hw[0]) ? w_dt[31:16] : w_dt[15:0];
assign w_dt8 = (r_select_hw[1:0] == 'd3) ? w_dt[31:24] :
(r_select_hw[1:0] == 'd2) ? w_dt[23:16] :
(r_select_hw[1:0] == 'd1) ? w_dt[15:8] :
w_dt[7:0];
assign w_dt4 = (r_select_hw[2:0] == 'd7) ? w_dt32[31:28] :
(r_select_hw[2:0] == 'd6) ? w_dt32[27:24] :
(r_select_hw[2:0] == 'd5) ? w_dt32[23:20] :
(r_select_hw[2:0] == 'd4) ? w_dt32[19:16] :
(r_select_hw[2:0] == 'd3) ? w_dt32[15:12] :
(r_select_hw[2:0] == 'd2) ? w_dt32[11:8] :
(r_select_hw[2:0] == 'd1) ? w_dt32[7:4] :
w_dt32[3:0];
assign w_dt4 = (r_select_hw[2:0] == 'd7) ? w_dt[31:28] :
(r_select_hw[2:0] == 'd6) ? w_dt[27:24] :
(r_select_hw[2:0] == 'd5) ? w_dt[23:20] :
(r_select_hw[2:0] == 'd4) ? w_dt[19:16] :
(r_select_hw[2:0] == 'd3) ? w_dt[15:12] :
(r_select_hw[2:0] == 'd2) ? w_dt[11:8] :
(r_select_hw[2:0] == 'd1) ? w_dt[7:4] :
w_dt[3:0];
 
assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw == 'd7) :
(i_color_mode == 'd2) ? (r_select_hw[1:0] == 'd3) :
(r_select_hw[0] == 'd1)
);
`endif
assign o_dt = (i_color_mode == 'd3) ? {12'd0,w_dt4} :
(i_color_mode == 'd2) ? {8'd0,w_dt8} :
w_dt16 ;
117,10 → 170,6
assign o_full = 1'b0;
assign o_empty = 1'b0;
assign w_we = i_wstrobe;
assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw == 'd7) :
(i_color_mode == 'd2) ? (r_select_hw[1:0] == 'd3) :
(r_select_hw[0] == 'd1)
);
assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
 
152,7 → 201,7
// select half word
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_select_hw <= 3'b0;
r_select_hw <= 'd0;
end else begin
if (i_renable) r_select_hw <= r_select_hw + 1'b1;
end
161,7 → 210,11
///////////////////
// module instance
///////////////////
`ifdef PP_BUSWIDTH_64
fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(64),.P_RANGE( P_RANGE)) ram_00 (
`else
fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(32),.P_RANGE( P_RANGE)) ram_00 (
`endif
.clka(clk_core),
.clkb(clk_vi),
.wea(w_we),
169,7 → 222,7
.addrb(w_read_counter),
.dia(i_dt),
.doa(),
.dob(w_dt32)
.dob(w_dt)
);
 
endmodule
/fm_hvc/fm_hvc_core.v
9,7 → 9,7
// HV counter core
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
185,9 → 185,7
// V counter
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
// r_vcnt <= 10'd0;
// r_vcnt <= 10'd36; // this is only for faster simulatin
r_vcnt <= 10'd9; // this is only for faster simulatin (v rise)
r_vcnt <= 10'd9; // this is for faster simulatin (v rise)
end else begin
if (w_v_end) r_vcnt <= 10'd0;
else if (w_h_end) r_vcnt <= r_vcnt + 1'b1;
/de0/d3d_top.v
9,7 → 9,7
// DE0 RTL top module
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
/de0/fm_vga_wrapper.v
9,7 → 9,7
// AVALON VGA Master
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
160,13 → 160,9
// configuration registers
.i_video_start(w_video_start),
.i_fb0_offset(w_fb0_offset),
.i_fb0_ms_offset(4'h0),
.i_fb1_offset(w_fb1_offset),
.i_fb1_ms_offset(4'h0),
.i_color_mode(w_color_mode),
.i_front_buffer(w_front_buffer),
.i_aa_en('d0),
.i_fb_blend_en(1'b0),
// status out
.o_vint_x(w_vint_x),
.o_vint_edge(w_vint_edge),
/de0/fm_avalon.v
9,7 → 9,7
// Monophony core top module AVALON version
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
/de0/fm_3d_wrapper.v
9,7 → 9,7
// AVALON interface
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
/de0/fm_hsys.v
9,7 → 9,7
// System register module
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//
/de0/fm_avalon_wb.v
6,10 → 6,10
// fm_avalon_wb.v
//
// Abstract:
// AVALON-WISHBOBE bus bridge
// AVALON-WISHBONE bus bridge
//
// Author:
// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
// Kenji Ishimaru (info.wf3d@gmail.com)
//
//======================================================================
//

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