URL
https://opencores.org/ocsvn/wisbone_2_ahb/wisbone_2_ahb/trunk
Subversion Repositories wisbone_2_ahb
Compare Revisions
- This comparison shows the changes necessary to convert path
/wisbone_2_ahb/tags/t3/svtb
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/avm_svtb/wb_ahb_responder.svh
0,0 → 1,173
//****************************************************************************************************** |
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd. |
|
|
//File name : wb_ahb_responder.svh |
//Designer : Ravi S Gupta |
//Date : 4 Sept, 2007 |
//Description : Response from AHB to the Inputs from Wishbone |
//Revision : 1.0 |
|
//****************************************************************************************************** |
|
|
// responder class |
import avm_pkg::*; |
import global::*; |
class wb_ahb_responder extends avm_threaded_component; |
|
int cnt; |
// local memory in AHB slave model |
logic [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0]; |
|
logic [AWIDTH-1:0] haddr_temp; |
logic [DWIDTH-1 :0] hrdata_temp; |
logic hwrite_temp; |
|
virtual wb_ahb_if pin_if; |
|
function new(string name ,avm_named_component parent); |
super.new(name,parent); |
pin_if =null; |
endfunction |
|
// task to sample address |
task samp_addr; |
forever |
begin |
@(posedge pin_if.master_wb.clk_i); |
if(pin_if.master_wb.rst_i) |
begin |
pin_if.slave_ba.hready='b0; |
pin_if.slave_ba.hwdata='bx; |
pin_if.slave_ba.hresp='b00; |
|
end |
else if(!pin_if.slave_ba.hwrite) |
begin |
pin_if.slave_ba.hrdata= #2 pin_if.slave_ba.haddr+1; |
end |
end |
endtask |
|
|
task response; |
forever |
begin |
@(posedge pin_if.master_wb.clk_i); |
end |
endtask |
|
//***************************************** |
//Write operations with no wait states |
//***************************************** |
task wait_state_by_slave; |
pin_if.slave_ba.hready='b1; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
cnt++; |
end |
while (cnt <= 9);//Write operations with no wait states for 10 clk cycles |
//************************************************ |
//Write operations with wait states from AHB Slave |
//************************************************ |
#2 pin_if.slave_ba.hready='b0; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
++cnt; |
end |
while (cnt <= 4);// 5 clock cycle asserted AHB Master is in Wait State |
//***************************************** |
//Write operations with no wait states |
//***************************************** |
#2 pin_if.slave_ba.hready='b1; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
cnt++; |
end |
while (cnt <= 4);//Write operations with no wait states for 5 clk cycles |
//*********************************************** |
//Write operations with wait states from WB Master |
//*********************************************** |
#2 pin_if.slave_ba.hready='b1; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
++cnt; |
end |
while (cnt <= 4);// 5 clock cycle deasserted WB Master is in Wait State |
//***************************************** |
//Write operations with no wait states |
//***************************************** |
#2 pin_if.slave_ba.hready='b1; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
cnt++; |
end |
while (cnt <= 4);//Write operations with no wait states for 5 clk cycles |
|
//************************************* |
//Read operations without wait states |
//************************************* |
#2 pin_if.slave_ba.hready='b1; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
cnt++; |
end |
while (cnt <= 9);// Read operations with no wait states for 10 clk cycles |
|
//********************************************** |
//Read operations with wait states from AHB Slave |
//********************************************** |
#2 pin_if.slave_ba.hready='b0; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
++cnt; |
end |
while (cnt <= 9);// 10 clock cycle asserted AHB Master is in Wait State |
|
//************************************* |
//Read operations without wait states |
//************************************* |
#2 pin_if.slave_ba.hready='b1; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
cnt++; |
end |
while (cnt <= 9);// Read operations with no wait states for 10 clk cycles |
//********************************************** |
//Read operations with wait states from WB Master |
//********************************************** |
#2 pin_if.slave_ba.hready='b1; |
cnt=0; |
do |
begin |
@(posedge pin_if.master_wb.clk_i); |
++cnt; |
end |
while (cnt <= 9);// 10 clock cycle asserted WB Master in in Wait state |
|
endtask |
// run all task |
task run; |
fork |
samp_addr; |
response; |
join |
endtask |
|
endclass |
avm_svtb/wb_ahb_responder.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_master.sv
===================================================================
--- avm_svtb/wb_ahb_master.sv (nonexistent)
+++ avm_svtb/wb_ahb_master.sv (revision 11)
@@ -0,0 +1,61 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_master.sv
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Master for initializing values during Reset State of Device
+//Revision : 1.0
+
+//******************************************************************************************************
+
+`timescale 1 ns/1 ps
+
+import global::*;
+module stimulus_gen( wb_ahb_if.master_wb m_wb,
+ input bit clk,
+ input bit reset);
+
+//******************************************
+// assign input clk and reset to stimulus gen
+//******************************************
+
+ assign m_wb.clk_i = clk;
+ assign m_wb.rst_i = reset;
+
+//*****************************************
+// Values of various signals at Reset State of the Device
+//*****************************************
+always @(posedge m_wb.clk_i)
+ if (m_wb.rst_i)
+ begin
+ m_wb.cyc_i='bx;
+ m_wb.stb_i='bx;
+ m_wb.sel_i='bx;
+ m_wb.addr_i='bx;
+ m_wb.data_i='bx;
+ end
+
+//******************************************
+// initial signal setups
+//******************************************
+task initial_setup;
+ begin
+ @(posedge m_wb.clk_i);
+ # 2 m_wb.cyc_i='b0;
+ m_wb.stb_i='b0;
+ m_wb.sel_i='b0;
+ m_wb.we_i='bx;
+ m_wb.addr_i='bx;
+ m_wb.data_i='bx;
+ # 20 m_wb.cyc_i='b1;
+ m_wb.stb_i='b1;
+ m_wb.sel_i='b0;
+ m_wb.we_i='b1;//Write operation
+ end
+endtask
+
+endmodule
+
+
avm_svtb/wb_ahb_master.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_scoreboard.svh
===================================================================
--- avm_svtb/wb_ahb_scoreboard.svh (nonexistent)
+++ avm_svtb/wb_ahb_scoreboard.svh (revision 11)
@@ -0,0 +1,138 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_scoreboard.svh
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Stimulus Generation for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// scoreboard class
+import avm_pkg::*;
+import global::*;
+
+class wb_ahb_scoreboard extends avm_threaded_component;
+
+analysis_fifo#(monitor_pkt) ap_fifo; // analysis port fifo
+analysis_if#(monitor_pkt) ap_if; // analysis port interface
+// local variables
+
+logic [AWIDTH-1:0]adr1; //WB ADDR
+logic [DWIDTH-1:0]dat1; //WB DATA
+logic [AWIDTH-1:0]adr2; //AHB ADDR
+logic [DWIDTH-1:0]dat2; //WB DATA
+
+// monitor packet
+monitor_pkt m_pkt;
+
+virtual ahb_wb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ ap_fifo =new("ap_fifo",this);
+ ap_if =null;
+ pin_if =null;
+ endfunction
+
+// connecting analysis fifo to the analysis interface
+function void export_connections();
+ ap_if = ap_fifo.analysis_export;
+endfunction
+
+task run;
+forever
+ begin
+ ap_fifo.get(m_pkt);
+ if(m_pkt.stb && m_pkt.ack) //No wait state
+ if(m_pkt.wr) //write mode
+ if(m_pkt.flag1) // first clock comparison only between addresses
+ begin
+ adr1=m_pkt.adr1;
+ dat1=m_pkt.dat1;
+ adr2=m_pkt.adr2;
+ if(m_pkt.flag2) // first clock after after wait state
+ begin
+ if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2))|| (( m_pkt.adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === dat2)));
+
+ //avm_report_message("Scoreboard: Write Passed","after wait state");
+ else
+ avm_report_warning("Scoreboard: Error in write after wait state",display_pkt(m_pkt));
+ adr1=m_pkt.adr1; // Holding the previous WB address
+ dat1=m_pkt.dat1; // Holding the previous WB data
+ adr2=m_pkt.adr2; // Holding the previous AHB Addr
+
+ end
+ else
+ begin
+ if(( m_pkt.adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === dat2));
+ //avm_report_message("Scoreboard: Write Passed","without wait state");
+ else
+ avm_report_warning("Scoreboard: Error in write without wait state",display_pkt(m_pkt));
+ end
+ end
+ else //READ Mode
+ if(m_pkt.flag1) // first clock comaprison between addresses
+ begin
+ adr1=m_pkt.adr1;// Holding the previous WB address
+ adr2=m_pkt.adr2;// Holding the previous AHB Addr
+ if(m_pkt.flag2) // first clock after after wait state
+ begin
+ if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2))|| (( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)));
+ //avm_report_message("Scoreboard: Read Passed","after wait state");
+ else
+
+ avm_report_warning("Scoreboard: Error in read after wait state",display_pkt(m_pkt));
+ adr1=m_pkt.adr1;
+ adr2=m_pkt.adr2;
+ end
+ else
+ begin
+ if(( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)); // comparing unknown values too
+ //avm_report_message("Scoreboard: Read Passed","without wait state");
+ else
+ avm_report_warning("Scoreboard: Error in read without wait state",display_pkt(m_pkt));
+ adr1=m_pkt.adr1;
+ adr2=m_pkt.adr2;
+ end
+ end
+ else // wait state by slave or master
+ begin
+ if(m_pkt.flag2) // latch the value
+ begin
+ adr1=m_pkt.adr1;
+ dat1=m_pkt.dat1;
+ adr2=m_pkt.adr2;
+ dat2=m_pkt.dat2;
+ end
+ else
+ begin
+ if(( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2));
+ //avm_report_message("Scoreboard: Passed","with wait state");
+ else
+ avm_report_warning("Scoreboard: Error in with wait state",display_pkt(m_pkt));
+ end
+ end
+
+ end
+endtask
+
+
+// function to display values at any instant
+function string display_pkt(input monitor_pkt m);
+ string s;
+ $sformat(s,"current_adr1=%0d,adr1=%0d,adr2=%0d,dat1=%0d,dat2=%0d,wr=%0b,stb=%0b,f1=%b,f2=%b",adr1,m.adr1,m.adr2,m.dat1,m.dat2,m.wr,m.stb,m.flag1,m.flag2);
+ return s;
+endfunction
+
+
+endclass
+
+
+
+
+
+
+
avm_svtb/wb_ahb_scoreboard.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_stim_gen.svh
===================================================================
--- avm_svtb/wb_ahb_stim_gen.svh (nonexistent)
+++ avm_svtb/wb_ahb_stim_gen.svh (revision 11)
@@ -0,0 +1,156 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_stim_gen.svh
+//Designaer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Stimulus Generation for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// class to generate write and read packet
+import avm_pkg::*;
+import global::*;
+class wb_ahb_stim_gen extends avm_named_component;
+
+
+avm_blocking_put_port#( wb_req_pkt) initiator_port;
+tlm_fifo#(wb_req_pkt) fifo;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ initiator_port=new("initiatot_port",this);
+ fifo =new("fifo",this);
+ endfunction
+
+task stimulus(input int count = 41);
+
+ wb_req_pkt p;
+//*****************************************
+//Write operations with no wait states
+//*****************************************
+ for(int i=0; i<11 ;i++)
+ begin
+ p.wr='b1;
+ p.adr=i+1;
+ p.dat=i;
+ p.stb='b1;
+ write_to_pipe(p);
+ end
+
+//************************************************
+//Write operations with wait states from AHB Slave
+//************************************************
+ for(int i=10;i<16;i++)
+ begin
+ p.wr='b1;//Wait state from AHB SLAVE
+ p.stb='b1;
+ write_to_pipe(p);
+ end
+
+//*****************************************
+//Write operations with no wait states
+//*****************************************
+ for(int i=15; i<21 ;i++)
+ begin
+ p.wr='b1;
+ p.adr=i+1;
+ p.dat=i;
+ p.stb='b1;
+ write_to_pipe(p);
+ end
+
+//***********************************************
+//Write operations with wait states from WB Master
+//***********************************************
+ for(int i=20;i<26;i++)
+ begin
+ p.stb='b0;
+ p.wr='b1;//Wait state from AHB SLAVE
+ write_to_pipe(p);
+ end
+
+//*****************************************
+//Write operations with no wait states
+//*****************************************
+ for(int i=25; i<31 ;i++)
+ begin
+ p.wr='b1;
+ p.adr=i+1;
+ p.dat=i;
+ p.stb='b1;
+ write_to_pipe(p);
+ end
+
+//*************************************
+//Read operations without wait states
+//*************************************
+ for(int i=30; i<41 ;i++)
+ begin
+
+ p.wr='b0;
+ p.adr=i+1;
+ p.stb='b1;
+ write_to_pipe(p);
+ end
+
+//**********************************************
+//Read operations with wait states from AHB Slave
+//**********************************************
+ for(int i=40; i<51 ;i++)
+ begin
+ p.wr='b0;
+ p.stb='b1;
+ write_to_pipe(p);
+ end
+//*************************************
+//Read operations without wait states
+//*************************************
+ for(int i=50; i<61 ;i++)
+ begin
+ p.wr='b0;
+ p.stb='b1;
+ p.adr=i+1;
+ write_to_pipe(p);
+ end
+//**********************************************
+//Read operations with wait states from WB Master
+//**********************************************
+ for(int i=60; i<71 ;i++)
+ begin
+ p.wr='b0;
+ p.stb='b0;
+ write_to_pipe(p);
+ end
+//*************************************
+//Read operations without wait states
+//*************************************
+ for(int i=70; i<81 ;i++)
+ begin
+ p.wr='b0;
+ p.stb='b1;
+ p.adr=i+1;
+ write_to_pipe(p);
+ end
+//*****************************************
+//Write operations with no wait states
+//*****************************************
+ for(int i=80; i<91 ;i++)
+ begin
+ p.wr='b1;
+ p.stb='b1;
+ p.adr=i+1;
+ p.dat=i;
+ write_to_pipe(p);
+ end
+
+endtask
+
+// task to push transaction in the fifo
+task write_to_pipe(wb_req_pkt p);
+ initiator_port.put(p);
+endtask
+
+endclass
avm_svtb/wb_ahb_stim_gen.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/global.sv
===================================================================
--- avm_svtb/global.sv (nonexistent)
+++ avm_svtb/global.sv (revision 11)
@@ -0,0 +1,46 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : global.sv
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Gloabl Declaration for WISHBONE_AHB Bridge used within Driver, Stimulus Generator and Monitor
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// package decleration
+package global;
+
+parameter int DWIDTH =32;
+parameter int AWIDTH =32;
+parameter int cyc_prd = 10;
+
+typedef struct {
+ rand logic [AWIDTH-1:0]adr;
+ rand logic [DWIDTH-1:0]dat;
+ logic wr; // write
+ logic stb;
+} wb_req_pkt;
+
+typedef struct {
+ rand logic [DWIDTH-1:0]dat;
+ logic rdy;// hready
+ logic trans;//htrans
+} wb_res_pkt;
+
+typedef struct {
+ bit flag1;//read/write
+ bit flag2;//ack
+ logic wr; //write signal
+ logic stb;//strobe for wait from master
+ logic ack;//ack for wait state from slave
+ logic [AWIDTH-1:0]adr1;
+ logic [AWIDTH-1:0]adr2;
+ logic [DWIDTH-1:0]dat1;
+ logic [DWIDTH-1:0]dat2;
+} monitor_pkt;
+
+
+endpackage
avm_svtb/global.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_monitor.svh
===================================================================
--- avm_svtb/wb_ahb_monitor.svh (nonexistent)
+++ avm_svtb/wb_ahb_monitor.svh (revision 11)
@@ -0,0 +1,186 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_monitor.svh
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Monitor for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// monitor class
+import avm_pkg::*;
+import global::*;
+class wb_ahb_monitor extends avm_threaded_component;
+
+avm_analysis_port#(monitor_pkt) ap_sb; // analysis port for Score board
+monitor_pkt m_pkt; // instance of packet
+
+local bit flag1;
+local bit flag2;
+
+virtual wb_ahb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ ap_sb = new("ap_sb",this);
+ pin_if =null;
+ endfunction
+// task to monitor event on read/write signal
+task rdwr;
+ forever
+ begin
+ @(pin_if.monitor.we_i);
+ flag1='b1;
+ end
+endtask
+// task to monitor event on ack_o or stb_i (wait state)
+task wait_ms;
+ forever
+ begin
+ @(pin_if.monitor.stb_i or pin_if.monitor.ack_o);
+ flag2='b1;
+ end
+endtask
+
+task main_run;
+ forever
+ begin
+ @(posedge pin_if.monitor.clk_i);
+ if(pin_if.monitor.stb_i)//No wait state
+ begin
+ if(pin_if.monitor.we_i) //write mode
+ begin
+ if(flag1) // first clock
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;// Get WB addr and Data along with AHB addr
+ m_pkt.dat1=pin_if.monitor.data_i;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.wr='b1;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag1='b1;
+ // write packet to scoreboard
+ ap_sb.write(m_pkt);
+ flag1='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;
+ m_pkt.dat1=pin_if.monitor.data_i;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.dat2=pin_if.monitor.hwdata;
+ m_pkt.wr='b1;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag1='b0;
+ m_pkt.flag2=flag2;
+ ap_sb.write(m_pkt);
+ end
+ end
+ else// read mode
+ begin
+ if(flag1) // first clock
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;//Get addr from both WB and AHB
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.wr='b0;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag1='b1;
+ //write packet to scoreboard
+ ap_sb.write(m_pkt);
+ flag1='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;
+ m_pkt.dat1=pin_if.monitor.data_o;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.dat2=pin_if.monitor.hrdata;
+ m_pkt.wr='b0;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag1='b0;
+ m_pkt.flag2=flag2;
+ // write packet to scoreboard
+ ap_sb.write(m_pkt);
+ end
+ end
+ end
+ else // wait state by slave or master
+ begin
+ if(pin_if.monitor.we_i) // write mode
+ begin
+ if(flag2) // latch the value
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;
+ m_pkt.dat1=pin_if.monitor.data_i;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.dat2=pin_if.monitor.hwdata;
+ m_pkt.wr='b1;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag2='b1;
+ ap_sb.write(m_pkt);
+ flag2='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;
+ m_pkt.dat1=pin_if.monitor.data_i;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.dat2=pin_if.monitor.hwdata;
+ m_pkt.wr='b1;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag2='b0;
+ ap_sb.write(m_pkt);
+ end
+ end
+ else
+ begin
+ if(flag2) // latch the value
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;
+ m_pkt.dat1=pin_if.monitor.data_o;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.dat2=pin_if.monitor.hrdata;
+ m_pkt.wr='b0;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag2='b1;
+ ap_sb.write(m_pkt);
+ flag2='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.addr_i;
+ m_pkt.dat1=pin_if.monitor.data_o;
+ m_pkt.adr2=pin_if.monitor.haddr;
+ m_pkt.dat2=pin_if.monitor.hrdata;
+ m_pkt.wr='b0;
+ m_pkt.stb=pin_if.monitor.stb_i;
+ m_pkt.ack=pin_if.monitor.ack_o;
+ m_pkt.flag2='b0;
+ ap_sb.write(m_pkt);
+ end
+ end
+ end
+ end
+endtask
+
+// run all task simultaneously
+task run;
+ fork
+ rdwr();
+ wait_ms();
+ main_run();
+ join
+endtask
+
+endclass
+
+
avm_svtb/wb_ahb_monitor.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_env.svh
===================================================================
--- avm_svtb/wb_ahb_env.svh (nonexistent)
+++ avm_svtb/wb_ahb_env.svh (revision 11)
@@ -0,0 +1,72 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_env.svh
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Environment for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// env class
+import avm_pkg::*;
+import wb_ahb_pkg::*;
+import global::*;
+
+class wb_ahb_env extends avm_env;
+
+virtual wb_ahb_if pin_if;// interface
+
+// operational components
+wb_ahb_stim_gen stim_gen;
+wb_ahb_driver driver;
+wb_ahb_responder responder;
+
+// analysis components
+wb_ahb_monitor monitor;
+wb_ahb_coverage coverage;
+wb_ahb_scoreboard scoreboard;
+
+tlm_fifo #(wb_req_pkt) fifo;
+
+avm_analysis_port#(monitor_pkt) e_ap;
+
+ function new (virtual wb_ahb_if pin);
+ stim_gen =new("stim_gen",this);
+ driver =new("driver",this);
+ responder =new("responder",this);
+ monitor =new("monitor",this);
+ coverage =new("coverage", this);
+ scoreboard =new("scoreboard", this);
+ fifo =new("fifo",this);
+ e_ap =new("e_ap",this);
+ pin_if =pin;
+ monitor.ap_sb =e_ap;
+
+ endfunction
+
+ function void connect();
+ stim_gen.initiator_port.connect(fifo.blocking_put_export);
+ driver.request_port.connect(fifo.nonblocking_get_export);
+ monitor.ap_sb.register(scoreboard.ap_if);
+ monitor.ap_sb.register(coverage.ap_if);
+ endfunction
+
+ function void import_connections();
+ driver.pin_if = pin_if;
+ responder.pin_if = pin_if;
+ monitor.pin_if = pin_if;
+ endfunction
+
+ task run;
+ fork
+ stim_gen.stimulus();
+ responder.wait_state_by_slave();
+ #700;
+ join
+ endtask
+
+endclass
+
avm_svtb/wb_ahb_env.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_interface.sv
===================================================================
--- avm_svtb/wb_ahb_interface.sv (nonexistent)
+++ avm_svtb/wb_ahb_interface.sv (revision 11)
@@ -0,0 +1,110 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_interface.sv
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Interface for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+`timescale 1 ns/ 1 ps
+import global::*;
+interface wb_ahb_if;
+//master to bridge
+ logic clk_i;
+ logic rst_i;
+ logic [DWIDTH-1:0]data_i;
+ logic [AWIDTH-1:0]addr_i;
+ logic ack_o;
+ logic cyc_i;
+ logic stb_i;
+ logic we_i;
+ logic [DWIDTH-1:0]data_o;
+ logic [3:0] sel_i;
+//bridge to slave
+ logic hclk;
+ logic hresetn;
+ logic hwrite;
+ logic [AWIDTH-1:0]haddr;
+ logic [DWIDTH-1:0]hwdata;
+ logic [2:0]hburst;
+ logic [2:0]hsize;
+ logic [1:0]htrans;
+ logic [1:0]hresp;
+ logic hready;
+ logic [DWIDTH-1:0]hrdata;
+modport master_wb ( output clk_i,
+ output rst_i,
+ output data_i,
+ output addr_i,
+ output cyc_i,
+ output stb_i,
+ output we_i,
+ output sel_i,
+ input data_o,
+ input ack_o
+ );
+modport slave_wb(input clk_i,
+ input rst_i,
+ input data_i,
+ input addr_i,
+ input cyc_i,
+ input stb_i,
+ input we_i,
+ input sel_i,
+ output data_o,
+ output ack_o
+ );
+modport master_ba(input hclk,
+ input hresetn,
+ input hwrite,
+ input haddr,
+ input hwdata,
+ input hburst,
+ input hsize,
+ input htrans,
+ output hready,
+ output hresp,
+ output hrdata
+ );
+modport slave_ba(input hready,
+ input hresp,
+ input hrdata,
+ output hclk,
+ output hresetn,
+ output hwrite,
+ output haddr,
+ output hwdata,
+ output hburst,
+ output hsize,
+ output htrans
+ );
+modport monitor(
+// signals from master to bridge
+ input clk_i,
+ input rst_i,
+ input data_i,
+ input addr_i,
+ input ack_o,
+ input cyc_i,
+ input stb_i,
+ input we_i,
+ input data_o,
+ input sel_i,
+// signals from bridge to slave
+ input hclk,
+ input hresetn,
+ input hwrite,
+ input haddr,
+ input hwdata,
+ input hburst,
+ input hsize,
+ input htrans,
+ input hresp,
+ input hready,
+ input hrdata
+ );
+endinterface
avm_svtb/wb_ahb_interface.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_top.sv
===================================================================
--- avm_svtb/wb_ahb_top.sv (nonexistent)
+++ avm_svtb/wb_ahb_top.sv (revision 11)
@@ -0,0 +1,68 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_top.svh
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Top for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+
+// top module
+`include "../../src/ahbmas_wbslv_top.v"
+
+import wb_ahb_pkg::*;
+import global::*;
+
+module wb_ahb_top;
+
+logic clk ='b0;
+logic reset ='b0;
+
+ wb_ahb_if inf1(); // interface instance from wb to bridge
+ stimulus_gen TB_M(inf1.master_wb,clk,reset); // WB master instance
+
+ AHBMAS_WBSLV_TOP DUT ( // interface connection from WB(stimulus gen) to bridge
+ .clk_i(inf1.slave_wb.clk_i),
+ .rst_i(inf1.slave_wb.rst_i),
+ .data_i(inf1.slave_wb.data_i),
+ .addr_i(inf1.slave_wb.addr_i),
+ .ack_o(inf1.slave_wb.ack_o),
+ .cyc_i(inf1.slave_wb.cyc_i),
+ .stb_i(inf1.slave_wb.stb_i),
+ .we_i(inf1.slave_wb.we_i),
+ .data_o(inf1.slave_wb.data_o),
+ .sel_i(inf1.slave_wb.sel_i),
+ // interface connection from bridge to wishbone(memory)
+ .hclk(inf1.master_ba.hclk),
+ .hresetn(inf1.master_ba.hresetn),
+ .hwrite(inf1.master_ba.hwrite),
+ .haddr(inf1.master_ba.haddr),
+ .hwdata(inf1.master_ba.hwdata),
+ .hburst(inf1.master_ba.hburst),
+ .hsize(inf1.master_ba.hsize),
+ .htrans(inf1.master_ba.htrans),
+ .hready(inf1.master_ba.hready),
+ .hrdata(inf1.master_ba.hrdata),
+ .hresp(inf1.master_ba.hresp));
+ wb_ahb_env env; // enviornment class
+// reset generation
+initial
+ begin
+ env = new(inf1);
+ #2 reset='b1;
+ #23 reset ='b0;
+ TB_M.initial_setup();
+ env.do_test();
+ $finish;
+
+ end
+
+//clock generation
+initial
+ forever
+ #(cyc_prd/2) clk = ~clk;
+endmodule
avm_svtb/wb_ahb_top.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_coverage.svh
===================================================================
--- avm_svtb/wb_ahb_coverage.svh (nonexistent)
+++ avm_svtb/wb_ahb_coverage.svh (revision 11)
@@ -0,0 +1,66 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_coverage.svh
+//Designaer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Coverage Status for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// coverage class
+import avm_pkg::*;
+import global::*;
+class wb_ahb_coverage extends avm_threaded_component;
+
+analysis_fifo#(monitor_pkt) ap_fifo; // analysis port fifo
+analysis_if#(monitor_pkt) ap_if; // analysis port interface
+
+// local variables
+logic [AWIDTH-1:0]adr1;
+logic [AWIDTH-1:0]adr2;
+logic [DWIDTH-1:0]dat1;
+logic [DWIDTH-1:0]dat2;
+bit stb,wr,ack;
+
+// monitor packet
+monitor_pkt m_pkt;
+
+// coverage group
+covergroup cov_wr;
+ write_read: coverpoint wr; // cover read/write
+ wr_with_wait_mst: cross wr,stb;// cover read/write on wait state by master
+ wr_with_wait_slv: cross wr,ack;// cover read/write on wait state by slave
+
+endgroup
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ ap_fifo =new("ap_fifo",this);
+ ap_if =null;
+ cov_wr=new;
+ endfunction
+
+// connecting analysis fifo to the analysis interface
+function void export_connections();
+ ap_if = ap_fifo.analysis_export;
+endfunction
+
+task run;
+ forever
+ begin
+ ap_fifo.get(m_pkt); // receiving monitor_pkt from monitor
+ // sampling the values of pkt to local variables
+ stb=m_pkt.stb;
+ wr=m_pkt.wr;
+ ack=m_pkt.ack;
+ // sample the coverpoints
+ cov_wr.sample();
+
+ end
+endtask
+
+endclass
+
avm_svtb/wb_ahb_coverage.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: avm_svtb/wb_ahb_driver.svh
===================================================================
--- avm_svtb/wb_ahb_driver.svh (nonexistent)
+++ avm_svtb/wb_ahb_driver.svh (revision 11)
@@ -0,0 +1,64 @@
+//******************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+
+
+//File name : wb_ahb_driver.svh
+//Designer : Ravi S Gupta
+//Date : 4 Sept, 2007
+//Description : Drivers for WISHBONE_AHB Bridge
+//Revision : 1.0
+
+//******************************************************************************************************
+
+// driver class
+import avm_pkg::*;
+import global::*;
+class wb_ahb_driver extends avm_threaded_component;
+
+avm_nonblocking_get_port #(wb_req_pkt) request_port;
+tlm_fifo #(wb_req_pkt) fifo;
+
+virtual wb_ahb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ request_port =new("request_port",this);
+ fifo =new("fifo",this);
+ pin_if = null;
+ endfunction
+
+task run;
+ wb_req_pkt req;
+ wb_res_pkt res;
+ forever
+ begin
+ @(posedge pin_if.master_wb.clk_i);
+ if(pin_if.master_wb.cyc_i && !pin_if.master_wb.rst_i)
+ begin
+ if(pin_if.master_wb.we_i)
+ begin
+ if(request_port.try_get(req))
+ write_to_bus(req);
+ end
+ else
+ begin
+ @(posedge pin_if.master_wb.clk_i);
+ if(request_port.try_get(req))
+ write_to_bus(req);
+ end
+
+ end
+ end
+endtask
+
+// write data to bus
+virtual task write_to_bus(input wb_req_pkt req);
+ #2 pin_if.master_wb.we_i=req.wr;
+ pin_if.master_wb.addr_i =req.adr;
+ pin_if.master_wb.data_i=req.dat;
+ pin_if.master_wb.stb_i=req.stb;
+
+endtask
+
+endclass
+
avm_svtb/wb_ahb_driver.svh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim_svtb/wb_run.all
===================================================================
--- sim_svtb/wb_run.all (nonexistent)
+++ sim_svtb/wb_run.all (revision 11)
@@ -0,0 +1,5 @@
+rm -rf ./work
+vlib work
+vlog -f compile_sv.f
+vsim -c -suppress 4025 -suppress 4029 -novopt wb_ahb_top -do "run 1000ns; exit"
+
sim_svtb/wb_run.all
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim_svtb/wb_coverage.all
===================================================================
--- sim_svtb/wb_coverage.all (nonexistent)
+++ sim_svtb/wb_coverage.all (revision 11)
@@ -0,0 +1,7 @@
+rm -rf ./work
+vlib work
+vlog -f compile_sv.f
+rm cover_rpt.ucdb cover_rpt.out
+vsim -c wb_ahb_top -do "run 1200ns ; fcover save cover_rpt.ucdb; vcover report -cvg -details cover_rpt.ucdb | tee cover_rpt.out; exit"
+gvim cover_rpt.out
+
sim_svtb/wb_coverage.all
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim_svtb/compile_sv.f
===================================================================
--- sim_svtb/compile_sv.f (nonexistent)
+++ sim_svtb/compile_sv.f (revision 11)
@@ -0,0 +1,8 @@
++incdir+libraries/systemverilog/avm
+libraries/systemverilog/avm/avm_pkg.sv
++incdir+.
+../avm_svtb/global.sv
+../avm_svtb/wb_ahb_interface.sv
+wb_ahb_pkg.sv
+../avm_svtb/wb_ahb_master.sv
+../avm_svtb/wb_ahb_top.sv
sim_svtb/compile_sv.f
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim_svtb/wb_ahb_pkg.sv
===================================================================
--- sim_svtb/wb_ahb_pkg.sv (nonexistent)
+++ sim_svtb/wb_ahb_pkg.sv (revision 11)
@@ -0,0 +1,12 @@
+`timescale 1 ns/ 1 ps
+package wb_ahb_pkg;
+import global::*;
+ `include "../avm_svtb/wb_ahb_stim_gen.svh"
+ `include "../avm_svtb/wb_ahb_driver.svh"
+ `include "../avm_svtb/wb_ahb_responder.svh"
+ `include "../avm_svtb/wb_ahb_monitor.svh"
+ `include "../avm_svtb/wb_ahb_scoreboard.svh"
+ `include "../avm_svtb/wb_ahb_coverage.svh"
+ `include "../avm_svtb/wb_ahb_env.svh"
+endpackage
+
sim_svtb/wb_ahb_pkg.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Readme.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: Readme.doc
===================================================================
--- Readme.doc (nonexistent)
+++ Readme.doc (revision 11)
Readme.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property