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URL https://opencores.org/ocsvn/wrimm/wrimm/trunk

Subversion Repositories wrimm

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  • This comparison shows the changes necessary to convert path 
    /wrimm/trunk
    from Rev 5 to Rev 6
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  •

Rev 5 → Rev 6

/License.txt File deleted \ No newline at end of file
/wrimm_top_TB.vhd File deleted
/WrimmExample_Top.vhd File deleted \ No newline at end of file
/WrimmBuild.sh
0,0 → 1,16
#!/bin/sh
 
# Propery of Tecphos Inc. See WrimmLicense.txt for license details
# Latest version of all Wrimm project files available at http://opencores.org/project,wrimm
# See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
# See wrimm subversion project for version history
 
#GHDL simulation script and gtkWave view of results
 
ghdl -i -v --workdir=work *.vhd
 
ghdl -m --workdir=work wrimm_top_tb
 
ghdl -r wrimm_top_tb --vcd=wrimm.vcd --assert-level=warning --stop-time=119ns
 
# gtkwave wrimm.vcd
/Wrimm.vhd
5,17 → 5,11
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wrimm;
use wrimm.WrimmPackage.all;
use ieee.numeric_std.all;
 
use work.WrimmPackage.all;
 
entity Wrimm is
--generic (
-- MasterParams : WbMasterDefType;
-- SlaveParams : WbSlaveDefType;
-- StatusParams : StatusFieldDefType;
-- SettingParams : SettingFieldDefType;
-- TriggerParams : TriggerFieldDefType);
port (
WbClk : in std_logic;
WbRst : out std_logic;
66,8 → 60,8
variable vGrant : WbMasterGrantType;
begin
if (rstZ='0') then
vGrant(vGrant'range) := (Others=>'0');
vGrant(vGrant'left) := '1';
vGrant := (Others=>'0');
vGrant(vGrant'left) := '1';
elsif rising_edge(WbClk) then
loopGrant: for i in WbMasterType loop
if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant
87,8 → 81,8
end if;
end if;
end loop loopGrant;
grant <= vGrant;
end if; --Clk
grant <= vGrant;
end process procArb;
--=============================================================================
-------------------------------------------------------------------------------
/Example/WrimmExample_Top.vhd
0,0 → 1,137
--Latest version of all project files available at http://opencores.org/project,wrimm
--See License.txt for license details
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.WrimmPackage.all;
 
entity Wrimm_Top is
port (
WishboneClock : in std_logic;
WishboneReset : out std_logic;
 
MasterPStrobe : in std_logic;
MasterPWrEn : in std_logic;
MasterPCyc : in std_logic;
MasterPAddr : in WbAddrType;
MasterPDataToSlave : in WbDataType;
MasterPAck : out std_logic;
MasterPErr : out std_logic;
MasterPRty : out std_logic;
MasterPDataFrSlave : out WbDataType;
 
MasterQStrobe : in std_logic;
MasterQWrEn : in std_logic;
MasterQCyc : in std_logic;
MasterQAddr : in WbAddrType;
MasterQDataToSlave : in WbDataType;
MasterQAck : out std_logic;
MasterQErr : out std_logic;
MasterQRty : out std_logic;
MasterQDataFrSlave : out WbDataType;
 
StatusRegA : in std_logic_vector(0 to 7);
StatusRegB : in std_logic_vector(0 to 7);
StatusRegC : in std_logic_vector(0 to 7);
 
SettingRegX : out std_logic_vector(0 to 7);
SettingRstX : in std_logic;
SettingRegY : out std_logic_vector(0 to 7);
SettingRstY : in std_logic;
SettingRegZ : out std_logic_vector(0 to 7);
SettingRstZ : in std_logic;
 
TriggerRegR : out std_logic;
TriggerClrR : in std_logic;
TriggerRegS : out std_logic;
TriggerClrS : in std_logic;
TriggerRegT : out std_logic;
TriggerClrT : in std_logic;
 
rstZ : in std_logic); --Global asyncronous reset for initialization
end entity Wrimm_Top;
 
architecture structure of Wrimm_Top is
 
component Wrimm is
--generic (
-- MasterParams : WbMasterDefType;
-- SlaveParams : WbSlaveDefType;
-- StatusParams : StatusFieldDefType;
-- SettingParams : SettingFieldDefType;
-- TriggerParams : TriggerFieldDefType);
port (
WbClk : in std_logic;
WbRst : out std_logic;
WbMasterIn : in WbMasterOutArray; --Signals from Masters
WbMasterOut : out WbSlaveOutArray; --Signals to Masters
-- WbSlaveIn : out WbMasterOutArray;
-- WbSlaveOut : in WbSlaveOutArray;
StatusRegs : in StatusArrayType;
SettingRegs : out SettingArrayType;
SettingRsts : in SettingArrayBitType;
Triggers : out TriggerArrayType;
TriggerClr : in TriggerArrayType;
rstZ : in std_logic); --Asynchronous reset
end component Wrimm;
 
signal masterQOut : WbSlaveOutType;
signal masterQIn : WbMasterOutType;
 
begin
MasterQAck <= masterQOut.ack;
MasterQErr <= masterQOut.err;
MasterQRty <= masterQOut.rty;
MasterQDataFrSlave <= masterQOut.data;
 
masterQIn.strobe <= MasterQStrobe;
masterQIn.wren <= MasterQWrEn;
masterQIn.cyc <= MasterQCyc;
masterQIn.addr <= MasterQAddr;
masterQIn.data <= MasterQDataToSlave;
 
instWrimm: Wrimm
--generic map(
-- MasterParams => ,
-- SlaveParams => ,
-- StatusParams => StatusParams,
-- SettingParams => SettingParams,
-- TriggerParams => TriggerParams)
port map(
WbClk => WishboneClock,
WbRst => WishboneReset,
WbMasterIn(P).strobe => MasterPStrobe,
WbMasterIn(P).wren => MasterPWrEn,
WbMasterIn(P).cyc => MasterPCyc,
WbMasterIn(P).addr => MasterPAddr,
WbMasterIn(P).data => MasterPDataToSlave,
WbMasterIn(Q) => masterQIn,
WbMasterOut(P).ack => MasterPAck,
WbMasterOut(P).err => MasterPErr,
WbMasterOut(P).rty => MasterPRty,
WbMasterOut(P).data => MasterPDataFrSlave,
WbMasterOut(Q) => masterQOut,
--WbSlaveIn => ,
--WbSlaveOut => ,
StatusRegs(StatusA) => StatusRegA,
StatusRegs(StatusB) => StatusRegB,
StatusRegs(StatusC) => StatusRegC,
SettingRegs(SettingX) => SettingRegX,
SettingRegs(SettingY) => SettingRegY,
SettingRegs(SettingZ) => SettingRegZ,
SettingRsts(SettingX) => SettingRstX,
SettingRsts(SettingY) => SettingRstY,
SettingRsts(SettingZ) => SettingRstZ,
Triggers(TriggerR) => TriggerRegR,
Triggers(TriggerS) => TriggerRegS,
Triggers(TriggerT) => TriggerRegT,
TriggerClr(TriggerR) => TriggerClrR,
TriggerClr(TriggerS) => TriggerClrS,
TriggerClr(TriggerT) => TriggerClrT,
rstZ => rstZ); --Asynchronous reset
 
end architecture structure;
/ReadMe.txt
0,0 → 1,4
Propery of Tecphos Inc. See WrimmLicense.txt for license details
Latest version of all Wrimm project files available at http://opencores.org/project,wrimm
See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
See wrimm subversion project for version history
/WrimmTestBench
0,0 → 1,220
--Propery of Tecphos Inc. See License.txt for license details
--Latest version of all project files available at http://opencores.org/project,wrimm
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
 
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
 
use work.WrimmPackage.all;
 
entity wrimm_top_tb is
end wrimm_top_tb;
 
architecture TB_ARCHITECTURE of wrimm_top_tb is
component wrimm_top
port(
WishboneClock : in std_logic;
WishboneReset : out std_logic;
MasterPStrobe : in std_logic;
MasterPWrEn : in std_logic;
MasterPCyc : in std_logic;
MasterPAddr : in WbAddrType;
MasterPDataToSlave : in WbDataType;
MasterPAck : out std_logic;
MasterPErr : out std_logic;
MasterPRty : out std_logic;
MasterPDataFrSlave : out WbDataType;
MasterQStrobe : in std_logic;
MasterQWrEn : in std_logic;
MasterQCyc : in std_logic;
MasterQAddr : in WbAddrType;
MasterQDataToSlave : in WbDataType;
MasterQAck : out std_logic;
MasterQErr : out std_logic;
MasterQRty : out std_logic;
MasterQDataFrSlave : out WbDataType;
StatusRegA : in std_logic_vector(0 to 7);
StatusRegB : in std_logic_vector(0 to 7);
StatusRegC : in std_logic_vector(0 to 7);
SettingRegX : out std_logic_vector(0 to 7);
SettingRstX : in std_logic;
SettingRegY : out std_logic_vector(0 to 7);
SettingRstY : in std_logic;
SettingRegZ : out std_logic_vector(0 to 7);
SettingRstZ : in std_logic;
TriggerRegR : out std_logic;
TriggerClrR : in std_logic;
TriggerRegS : out std_logic;
TriggerClrS : in std_logic;
TriggerRegT : out std_logic;
TriggerClrT : in std_logic;
rstZ : in std_logic);
end component;
 
signal WishboneClock : std_logic;
signal MasterPStrobe : std_logic;
signal MasterPWrEn : std_logic;
signal MasterPCyc : std_logic;
signal MasterPAddr : WbAddrType;
signal MasterPDataToSlave : WbDataType;
signal MasterQStrobe : std_logic;
signal MasterQWrEn : std_logic;
signal MasterQCyc : std_logic;
signal MasterQAddr : WbAddrType;
signal MasterQDataToSlave : WbDataType;
signal StatusRegA : std_logic_vector(0 to 7);
signal StatusRegB : std_logic_vector(0 to 7);
signal StatusRegC : std_logic_vector(0 to 7);
signal SettingRstX : std_logic;
signal SettingRstY : std_logic;
signal SettingRstZ : std_logic;
signal TriggerClrR : std_logic;
signal TriggerClrS : std_logic;
signal TriggerClrT : std_logic;
signal rstZ : std_logic;
signal WishboneReset : std_logic;
signal MasterPAck : std_logic;
signal MasterPErr : std_logic;
signal MasterPRty : std_logic;
signal MasterPDataFrSlave : WbDataType;
signal MasterQAck : std_logic;
signal MasterQErr : std_logic;
signal MasterQRty : std_logic;
signal MasterQDataFrSlave : WbDataType;
signal SettingRegX : std_logic_vector(0 to 7);
signal SettingRegY : std_logic_vector(0 to 7);
signal SettingRegZ : std_logic_vector(0 to 7);
signal TriggerRegR : std_logic;
signal TriggerRegS : std_logic;
signal TriggerRegT : std_logic;
 
constant clkPeriod : time := 0.01 us; --100 MHz
 
begin
UUT : wrimm_top
port map (
WishboneClock => WishboneClock,
WishboneReset => WishboneReset,
MasterPStrobe => MasterPStrobe,
MasterPWrEn => MasterPWrEn,
MasterPCyc => MasterPCyc,
MasterPAddr => MasterPAddr,
MasterPDataToSlave => MasterPDataToSlave,
MasterPAck => MasterPAck,
MasterPErr => MasterPErr,
MasterPRty => MasterPRty,
MasterPDataFrSlave => MasterPDataFrSlave,
MasterQStrobe => MasterQStrobe,
MasterQWrEn => MasterQWrEn,
MasterQCyc => MasterQCyc,
MasterQAddr => MasterQAddr,
MasterQDataToSlave => MasterQDataToSlave,
MasterQAck => MasterQAck,
MasterQErr => MasterQErr,
MasterQRty => MasterQRty,
MasterQDataFrSlave => MasterQDataFrSlave,
StatusRegA => StatusRegA,
StatusRegB => StatusRegB,
StatusRegC => StatusRegC,
SettingRegX => SettingRegX,
SettingRstX => SettingRstX,
SettingRegY => SettingRegY,
SettingRstY => SettingRstY,
SettingRegZ => SettingRegZ,
SettingRstZ => SettingRstZ,
TriggerRegR => TriggerRegR,
TriggerClrR => TriggerClrR,
TriggerRegS => TriggerRegS,
TriggerClrS => TriggerClrS,
TriggerRegT => TriggerRegT,
TriggerClrT => TriggerClrT,
rstZ => rstZ);
 
procClk: process
begin
if WishBoneClock='1' then
WishBoneClock <= '0';
else
WishBoneClock <= '1';
end if;
wait for clkPeriod/2;
end process procClk;
 
procRstZ: process
begin
rstZ <= '0';
wait for 10 ns;
rstZ <= '1';
wait;
end process procRstZ;
 
procWbMasterP: process
begin
MasterPStrobe <= '0';
MasterPWrEn <= '0';
MasterPCyc <= '0';
MasterPAddr <= x"0";
MasterPDataToSlave <= x"00";
wait for clkPeriod / 10;
wait for clkPeriod * 5;
MasterPStrobe <= '1';
MasterPWrEn <= '1';
MasterPCyc <= '1';
MasterPAddr <= x"6";
MasterPDataToSlave <= x"55";
wait for clkPeriod * 2;
MasterPStrobe <= '0';
MasterPWrEn <= '0';
MasterPCyc <= '0';
MasterPAddr <= x"0";
MasterPDataToSlave <= x"00";
wait for clkPeriod * 10;
MasterPStrobe <= '1';
MasterPWrEn <= '1';
MasterPCyc <= '1';
MasterPAddr <= x"6";
MasterPDataToSlave <= x"99";
wait for clkPeriod * 2;
MasterPStrobe <= '0';
MasterPWrEn <= '0';
MasterPCyc <= '0';
MasterPAddr <= x"0";
MasterPDataToSlave <= x"00";
wait;
end process procWbMasterP;
procWbMasterQ: process
begin
MasterQStrobe <= '0';
MasterQWrEn <= '0';
MasterQCyc <= '0';
MasterQAddr <= x"0";
MasterQDataToSlave <= x"00";
wait for clkPeriod / 10;
wait for clkPeriod * 8;
MasterQStrobe <= '1';
MasterQWrEn <= '1';
MasterQCyc <= '1';
MasterQAddr <= x"6";
MasterQDataToSlave <= x"77";
wait for clkPeriod * 2;
MasterQStrobe <= '0';
MasterQWrEn <= '0';
MasterQCyc <= '0';
MasterQAddr <= x"0";
MasterQDataToSlave <= x"00";
wait for clkPeriod * 2;
assert false report "Test Complete" severity warning;
end process procWbMasterQ;
 
end TB_ARCHITECTURE;
 
configuration TESTBENCH_FOR_wrimm_top of wrimm_top_tb is
for TB_ARCHITECTURE
for UUT : wrimm_top
use entity work.wrimm_top(structure);
end for;
end for;
end TESTBENCH_FOR_wrimm_top;
 
/WrimmLicense.txt
0,0 → 1,24
All files in Wrimm project are Copyright (c) 2014, Tecphos Inc.
All rights reserved.
 
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Tecphos Inc. nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Tecphos Inc. BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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