URL
https://opencores.org/ocsvn/wrimm/wrimm/trunk
Subversion Repositories wrimm
Compare Revisions
- This comparison shows the changes necessary to convert path
/wrimm
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/WrimmBuild.sh
5,12 → 5,12
# See WrimmManual.pdf for the Wishbone Datasheet and implementation details. |
# See wrimm subversion project for version history |
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#GHDL simulation script and gtkWave view of results |
#GHDL simulation script and gtkWave view results |
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ghdl -i -v --workdir=work *.vhd |
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ghdl -m --workdir=work wrimm_top_tb |
ghdl -m --workdir=work WrimmTestBench |
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ghdl -r wrimm_top_tb --vcd=wrimm.vcd --assert-level=warning --stop-time=119ns |
ghdl -r WrimmTestBench --wave=wrimm.ghw --assert-level=error --stop-time=1000ns |
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# gtkwave wrimm.vcd |
# gtkwave wrimm.ghw |
/trunk/WrimmPackage.vhd
87,9 → 87,9
type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams; |
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constant SettingParams : SettingFieldDefType :=( |
SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"00"), |
SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"00"), |
SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"00")); |
SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"05"), |
SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"3C"), |
SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"AA")); |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Trigger Registers (Report internal results) |
/trunk/Example/WrimmExample_Top.vhd
1,7 → 1,7
--Latest version of all project files available at http://opencores.org/project,wrimm |
--See License.txt for license details |
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details. |
--See wrimm subversion project for version history |
--Propery of Tecphos Inc. See License.txt for license details |
--Latest version of all project files available at http://opencores.org/project,wrimm |
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details. |
--See wrimm subversion project for version history |
|
library ieee; |
use ieee.std_logic_1164.all; |
58,12 → 58,6
architecture structure of Wrimm_Top is |
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component Wrimm is |
--generic ( |
-- MasterParams : WbMasterDefType; |
-- SlaveParams : WbSlaveDefType; |
-- StatusParams : StatusFieldDefType; |
-- SettingParams : SettingFieldDefType; |
-- TriggerParams : TriggerFieldDefType); |
port ( |
WbClk : in std_logic; |
WbRst : out std_logic; |
/trunk/Wrimm.vhd
1,5 → 1,5
--Latest version of all project files available at http://opencores.org/project,wrimm |
--See License.txt for license details |
--Propery of Tecphos Inc. See WrimmLicense.txt for license details |
--Latest version of all Wrimm project files available at http://opencores.org/project,wrimm |
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details. |
--See wrimm subversion project for version history |
|
/trunk/WrimmTestBench.vhd
5,216 → 5,200
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library ieee; |
use ieee.NUMERIC_STD.all; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_1164.all; |
use std.textio.all; |
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use work.WrimmPackage.all; |
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entity wrimm_top_tb is |
end wrimm_top_tb; |
entity WrimmTestBench is |
end WrimmTestBench; |
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architecture TbArch of WrimmTestBench is |
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architecture TB_ARCHITECTURE of wrimm_top_tb is |
component wrimm_top |
port( |
WishboneClock : in std_logic; |
WishboneReset : out std_logic; |
MasterPStrobe : in std_logic; |
MasterPWrEn : in std_logic; |
MasterPCyc : in std_logic; |
MasterPAddr : in WbAddrType; |
MasterPDataToSlave : in WbDataType; |
MasterPAck : out std_logic; |
MasterPErr : out std_logic; |
MasterPRty : out std_logic; |
MasterPDataFrSlave : out WbDataType; |
MasterQStrobe : in std_logic; |
MasterQWrEn : in std_logic; |
MasterQCyc : in std_logic; |
MasterQAddr : in WbAddrType; |
MasterQDataToSlave : in WbDataType; |
MasterQAck : out std_logic; |
MasterQErr : out std_logic; |
MasterQRty : out std_logic; |
MasterQDataFrSlave : out WbDataType; |
StatusRegA : in std_logic_vector(0 to 7); |
StatusRegB : in std_logic_vector(0 to 7); |
StatusRegC : in std_logic_vector(0 to 7); |
SettingRegX : out std_logic_vector(0 to 7); |
SettingRstX : in std_logic; |
SettingRegY : out std_logic_vector(0 to 7); |
SettingRstY : in std_logic; |
SettingRegZ : out std_logic_vector(0 to 7); |
SettingRstZ : in std_logic; |
TriggerRegR : out std_logic; |
TriggerClrR : in std_logic; |
TriggerRegS : out std_logic; |
TriggerClrS : in std_logic; |
TriggerRegT : out std_logic; |
TriggerClrT : in std_logic; |
rstZ : in std_logic); |
end component; |
component Wrimm is |
port ( |
WbClk : in std_logic; |
WbRst : out std_logic; |
WbMasterIn : in WbMasterOutArray; --Signals from Masters |
WbMasterOut : out WbSlaveOutArray; --Signals to Masters |
--WbSlaveIn : out WbMasterOutArray; |
--WbSlaveOut : in WbSlaveOutArray; |
StatusRegs : in StatusArrayType; |
SettingRegs : out SettingArrayType; |
SettingRsts : in SettingArrayBitType; |
Triggers : out TriggerArrayType; |
TriggerClr : in TriggerArrayType; |
rstZ : in std_logic); --Asynchronous reset |
end component Wrimm; |
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signal wbMastersOut : WbSlaveOutArray; |
signal wbMastersIn : WbMasterOutArray; |
signal statusRegs : StatusArrayType; |
signal settingRegs : SettingArrayType; |
signal settingRsts : SettingArrayBitType; |
signal triggers : TriggerArrayType; |
signal triggerClrs : TriggerArrayType; |
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signal rstZ : std_logic; |
signal WishboneClock : std_logic; |
signal WishBoneReset : std_logic; |
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signal WishboneClock : std_logic; |
signal MasterPStrobe : std_logic; |
signal MasterPWrEn : std_logic; |
signal MasterPCyc : std_logic; |
signal MasterPAddr : WbAddrType; |
signal MasterPDataToSlave : WbDataType; |
signal MasterQStrobe : std_logic; |
signal MasterQWrEn : std_logic; |
signal MasterQCyc : std_logic; |
signal MasterQAddr : WbAddrType; |
signal MasterQDataToSlave : WbDataType; |
signal StatusRegA : std_logic_vector(0 to 7); |
signal StatusRegB : std_logic_vector(0 to 7); |
signal StatusRegC : std_logic_vector(0 to 7); |
signal SettingRstX : std_logic; |
signal SettingRstY : std_logic; |
signal SettingRstZ : std_logic; |
signal TriggerClrR : std_logic; |
signal TriggerClrS : std_logic; |
signal TriggerClrT : std_logic; |
signal rstZ : std_logic; |
signal WishboneReset : std_logic; |
signal MasterPAck : std_logic; |
signal MasterPErr : std_logic; |
signal MasterPRty : std_logic; |
signal MasterPDataFrSlave : WbDataType; |
signal MasterQAck : std_logic; |
signal MasterQErr : std_logic; |
signal MasterQRty : std_logic; |
signal MasterQDataFrSlave : WbDataType; |
signal SettingRegX : std_logic_vector(0 to 7); |
signal SettingRegY : std_logic_vector(0 to 7); |
signal SettingRegZ : std_logic_vector(0 to 7); |
signal TriggerRegR : std_logic; |
signal TriggerRegS : std_logic; |
signal TriggerRegT : std_logic; |
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constant clkPeriod : time := 0.01 us; --100 MHz |
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begin |
UUT : wrimm_top |
port map ( |
WishboneClock => WishboneClock, |
WishboneReset => WishboneReset, |
MasterPStrobe => MasterPStrobe, |
MasterPWrEn => MasterPWrEn, |
MasterPCyc => MasterPCyc, |
MasterPAddr => MasterPAddr, |
MasterPDataToSlave => MasterPDataToSlave, |
MasterPAck => MasterPAck, |
MasterPErr => MasterPErr, |
MasterPRty => MasterPRty, |
MasterPDataFrSlave => MasterPDataFrSlave, |
MasterQStrobe => MasterQStrobe, |
MasterQWrEn => MasterQWrEn, |
MasterQCyc => MasterQCyc, |
MasterQAddr => MasterQAddr, |
MasterQDataToSlave => MasterQDataToSlave, |
MasterQAck => MasterQAck, |
MasterQErr => MasterQErr, |
MasterQRty => MasterQRty, |
MasterQDataFrSlave => MasterQDataFrSlave, |
StatusRegA => StatusRegA, |
StatusRegB => StatusRegB, |
StatusRegC => StatusRegC, |
SettingRegX => SettingRegX, |
SettingRstX => SettingRstX, |
SettingRegY => SettingRegY, |
SettingRstY => SettingRstY, |
SettingRegZ => SettingRegZ, |
SettingRstZ => SettingRstZ, |
TriggerRegR => TriggerRegR, |
TriggerClrR => TriggerClrR, |
TriggerRegS => TriggerRegS, |
TriggerClrS => TriggerClrS, |
TriggerRegT => TriggerRegT, |
TriggerClrT => TriggerClrT, |
rstZ => rstZ); |
begin |
procClk: process |
begin |
if WishBoneClock='1' then |
WishBoneClock <= '0'; |
else |
WishBoneClock <= '1'; |
end if; |
wait for clkPeriod/2; |
end process procClk; |
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procRstZ: process |
begin |
rstZ <= '0'; |
wait for 10 ns; |
rstZ <= '1'; |
wait; |
end process procRstZ; |
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instWrimm: Wrimm |
port map( |
WbClk => WishboneClock, |
WbRst => WishboneReset, |
WbMasterIn => wbMastersIn, |
WbMasterOut => wbMastersOut, |
--WbSlaveIn => , |
--WbSlaveOut => , |
StatusRegs => statusRegs, |
SettingRegs => settingRegs, |
SettingRsts => settingRsts, |
Triggers => triggers, |
TriggerClr => triggerClrs, |
rstZ => rstZ); |
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procStatusStim: process(WishboneClock) is |
variable statusCount : unsigned (0 to WbDataBits-1) := (Others=>'0'); |
begin |
if rising_edge(WishboneClock) then |
loopStatusAssign: for i in StatusFieldType loop |
statusRegs(i) <= std_logic_vector(statusCount); |
statusCount := statusCount + 1; --actual values don't matter, just generating unique values. |
end loop loopStatusAssign; |
end if; --Clk |
end process procStatusStim; |
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procStatusVerify: process(WishboneClock) is |
variable L : line; |
begin |
if rising_edge(WishBoneClock) then |
loopMasters: for i in WbMasterType loop |
if wbMastersOut(i).Ack='1' and wbMastersIn(i).WrEn='0' then --valid Ack to Read request |
loopStatusRegs: for j in StatusFieldType loop |
if StatusParams(j).Address=wbMastersIn(i).Addr then --correct address |
report "Evaluating Status Read" severity NOTE; |
assert (statusRegs(j)=wbMastersOut(i).data) report "Invalid Status Register Read" severity Warning; |
end if; |
end loop loopStatusRegs; |
end if; -- valid Ack |
end loop loopMasters; |
end if; --Clk |
end process procStatusVerify; |
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procSettingResets: process(WishboneClock) is |
variable resetVector : unsigned(0 to settingRsts'length-1) := (Others=>'0'); |
variable resetCount : integer := 0; |
variable resetIndex : integer := 0; |
begin |
if rising_edge(WishboneClock) then |
if resetCount=20 then |
resetCount := 0; |
resetVector := resetVector+1; |
resetIndex := 0; |
loopSetRsts: for i in SettingFieldType loop |
settingRsts(i) <= resetVector(resetIndex); |
resetIndex := resetIndex + 1; |
end loop loopSetRsts; |
else |
resetCount := resetCount + 1; |
settingRsts <= (Others=>'0'); |
end if; |
end if; --Clk |
end process procSettingResets; |
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procSettingMonitor: process(WishboneClock,rstZ) is |
variable settingTBRegs : SettingArrayType; |
begin |
if (rstZ='0') then |
loopSettingRstZ: for i in SettingFieldType loop |
settingTBRegs(i) := SettingParams(i).Default; |
end loop loopSettingRstZ; |
elsif rising_edge(WishboneClock) then |
loopSettingRegsCheck : for k in SettingFieldType loop |
assert (settingTBRegs(k)=settingRegs(k)) report "Setting Reg Mismatch" severity Warning; |
end loop loopSettingRegsCheck; |
loopMasters: for i in WbMasterType loop --valid Ack |
if wbMastersOut(i).Ack='1' then |
if wbMastersIn(i).WrEn='1' then -- Write request |
loopSettingWriteRegs: for j in SettingFieldType loop |
if SettingParams(j).Address=wbMastersIn(i).Addr then --valid setting address |
report "Writing Setting Reg"; |
settingTBRegs(j) := wbMastersIn(i).data; |
end if; --Address match |
end loop loopSettingWriteRegs; |
else -- Read request |
loopSettingReadRegs: for j in SettingFieldType loop |
if SettingParams(j).Address=wbMastersIn(i).Addr then --valid setting address |
report "Reading Setting Reg"; |
assert (wbMastersOut(i).data=settingTBRegs(j)) report "Setting Read Mismatch" severity Warning; |
end if; --Address match |
end loop loopSettingReadRegs; |
end if; --WrEn |
end if; --Ack to write |
end loop loopMasters; |
loopSettingResets: for i in SettingFieldType loop |
if settingRsts(i)='1' then |
settingTBRegs(i) := SettingParams(i).Default; |
end if; |
end loop loopSettingResets; |
end if; --Clk |
end process procSettingMonitor; |
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procClk: process |
begin |
if WishBoneClock='1' then |
WishBoneClock <= '0'; |
else |
WishBoneClock <= '1'; |
end if; |
wait for clkPeriod/2; |
end process procClk; |
procMasterStim: process(WishboneClock,rstZ) is |
variable rCount : unsigned(0 to WbAddrBits) := (Others=>'0'); |
variable rData : unsigned(0 to WbDataBits-1) := (Others=>'0'); |
variable burstCount : integer := 5; |
variable idleCount : integer := 4; |
begin |
if rising_edge(WishboneClock) then |
rData := rData + 1; |
if WbMastersOut(Q).Ack='1' or WbMastersOut(Q).Rty='1' or WbMastersOut(Q).Err='1' then |
rCount := rCount + 1; |
burstCount := burstcount - 1; |
if burstCount=0 then |
idleCount := 3; |
end if; |
elsif idleCount=0 then |
if burstCount=0 then |
burstCount := 4; |
end if; |
else |
idleCount := idleCount - 1; |
end if; |
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wbMastersIn(Q).Data <= std_logic_vector(rData); |
wbMastersIn(Q).Addr <= std_logic_vector(rCount(1 to WbAddrBits)); |
wbMastersIn(Q).WrEn <= rCount(0); --read then write |
if burstCount=0 then |
wbMastersIn(Q).Strobe <= '0'; |
wbMastersIn(Q).Cyc <= '0'; |
else |
wbMastersIn(Q).Strobe <= '1'; |
wbMastersIn(Q).Cyc <= '1'; |
end if; |
end if; --Clk |
end process procMasterStim; |
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procRstZ: process |
begin |
rstZ <= '0'; |
wait for 10 ns; |
rstZ <= '1'; |
wait; |
end process procRstZ; |
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procWbMasterP: process |
begin |
MasterPStrobe <= '0'; |
MasterPWrEn <= '0'; |
MasterPCyc <= '0'; |
MasterPAddr <= x"0"; |
MasterPDataToSlave <= x"00"; |
wait for clkPeriod / 10; |
wait for clkPeriod * 5; |
MasterPStrobe <= '1'; |
MasterPWrEn <= '1'; |
MasterPCyc <= '1'; |
MasterPAddr <= x"6"; |
MasterPDataToSlave <= x"55"; |
wait for clkPeriod * 2; |
MasterPStrobe <= '0'; |
MasterPWrEn <= '0'; |
MasterPCyc <= '0'; |
MasterPAddr <= x"0"; |
MasterPDataToSlave <= x"00"; |
wait for clkPeriod * 10; |
MasterPStrobe <= '1'; |
MasterPWrEn <= '1'; |
MasterPCyc <= '1'; |
MasterPAddr <= x"6"; |
MasterPDataToSlave <= x"99"; |
wait for clkPeriod * 2; |
MasterPStrobe <= '0'; |
MasterPWrEn <= '0'; |
MasterPCyc <= '0'; |
MasterPAddr <= x"0"; |
MasterPDataToSlave <= x"00"; |
wait; |
end process procWbMasterP; |
procWbMasterQ: process |
begin |
MasterQStrobe <= '0'; |
MasterQWrEn <= '0'; |
MasterQCyc <= '0'; |
MasterQAddr <= x"0"; |
MasterQDataToSlave <= x"00"; |
wait for clkPeriod / 10; |
wait for clkPeriod * 8; |
MasterQStrobe <= '1'; |
MasterQWrEn <= '1'; |
MasterQCyc <= '1'; |
MasterQAddr <= x"6"; |
MasterQDataToSlave <= x"77"; |
wait for clkPeriod * 2; |
MasterQStrobe <= '0'; |
MasterQWrEn <= '0'; |
MasterQCyc <= '0'; |
MasterQAddr <= x"0"; |
MasterQDataToSlave <= x"00"; |
wait for clkPeriod * 2; |
assert false report "Test Complete" severity warning; |
end process procWbMasterQ; |
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end TB_ARCHITECTURE; |
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configuration TESTBENCH_FOR_wrimm_top of wrimm_top_tb is |
for TB_ARCHITECTURE |
for UUT : wrimm_top |
use entity work.wrimm_top(structure); |
end for; |
end for; |
end TESTBENCH_FOR_wrimm_top; |
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end TbArch; |