URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
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- This comparison shows the changes necessary to convert path
/xgate/trunk/rtl/verilog
- from Rev 12 to Rev 15
- ↔ Reverse comparison
Rev 12 → Rev 15
/xgate_regs.v
43,7 → 43,8
( |
output reg xge, // XGATE Module Enable |
output reg xgfrz, // Stop XGATE in Freeze Mode |
output reg xgdbg, // XGATE Debug Mode |
output reg xgdbg_set, // Enter XGATE Debug Mode |
output reg xgdbg_clear, // Leave XGATE Debug Mode |
output reg xgss, // XGATE Single Step |
output reg xgfact, // XGATE Flag Activity |
output reg xgsweif_c, // Clear XGATE Software Error Interrupt FLag |
99,13 → 100,13
|
// generate wishbone write registers |
// XGMCTL Register |
// xgdbgm; // XGATE Debug Mode Mask |
always @(posedge bus_clk or negedge async_rst_b) |
if (!async_rst_b) |
begin |
xge <= 1'b0; |
xgfrz <= 1'b0; |
xgdbg <= 1'b0; |
xgdbg_set <= 1'b0; |
xgdbg_clear <= 1'b0; |
xgss <= 1'b0; |
xgfact <= 1'b0; |
brk_irq_ena <= 1'b0; |
116,7 → 117,8
begin |
xge <= 1'b0; |
xgfrz <= 1'b0; |
xgdbg <= 1'b0; |
xgdbg_set <= 1'b0; |
xgdbg_clear <= 1'b0; |
xgss <= 1'b0; |
xgfact <= 1'b0; |
brk_irq_ena <= 1'b0; |
127,7 → 129,8
begin |
xge <= write_bus[15] ? write_bus[7] : xge; |
xgfrz <= write_bus[14] ? write_bus[6] : xgfrz; |
xgdbg <= write_bus[13] ? write_bus[5] : xgdbg; |
xgdbg_set <= write_bus[13] && write_bus[5]; |
xgdbg_clear <= write_bus[13] && !write_bus[5]; |
xgss <= write_bus[12] && write_bus[4]; |
xgfact <= write_bus[11] ? write_bus[3] : xgfact; |
brk_irq_ena <= write_bus[10] ? write_bus[2] : brk_irq_ena; |
136,8 → 139,10
end |
else |
begin |
xgss <= 1'b0; |
xgsweif_c <= 1'b0; |
xgss <= 1'b0; |
xgsweif_c <= 1'b0; |
xgdbg_set <= 1'b0; |
xgdbg_clear <= 1'b0; |
end |
|
// XGVBR Register |
/xgate_risc.v
69,7 → 69,8
input mem_req_ack, // Memory Bus available - data good |
input xge, // XGATE Module Enable |
input xgfrz, // Stop XGATE in Freeze Mode |
input xgdbg, // XGATE Debug Mode |
input xgdbg_set, // Enter XGATE Debug Mode |
input xgdbg_clear, // Leave XGATE Debug Mode |
input xgss, // XGATE Single Step |
input [15:1] xgvbr, // XGATE vector Base Address Register |
input [ 6:0] int_req, // Encoded interrupt request |
188,8 → 189,7
reg xgss_edge; // Flop for edge detection |
wire single_step; // Pulse to trigger a single instruction execution in debug mode |
reg brk_set_dbg; // Pulse to set debug_active from instruction decoder |
reg xgdbg_dly; // |
wire xgdbg_negedge; // |
reg cmd_change_pc; // Debug write to PC register |
|
|
assign xgate_address = data_access ? data_address : program_counter; |
204,7 → 204,7
assign start_thread = xge && (|int_req); |
|
assign cpu_is_idle = (cpu_state == IDLE); |
assign perif_wrt_ena = (cpu_is_idle && ~xge) || xgdbg; |
assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active; |
|
// Decode register select for RD and RS |
always @* |
226,7 → 226,7
// Decode register write select for eather RD or RI/RS2 |
always @* |
begin |
wrt_sel_xgr1 = (cpu_state == BOOT_2); |
wrt_sel_xgr1 = (cpu_state == BOOT_3); |
wrt_sel_xgr2 = 1'b0; |
wrt_sel_xgr3 = 1'b0; |
wrt_sel_xgr4 = 1'b0; |
294,21 → 294,12
|
assign xg_sw_irq = software_error && xgie; |
|
// Edge detect xgdbg |
always @(posedge risc_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
xgdbg_dly <= 1'b0; |
else |
xgdbg_dly <= xgdbg; |
|
assign xgdbg_negedge = !xgdbg && xgdbg_dly; |
|
// Latch the debug state, set by eather xgdb or BRK instructions |
always @(posedge risc_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
debug_active <= 1'b0; |
else |
debug_active <= !xgdbg_negedge && (xgdbg || brk_set_dbg || op_code_error || debug_active); |
debug_active <= !xgdbg_clear && (xgdbg_set || brk_set_dbg || op_code_error || debug_active); |
|
// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse |
always @(posedge risc_clk or negedge async_rst_b) |
355,6 → 346,13
else |
program_counter <= (write_xgpc && perif_wrt_ena) ? perif_data : (mem_req_ack ? next_pc : program_counter); |
|
// Debug Change Program Counter Register |
always @(posedge risc_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
cmd_change_pc <= 1'b0; |
else |
cmd_change_pc <= write_xgpc && perif_wrt_ena; |
|
// ALU Flag Bits |
always @(posedge risc_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
559,8 → 557,8
|
{DEBUG, 16'b????????????????} : |
begin |
next_cpu_state = xge ? ((single_step || !debug_active) ? CONT : DEBUG) : IDLE; |
load_next_inst = 1'b0; |
next_cpu_state = xge ? ((single_step || !debug_active) ? CONT : (cmd_change_pc ? LD_INST : DEBUG)) : IDLE; |
load_next_inst = cmd_change_pc; |
next_pc = program_counter; |
end |
|
/xgate_top.v
126,7 → 126,8
|
wire xge; // XGATE Module Enable |
wire xgfrz; // Stop XGATE in Freeze Mode |
wire xgdbg; // XGATE Debug Mode |
wire xgdbg_set; // Enter XGATE Debug Mode |
wire xgdbg_clear; // Leave XGATE Debug Mode |
wire xgss; // XGATE Single Step |
wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag |
wire xgie; // XGATE Interrupt Enable |
230,7 → 231,8
// outputs |
.xge( xge ), |
.xgfrz( xgfrz ), |
.xgdbg( xgdbg ), |
.xgdbg_set( xgdbg_set ), |
.xgdbg_clear( xgdbg_clear ), |
.xgss( xgss ), |
.xgsweif_c( xgsweif_c ), |
.xgie( xgie ), |
304,7 → 306,8
.mem_req_ack( mem_req_ack ), |
.xge( xge ), |
.xgfrz( xgfrz ), |
.xgdbg( xgdbg ), |
.xgdbg_set( xgdbg_set ), |
.xgdbg_clear( xgdbg_clear ), |
.xgss( xgss ), |
.xgvbr( xgvbr ), |
.int_req( int_req ), |