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  • This comparison shows the changes necessary to convert path 
    /xgate/trunk/rtl/verilog
    from Rev 15 to Rev 17
    ↔ Reverse comparison
  •

Rev 15 → Rev 17

/xgate_wbs_bus.v
56,6 → 56,7
input [1:0] wbs_sel_i, // Select byte in word bus transaction
// XGATE Control Signals
output reg write_xgmctl, // Write Strobe for XGMCTL register
output reg write_xgchid, // Write Strobe for XGCHID register
output reg write_xgisp74,// Write Strobe for XGISP74 register
output reg write_xgisp30,// Write Strobe for XGISP30 register
output reg write_xgvbr, // Write Strobe for XGVBR register
89,7 → 90,8
reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux
reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data
reg write_reserv; // Dummy Reg decode for Reserved address
reg write_reserv1; // Dummy Reg decode for Reserved address
reg write_reserv2; // Dummy Reg decode for Reserved address
 
// Wires
wire module_sel; // This module is selected for bus transaction
163,8 → 165,10
// generate wishbone write register strobes
always @*
begin
write_reserv = 1'b0;
write_xgmctl = 1'b0;
write_reserv1 = 1'b0;
write_reserv2 = 1'b0;
write_xgmctl = 1'b0;
write_xgchid = 1'b0;
write_xgisp74 = 1'b0;
write_xgisp30 = 1'b0;
write_xgvbr = 1'b0;
192,7 → 196,7
case (wbs_adr_i) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
5'b0_0000 : write_xgmctl = 1'b1;
// 5'b0_0001 : write_xgchid = 1'b1;
5'b0_0001 : write_xgchid = 1'b1;
5'b0_0010 : write_xgisp74 = 1'b1;
5'b0_0011 : write_xgisp30 = 1'b1;
5'b0_0100 : write_xgvbr = 1'b1;
206,10 → 210,10
5'b0_1100 : write_xgif_0 = 1'b1;
5'b0_1101 : write_xgswt = 1'b1;
5'b0_1110 : write_xgsem = 1'b1;
5'b0_1111 : write_reserv = 1'b1;
5'b0_1111 : write_reserv1 = 1'b1;
5'b1_0000 : write_xgccr = 1'b1;
5'b1_0001 : write_xgpc = 1'b1;
5'b1_0010 : write_reserv = 1'b1;
5'b1_0010 : write_reserv2 = 1'b1;
5'b1_0011 : write_xgr1 = 1'b1;
5'b1_0100 : write_xgr2 = 1'b1;
5'b1_0101 : write_xgr3 = 1'b1;
/xgate_risc.v
76,6 → 76,7
input [ 6:0] int_req, // Encoded interrupt request
input xgie, // XGATE Interrupt Enable
input brk_irq_ena, // Enable BRK instruction to generate interrupt
input write_xgchid, // Write Strobe for XGCHID register
input write_xgsem, // Write Strobe for XGSEM register
input write_xgccr, // Write Strobe for XGATE Condition Code Register
input write_xgpc, // Write Strobe for XGATE Program Counter
115,7 → 116,8
DEBUG = 4'b1000, // Stop in this state while waiting for debug commands
BOOT_1 = 4'b1001, //
BOOT_2 = 4'b1010, //
BOOT_3 = 4'b1011; //
BOOT_3 = 4'b1011, //
CHG_CHID = 4'b1100;
 
 
// Semaphore states
146,7 → 148,7
reg next_negative; // Pseudo Register,
reg next_carry; // Pseudo Register,
reg next_overflow; // Pseudo Register,
 
reg op_code_error; // Pseudo Register,
reg software_error; // OP Code error, Address Error, BRK Error
wire addr_error; // Decode Addressing error
181,7 → 183,7
reg [ 4:0] shift_ammount;
reg [15:0] shift_filler;
 
wire start_thread;
wire start_thread; // Signle to pop RISC core out of IDLE State
 
wire cpu_is_idle; // Processor is in the IDLE state
wire perif_wrt_ena; // Enable for Salve writes to CPU registers
191,9 → 193,18
reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
reg cmd_change_pc; // Debug write to PC register
 
reg [ 1:0] chid_sm_ns; // Pseudo Register,
reg [ 1:0] chid_sm; //
wire chid_goto_idle; //
 
// Debug states for change CHID
parameter [1:0] CHID_IDLE = 2'b00,
CHID_TEST = 2'b10,
CHID_WAIT = 2'b11;
 
 
assign xgate_address = data_access ? data_address : program_counter;
 
// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
 
201,7 → 212,7
assign write_mem_strb_h = data_access && data_write && (data_word_op || data_address[0]);
assign write_mem_data = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
 
assign start_thread = xge && (|int_req);
assign start_thread = xge && (|int_req) && !debug_active;
 
assign cpu_is_idle = (cpu_state == IDLE);
assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
289,9 → 300,9
if ( !async_rst_b )
software_error <= 1'b0;
else
software_error <= addr_error || op_code_error ||
software_error <= addr_error || op_code_error ||
(brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
 
assign xg_sw_irq = software_error && xgie;
 
// Latch the debug state, set by eather xgdb or BRK instructions
330,8 → 341,36
if ( !async_rst_b )
xgchid <= 7'b0;
else
xgchid <= (cpu_is_idle && mem_req_ack) ? int_req : xgchid;
xgchid <= (write_xgchid && debug_active) ? perif_data[6:0] : ((cpu_is_idle && mem_req_ack) ? int_req : xgchid);
 
// Channel Change Debug state machine register
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
chid_sm <= CHID_IDLE;
else
chid_sm <= chid_sm_ns;
 
// Channel Change Debug next state
always @*
case (chid_sm)
CHID_IDLE:
if ( write_xgchid && debug_active )
chid_sm_ns = CHID_TEST;
CHID_TEST:
if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
chid_sm_ns = CHID_IDLE;
else
chid_sm_ns = CHID_WAIT;
CHID_WAIT:
if ( (cpu_state == IDLE) || (cpu_state == CHG_CHID) )
chid_sm_ns = CHID_IDLE;
else
chid_sm_ns = CHID_WAIT;
default : chid_sm_ns = CHID_IDLE;
endcase
assign chid_goto_idle = (chid_sm == CHID_WAIT);
 
// CPU Read Data Buffer Register
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
499,6 → 538,19
load_next_inst = 1'b0;
end
 
{CHG_CHID, 16'b????????????????} :
begin
if (!xge)
next_cpu_state = IDLE;
else if (single_step || !debug_active)
next_cpu_state = BOOT_1;
else
next_cpu_state = CHG_CHID;
 
next_pc = program_counter;
load_next_inst = 1'b0;
end
 
// Output RAM address for Program Counter
{BOOT_1, 16'b????????????????} :
begin
536,7 → 588,17
 
{BREAK, 16'b????????????????} :
begin
next_cpu_state = xge ? ((single_step || !debug_active) ? BREAK_2 : BREAK) : IDLE;
if (!xge)
next_cpu_state = IDLE;
else if (single_step || !debug_active)
next_cpu_state = BREAK_2;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = BREAK;
// next_cpu_state = (xge && !chid_goto_idle) ?
// ((single_step || !debug_active) ?
// BREAK_2 : BREAK) : IDLE;
load_next_inst = 1'b0;
next_pc = program_counter;
end
557,7 → 619,20
 
{DEBUG, 16'b????????????????} :
begin
next_cpu_state = xge ? ((single_step || !debug_active) ? CONT : (cmd_change_pc ? LD_INST : DEBUG)) : IDLE;
if (!xge)
next_cpu_state = IDLE;
else if (single_step || !debug_active)
next_cpu_state = CONT;
else if (cmd_change_pc)
next_cpu_state = LD_INST;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = DEBUG;
 
// next_cpu_state = (xge && !chid_goto_idle) ?
// ((single_step || !debug_active) ?
// CONT : (cmd_change_pc ? LD_INST : DEBUG)) : IDLE;
load_next_inst = cmd_change_pc;
next_pc = program_counter;
end
1971,7 → 2046,7
next_cpu_state = DEBUG;
next_pc = program_counter;
load_next_inst = 1'b0;
op_code_error = 1'b1;
op_code_error = 1'b1;
end
endcase
end // always
/xgate_top.v
91,6 → 91,7
wire [15:0] xgisp30; // XGATE Interrupt level 3-0 stack pointer
 
wire write_xgmctl; // Write Strobe for XGMCTL register
wire write_xgchid; // Write Strobe for XGCHID register
wire write_xgisp74; // Write Strobe for XGISP74 register
wire write_xgisp31; // Write Strobe for XGISP31 register
wire write_xgvbr; // Write Strobe for XGVBR_LO register
169,6 → 170,7
// outputs
.sync_reset( sync_reset ),
.write_xgmctl( write_xgmctl ),
.write_xgchid( write_xgchid ),
.write_xgisp74( write_xgisp74 ),
.write_xgisp30( write_xgisp30 ),
.write_xgvbr( write_xgvbr ),
204,22 → 206,22
16'b0, // Reserved (XGR0)
xgate_address, // XGPC
{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
16'b0, // Reserved
16'b0, // Reserved
{8'h00, host_semap}, // XGSEM
{8'h00, xgswt}, // XGSWT
xgif[ 15: 0], // XGIF_0
xgif[ 31: 16], // XGIF_1
xgif[ 47: 32], // XGIF_2
xgif[ 63: 48], // XGIF_3
xgif[ 79: 64], // XGIF_4
xgif[ 95: 80], // XGIF_5
xgif[111: 96], // XGIF_6
xgif[127:112], // XGIF_7
{8'h00, xgswt}, // XGSWT
xgif[ 15: 0], // XGIF_0
xgif[ 31: 16], // XGIF_1
xgif[ 47: 32], // XGIF_2
xgif[ 63: 48], // XGIF_3
xgif[ 79: 64], // XGIF_4
xgif[ 95: 80], // XGIF_5
xgif[111: 96], // XGIF_6
xgif[127:112], // XGIF_7
{xgvbr[15:1], 1'b0}, // XGVBR
xgisp30, // Reserved
xgisp74, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, 2'b0, xg_sw_irq, xgie} // XGMCTL
xgisp30, // Reserved
xgisp74, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, 1'b0, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
}
)
);
269,8 → 271,6
.write_xgif_1( write_xgif_1 ),
.write_xgif_0( write_xgif_0 ),
.write_xgswt( write_xgswt )
 
);
 
// ---------------------------------------------------------------------------
314,6 → 314,7
.xgie( xgie ),
.brk_irq_ena( brk_irq_ena ),
.write_xgsem( write_xgsem ),
.write_xgchid( write_xgchid ),
.write_xgccr( write_xgccr ),
.write_xgpc( write_xgpc ),
.write_xgr7( write_xgr7 ),

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