URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
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- This comparison shows the changes necessary to convert path
/xgate/trunk/rtl/verilog
- from Rev 31 to Rev 34
- ↔ Reverse comparison
Rev 31 → Rev 34
/xgate_wbm_bus.v
57,7 → 57,9
// XGATE Control Signals |
output [DWIDTH-1:0] read_mem_data, // Data from system memory |
output mem_req_ack, // Memory bus transaction complete |
input xge, // XGATE Enabled |
input [15:0] xgate_address, // Address to system memory |
input mem_access, // |
input write_mem_strb_l, // Strobe for writing low data byte |
input write_mem_strb_h, // Strobe for writing high data bye |
input [DWIDTH-1:0] write_mem_data // Data to system memory |
64,16 → 66,12
); |
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// registers |
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// Wires |
// Wires and Registers |
wire module_sel; // This module is selected for bus transaction |
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// |
// module body |
// Module body |
// |
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// generate internal resets |
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assign wbm_dat_o = write_mem_data; |
assign read_mem_data = wbm_dat_i; |
85,8 → 83,8
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l}; |
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assign wbm_cyc_o = 1'b1; |
assign wbm_cyc_o = xge && mem_access; |
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assign wbm_stb_o = 1'b1; |
assign wbm_stb_o = xge && mem_access; |
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endmodule // xgate_wbm_bus |
/xgate_risc.v
49,6 → 49,7
output reg [15:0] xgr7, |
output [15:0] xgate_address, |
output [15:0] write_mem_data, // Data for Memory write |
output mem_access, // |
output write_mem_strb_l, // Strobe for writing low data byte |
output write_mem_strb_h, // Strobe for writing high data bye |
output reg zero_flag, |
205,6 → 206,8
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assign xgate_address = data_access ? data_address : program_counter; |
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assign mem_access = data_access || load_next_inst; |
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address. |
assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op)); |
/xgate_top.v
143,6 → 143,7
wire [15:0] xgate_address; // |
wire [15:0] write_mem_data; // |
wire [15:0] read_mem_data; // |
wire mem_access; // |
wire mem_req_ack; // |
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wire debug_active; // RISC state machine in Debug mode |
300,6 → 301,7
.xgif_status( xgif_status ), |
.debug_active( debug_active ), |
.xg_sw_irq( xg_sw_irq ), |
.mem_access( mem_access ), |
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// inputs |
.risc_clk( risc_clk ), |
365,6 → 367,8
.wbs_rst_i( wbs_rst_i ), |
.arst_i( arst_i ), |
// XGATE Control Signals |
.xge( xge ), |
.mem_access( mem_access ), |
.read_mem_data( read_mem_data ), |
.xgate_address( xgate_address ), |
.mem_req_ack( mem_req_ack ), |