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URL https://opencores.org/ocsvn/xgate/xgate/trunk

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  • This comparison shows the changes necessary to convert path 
    /xgate/trunk/rtl/verilog
    from Rev 40 to Rev 41
    ↔ Reverse comparison
  •

Rev 40 → Rev 41

/xgate_wbs_bus.v
48,7 → 48,7
input wbs_clk_i, // master clock input
input wbs_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [ 4:0] wbs_adr_i, // lower address bits
input [ 5:1] wbs_adr_i, // lower address bits
input [DWIDTH-1:0] wbs_dat_i, // databus input
input wbs_we_i, // write enable input
input wbs_stb_i, // stobe/core select signal
59,26 → 59,26
output reg write_xgchid, // Write Strobe for XGCHID register
output reg write_xgisp74,// Write Strobe for XGISP74 register
output reg write_xgisp30,// Write Strobe for XGISP30 register
output reg write_xgvbr, // Write Strobe for XGVBR register
output reg write_xgif_7, // Write Strobe for Interrupt Flag Register 7
output reg write_xgif_6, // Write Strobe for Interrupt Flag Register 6
output reg write_xgif_5, // Write Strobe for Interrupt Flag Register 5
output reg write_xgif_4, // Write Strobe for Interrupt Flag Register 4
output reg write_xgif_3, // Write Strobe for Interrupt Flag Register 3
output reg write_xgif_2, // Write Strobe for Interrupt Flag Register 2
output reg write_xgif_1, // Write Strobe for Interrupt Flag Register 1
output reg write_xgif_0, // Write Strobe for Interrupt Flag Register 0
output reg [1:0] write_xgvbr, // Write Strobe for XGVBR register
output reg [1:0] write_xgif_7, // Write Strobe for Interrupt Flag Register 7
output reg [1:0] write_xgif_6, // Write Strobe for Interrupt Flag Register 6
output reg [1:0] write_xgif_5, // Write Strobe for Interrupt Flag Register 5
output reg [1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
output reg [1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
output reg [1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
output reg [1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
output reg [1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
output reg write_xgswt, // Write Strobe for XGSWT register
output reg write_xgsem, // Write Strobe for XGSEM register
output reg write_xgccr, // Write Strobe for XGATE Condition Code Register
output reg write_xgpc, // Write Strobe for XGATE Program Counter
output reg write_xgr7, // Write Strobe for XGATE Data Register R7
output reg write_xgr6, // Write Strobe for XGATE Data Register R6
output reg write_xgr5, // Write Strobe for XGATE Data Register R5
output reg write_xgr4, // Write Strobe for XGATE Data Register R4
output reg write_xgr3, // Write Strobe for XGATE Data Register R3
output reg write_xgr2, // Write Strobe for XGATE Data Register R2
output reg write_xgr1, // Write Strobe for XGATE Data Register R1
output reg [1:0] write_xgpc, // Write Strobe for XGATE Program Counter
output reg [1:0] write_xgr7, // Write Strobe for XGATE Data Register R7
output reg [1:0] write_xgr6, // Write Strobe for XGATE Data Register R6
output reg [1:0] write_xgr5, // Write Strobe for XGATE Data Register R5
output reg [1:0] write_xgr4, // Write Strobe for XGATE Data Register R4
output reg [1:0] write_xgr3, // Write Strobe for XGATE Data Register R3
output reg [1:0] write_xgr2, // Write Strobe for XGATE Data Register R2
output reg [1:0] write_xgr1, // Write Strobe for XGATE Data Register R1
output async_rst_b, //
output sync_reset, //
input [415:0] read_regs // status register bits
171,56 → 171,55
write_xgchid = 1'b0;
write_xgisp74 = 1'b0;
write_xgisp30 = 1'b0;
write_xgvbr = 1'b0;
write_xgif_7 = 1'b0;
write_xgif_6 = 1'b0;
write_xgif_5 = 1'b0;
write_xgif_4 = 1'b0;
write_xgif_3 = 1'b0;
write_xgif_2 = 1'b0;
write_xgif_1 = 1'b0;
write_xgif_0 = 1'b0;
write_xgif_7 = 1'b0;
write_xgvbr = 2'b00;
write_xgif_7 = 2'b00;
write_xgif_6 = 2'b00;
write_xgif_5 = 2'b00;
write_xgif_4 = 2'b00;
write_xgif_3 = 2'b00;
write_xgif_2 = 2'b00;
write_xgif_1 = 2'b00;
write_xgif_0 = 2'b00;
write_xgswt = 1'b0;
write_xgsem = 1'b0;
write_xgccr = 1'b0;
write_xgpc = 1'b0;
write_xgr7 = 1'b0;
write_xgr6 = 1'b0;
write_xgr5 = 1'b0;
write_xgr4 = 1'b0;
write_xgr3 = 1'b0;
write_xgr2 = 1'b0;
write_xgr1 = 1'b0;
write_xgpc = 2'b00;
write_xgr7 = 2'b00;
write_xgr6 = 2'b00;
write_xgr5 = 2'b00;
write_xgr4 = 2'b00;
write_xgr3 = 2'b00;
write_xgr2 = 2'b00;
write_xgr1 = 2'b00;
if (wbs_wacc)
case (wbs_adr_i) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
5'b0_0000 : write_xgmctl = 1'b1;
5'b0_0001 : write_xgchid = 1'b1;
// 16 bit Bus, 8 bit Granularity
5'b0_0000 : write_xgmctl = &wbs_sel_i;
5'b0_0001 : write_xgchid = wbs_sel_i[0];
5'b0_0010 : write_xgisp74 = 1'b1;
5'b0_0011 : write_xgisp30 = 1'b1;
5'b0_0100 : write_xgvbr = 1'b1;
5'b0_0101 : write_xgif_7 = 1'b1;
5'b0_0110 : write_xgif_6 = 1'b1;
5'b0_0111 : write_xgif_5 = 1'b1;
5'b0_1000 : write_xgif_4 = 1'b1;
5'b0_1001 : write_xgif_3 = 1'b1;
5'b0_1010 : write_xgif_2 = 1'b1;
5'b0_1011 : write_xgif_1 = 1'b1;
5'b0_1100 : write_xgif_0 = 1'b1;
5'b0_1101 : write_xgswt = 1'b1;
5'b0_1110 : write_xgsem = 1'b1;
5'b0_0100 : write_xgvbr = wbs_sel_i;
5'b0_0101 : write_xgif_7 = wbs_sel_i;
5'b0_0110 : write_xgif_6 = wbs_sel_i;
5'b0_0111 : write_xgif_5 = wbs_sel_i;
5'b0_1000 : write_xgif_4 = wbs_sel_i;
5'b0_1001 : write_xgif_3 = wbs_sel_i;
5'b0_1010 : write_xgif_2 = wbs_sel_i;
5'b0_1011 : write_xgif_1 = wbs_sel_i;
5'b0_1100 : write_xgif_0 = wbs_sel_i;
5'b0_1101 : write_xgswt = &wbs_sel_i;
5'b0_1110 : write_xgsem = &wbs_sel_i;
5'b0_1111 : write_reserv1 = 1'b1;
5'b1_0000 : write_xgccr = 1'b1;
5'b1_0001 : write_xgpc = 1'b1;
5'b1_0000 : write_xgccr = wbs_sel_i[0];
5'b1_0001 : write_xgpc = wbs_sel_i;
5'b1_0010 : write_reserv2 = 1'b1;
5'b1_0011 : write_xgr1 = 1'b1;
5'b1_0100 : write_xgr2 = 1'b1;
5'b1_0101 : write_xgr3 = 1'b1;
5'b1_0110 : write_xgr4 = 1'b1;
5'b1_0111 : write_xgr5 = 1'b1;
5'b1_1000 : write_xgr6 = 1'b1;
5'b1_1001 : write_xgr7 = 1'b1;
5'b1_0011 : write_xgr1 = wbs_sel_i;
5'b1_0100 : write_xgr2 = wbs_sel_i;
5'b1_0101 : write_xgr3 = wbs_sel_i;
5'b1_0110 : write_xgr4 = wbs_sel_i;
5'b1_0111 : write_xgr5 = wbs_sel_i;
5'b1_1000 : write_xgr6 = wbs_sel_i;
5'b1_1001 : write_xgr7 = wbs_sel_i;
default: ;
endcase
end
/xgate_regs.v
72,15 → 72,15
input write_xgmctl, // Write Strobe for XGMCTL register
input write_xgisp74, // Write Strobe for XGISP74 register
input write_xgisp30, // Write Strobe for XGISP30 register
input write_xgvbr, // Write Strobe for XGVBR register
input write_xgif_7, // Write Strobe for Interrupt Flag Register 7
input write_xgif_6, // Write Strobe for Interrupt Flag Register 6
input write_xgif_5, // Write Strobe for Interrupt Flag Register 5
input write_xgif_4, // Write Strobe for Interrupt Flag Register 4
input write_xgif_3, // Write Strobe for Interrupt Flag Register 3
input write_xgif_2, // Write Strobe for Interrupt Flag Register 2
input write_xgif_1, // Write Strobe for Interrupt Flag Register 1
input write_xgif_0, // Write Strobe for Interrupt Flag Register 0
input [ 1:0] write_xgvbr, // Write Strobe for XGVBR register
input [ 1:0] write_xgif_7, // Write Strobe for Interrupt Flag Register 7
input [ 1:0] write_xgif_6, // Write Strobe for Interrupt Flag Register 6
input [ 1:0] write_xgif_5, // Write Strobe for Interrupt Flag Register 5
input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
input [ 1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
input write_xgswt // Write Strobe for XGSWT register
);
 
88,7 → 88,7
// registers
 
// Wires
wire write_any_xgif;
wire [ 1:0] write_any_xgif;
 
//
// module body
152,9 → 152,10
begin
xgvbr <= 15'b1111_1110_0000_000;
end
else if (write_xgvbr)
else if (|write_xgvbr && !xge)
begin
xgvbr[15: 1] <= xge ? 15'b0 : write_bus[15:1];
xgvbr[15:8] <= write_xgvbr[1] ? write_bus[15:8] : xgvbr[15:8];
xgvbr[ 7:1] <= write_xgvbr[0] ? write_bus[ 7:1] : xgvbr[ 7:1];
end
 
// XGISP74 Register
176,8 → 177,8
xgisp30 <= xge ? xgisp30 : write_bus;
 
// XGIF 7-0 Registers
assign write_any_xgif = write_xgif_7 || write_xgif_6 || write_xgif_5 || write_xgif_4 ||
write_xgif_3 || write_xgif_2 || write_xgif_1 || write_xgif_0;
assign write_any_xgif = write_xgif_7 | write_xgif_6 | write_xgif_5 | write_xgif_4 |
write_xgif_3 | write_xgif_2 | write_xgif_1 | write_xgif_0;
 
// Registers to clear the interrupt flags. Decode a specific interrupt to
// clear by ANDing the clear_xgif_x signal with the clear_xgif_data.
208,15 → 209,16
end
else
begin
clear_xgif_7 <= write_xgif_7 && (MAX_CHANNEL > 111);
clear_xgif_6 <= write_xgif_6 && (MAX_CHANNEL > 95);
clear_xgif_5 <= write_xgif_5 && (MAX_CHANNEL > 79);
clear_xgif_4 <= write_xgif_4 && (MAX_CHANNEL > 63);
clear_xgif_3 <= write_xgif_3 && (MAX_CHANNEL > 47);
clear_xgif_2 <= write_xgif_2 && (MAX_CHANNEL > 31);
clear_xgif_1 <= write_xgif_1 && (MAX_CHANNEL > 15);
clear_xgif_0 <= write_xgif_0;
clear_xgif_data <= write_any_xgif ? write_bus : clear_xgif_data;
clear_xgif_7 <= |write_xgif_7 && (MAX_CHANNEL > 111);
clear_xgif_6 <= |write_xgif_6 && (MAX_CHANNEL > 95);
clear_xgif_5 <= |write_xgif_5 && (MAX_CHANNEL > 79);
clear_xgif_4 <= |write_xgif_4 && (MAX_CHANNEL > 63);
clear_xgif_3 <= |write_xgif_3 && (MAX_CHANNEL > 47);
clear_xgif_2 <= |write_xgif_2 && (MAX_CHANNEL > 31);
clear_xgif_1 <= |write_xgif_1 && (MAX_CHANNEL > 15);
clear_xgif_0 <= |write_xgif_0;
clear_xgif_data[15:8] <= write_any_xgif[1] ? write_bus[15:8] : 8'b0;
clear_xgif_data[ 7:0] <= write_any_xgif[0] ? write_bus[ 7:0] : 8'b0;
end
 
 
/xgate_risc.v
69,7 → 69,6
input async_rst_b,
input mem_req_ack, // Memory Bus available - data good
input xge, // XGATE Module Enable
input xgfrz, // Stop XGATE in Freeze Mode
input debug_mode_i, // Force RISC core into debug mode
input xgdbg_set, // Enter XGATE Debug Mode
input xgdbg_clear, // Leave XGATE Debug Mode
81,14 → 80,14
input write_xgchid, // Write Strobe for XGCHID register
input write_xgsem, // Write Strobe for XGSEM register
input write_xgccr, // Write Strobe for XGATE Condition Code Register
input write_xgpc, // Write Strobe for XGATE Program Counter
input write_xgr7, // Write Strobe for XGATE Data Register R7
input write_xgr6, // Write Strobe for XGATE Data Register R6
input write_xgr5, // Write Strobe for XGATE Data Register R5
input write_xgr4, // Write Strobe for XGATE Data Register R4
input write_xgr3, // Write Strobe for XGATE Data Register R3
input write_xgr2, // Write Strobe for XGATE Data Register R2
input write_xgr1, // Write Strobe for XGATE Data Register R1
input [ 1:0] write_xgpc, // Write Strobe for XGATE Program Counter
input [ 1:0] write_xgr7, // Write Strobe for XGATE Data Register R7
input [ 1:0] write_xgr6, // Write Strobe for XGATE Data Register R6
input [ 1:0] write_xgr5, // Write Strobe for XGATE Data Register R5
input [ 1:0] write_xgr4, // Write Strobe for XGATE Data Register R4
input [ 1:0] write_xgr3, // Write Strobe for XGATE Data Register R3
input [ 1:0] write_xgr2, // Write Strobe for XGATE Data Register R2
input [ 1:0] write_xgr1, // Write Strobe for XGATE Data Register R1
input xgsweif_c, // Clear Software Flag
input clear_xgif_7, // Strobe for decode to clear interrupt flag bank 7
input clear_xgif_6, // Strobe for decode to clear interrupt flag bank 6
395,7 → 394,10
if ( !async_rst_b )
program_counter <= 16'h0000;
else
program_counter <= (write_xgpc && perif_wrt_ena) ? perif_data : (mem_req_ack ? next_pc : program_counter);
program_counter <= (|write_xgpc && perif_wrt_ena) ?
{(write_xgpc[1] ? perif_data[15:8]: program_counter[15:8]),
(write_xgpc[0] ? perif_data[ 7:0]: program_counter[ 7:0])} :
(mem_req_ack ? next_pc : program_counter);
 
// Debug Change Program Counter Register
always @(posedge risc_clk or negedge async_rst_b)
402,7 → 404,7
if ( !async_rst_b )
cmd_change_pc <= 1'b0;
else
cmd_change_pc <= write_xgpc && perif_wrt_ena;
cmd_change_pc <= |write_xgpc && perif_wrt_ena;
 
// ALU Flag Bits
always @(posedge risc_clk or negedge async_rst_b)
471,25 → 473,39
end
else
begin
xgr1 <= (write_xgr1 && perif_wrt_ena) ? perif_data :
xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
{(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
(write_xgr1[0] ? perif_data[ 7:0]: xgr1[ 7:0])} :
{((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
((wrt_sel_xgr1 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr1[ 7:0])};
xgr2 <= (write_xgr2 && perif_wrt_ena) ? perif_data :
xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
{(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
(write_xgr2[0] ? perif_data[ 7:0]: xgr2[ 7:0])} :
{((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
((wrt_sel_xgr2 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr2[ 7:0])};
xgr3 <= (write_xgr3 && perif_wrt_ena) ? perif_data :
xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
{(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
(write_xgr3[0] ? perif_data[ 7:0]: xgr3[ 7:0])} :
{((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
((wrt_sel_xgr3 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr3[ 7:0])};
xgr4 <= (write_xgr4 && perif_wrt_ena) ? perif_data :
xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
{(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
(write_xgr4[0] ? perif_data[ 7:0]: xgr4[ 7:0])} :
{((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
((wrt_sel_xgr4 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr4[ 7:0])};
xgr5 <= (write_xgr5 && perif_wrt_ena) ? perif_data :
xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
{(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
(write_xgr5[0] ? perif_data[ 7:0]: xgr5[ 7:0])} :
{((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
((wrt_sel_xgr5 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr5[ 7:0])};
xgr6 <= (write_xgr6 && perif_wrt_ena) ? perif_data :
xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
{(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
(write_xgr6[0] ? perif_data[ 7:0]: xgr6[ 7:0])} :
{((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
((wrt_sel_xgr6 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr6[ 7:0])};
xgr7 <= (write_xgr7 && perif_wrt_ena) ? perif_data :
xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
{(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
(write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
end
/xgate_top.v
49,7 → 49,7
input wbs_clk_i, // master clock input
input wbs_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [4:0] wbs_adr_i, // lower address bits
input [5:1] wbs_adr_i, // lower address bits
input [DWIDTH-1:0] wbs_dat_i, // databus input
input wbs_we_i, // write enable input
input wbs_stb_i, // stobe/core select signal
96,26 → 96,26
wire write_xgchid; // Write Strobe for XGCHID register
wire write_xgisp74; // Write Strobe for XGISP74 register
wire write_xgisp30; // Write Strobe for XGISP30 register
wire write_xgvbr; // Write Strobe for XGVBR_LO register
wire write_xgif_7; // Write Strobe for Interrupt Flag Register 7
wire write_xgif_6; // Write Strobe for Interrupt Flag Register 6
wire write_xgif_5; // Write Strobe for Interrupt Flag Register 5
wire write_xgif_4; // Write Strobe for Interrupt Flag Register 4
wire write_xgif_3; // Write Strobe for Interrupt Flag Register 3
wire write_xgif_2; // Write Strobe for Interrupt Flag Register 2
wire write_xgif_1; // Write Strobe for Interrupt Flag Register 1
wire write_xgif_0; // Write Strobe for Interrupt Flag Register 0
wire [1:0] write_xgvbr; // Write Strobe for XGVBR register
wire [1:0] write_xgif_7; // Write Strobe for Interrupt Flag Register 7
wire [1:0] write_xgif_6; // Write Strobe for Interrupt Flag Register 6
wire [1:0] write_xgif_5; // Write Strobe for Interrupt Flag Register 5
wire [1:0] write_xgif_4; // Write Strobe for Interrupt Flag Register 4
wire [1:0] write_xgif_3; // Write Strobe for Interrupt Flag Register 3
wire [1:0] write_xgif_2; // Write Strobe for Interrupt Flag Register 2
wire [1:0] write_xgif_1; // Write Strobe for Interrupt Flag Register 1
wire [1:0] write_xgif_0; // Write Strobe for Interrupt Flag Register 0
wire write_xgswt; // Write Strobe for XGSWT register
wire write_xgsem; // Write Strobe for XGSEM register
wire write_xgccr; // Write Strobe for XGATE Condition Code Register
wire write_xgpc; // Write Strobe for XGATE Program Counter
wire write_xgr7; // Write Strobe for XGATE Data Register R7
wire write_xgr6; // Write Strobe for XGATE Data Register R6
wire write_xgr5; // Write Strobe for XGATE Data Register R5
wire write_xgr4; // Write Strobe for XGATE Data Register R4
wire write_xgr3; // Write Strobe for XGATE Data Register R3
wire write_xgr2; // Write Strobe for XGATE Data Register R2
wire write_xgr1; // Write Strobe for XGATE Data Register R1
wire [1:0] write_xgpc; // Write Strobe for XGATE Program Counter
wire [1:0] write_xgr7; // Write Strobe for XGATE Data Register R7
wire [1:0] write_xgr6; // Write Strobe for XGATE Data Register R6
wire [1:0] write_xgr5; // Write Strobe for XGATE Data Register R5
wire [1:0] write_xgr4; // Write Strobe for XGATE Data Register R4
wire [1:0] write_xgr3; // Write Strobe for XGATE Data Register R3
wire [1:0] write_xgr2; // Write Strobe for XGATE Data Register R2
wire [1:0] write_xgr1; // Write Strobe for XGATE Data Register R1
 
wire clear_xgif_7; // Strobe for decode to clear interrupt flag bank 7
wire clear_xgif_6; // Strobe for decode to clear interrupt flag bank 6
131,6 → 131,7
wire xgfrz; // Stop XGATE in Freeze Mode
wire xgdbg_set; // Enter XGATE Debug Mode
wire xgdbg_clear; // Leave XGATE Debug Mode
wire xgfact; // Fake Activity
wire xgss; // XGATE Single Step
wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
wire xgie; // XGATE Interrupt Enable
225,7 → 226,7
xgisp30, // Reserved
xgisp74, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, 1'b0, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
}
)
);
239,6 → 240,7
.xgfrz( xgfrz ),
.xgdbg_set( xgdbg_set ),
.xgdbg_clear( xgdbg_clear ),
.xgfact( xgfact ),
.xgss( xgss ),
.xgsweif_c( xgsweif_c ),
.xgie( xgie ),
310,7 → 312,6
.read_mem_data( read_mem_data ),
.mem_req_ack( mem_req_ack ),
.xge( xge ),
.xgfrz( xgfrz ),
.xgdbg_set( xgdbg_set ),
.xgdbg_clear( xgdbg_clear ),
.debug_mode_i(debug_mode_i),

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