OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xgate/trunk/rtl/verilog
    from Rev 47 to Rev 53
    ↔ Reverse comparison
  •

Rev 47 → Rev 53

/xgate_wbs_bus.v
45,6 → 45,7
// Wishbone Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output
output wbs_ack_o, // bus cycle acknowledge output
output wbs_err_o, // bus error, lost module select durning wait state
input wbs_clk_i, // master clock input
input wbs_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
110,8 → 111,9
assign module_sel = wbs_cyc_i && wbs_stb_i;
assign wbs_wacc = module_sel && wbs_we_i && (wbs_ack_o || SINGLE_CYCLE);
assign wbs_racc = module_sel && !wbs_we_i;
assign wbs_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state;
assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
assign wbs_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state;
 
// generate acknowledge output signal, By using register all accesses takes two cycles.
// Accesses in back to back clock cycles are not possable.
/xgate_wbm_bus.v
57,7 → 57,11
// XGATE Control Signals
output [DWIDTH-1:0] read_mem_data, // Data from system memory
output mem_req_ack, // Memory bus transaction complete
input risc_clk, //
input async_rst_b, //
input xge, // XGATE Enabled
input single_step, // Pulse to trigger a single instruction execution in debug mode
output ss_mem_ack, // WISHBONE Bus has granted single step memory access
input [15:0] xgate_address, // Address to system memory
input mem_access, //
input write_mem_strb_l, // Strobe for writing low data byte
68,11 → 72,22
 
// Wires and Registers
wire module_sel; // This module is selected for bus transaction
reg ss_mem_req; // Bus request for single step memory access
 
//
// Module body
//
// Latch Single Step Request and ask for memory access
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
ss_mem_req <= 1'b0;
else
ss_mem_req <= (single_step || ss_mem_req) && !wbm_ack_i && xge;
assign ss_mem_ack = ss_mem_req && wbm_ack_i;
 
assign wbm_dat_o = write_mem_data;
assign read_mem_data = wbm_dat_i;
assign wbm_adr_o = xgate_address;
83,8 → 98,8
assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
assign wbm_cyc_o = xge && mem_access;
assign wbm_cyc_o = xge && (mem_access || ss_mem_req);
assign wbm_stb_o = xge && mem_access;
assign wbm_stb_o = xge && (mem_access || ss_mem_req);
 
endmodule // xgate_wbm_bus
/xgate_regs.v
77,7 → 77,8
input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
input write_xgswt // Write Strobe for XGSWT register
input write_xgswt, // Write Strobe for XGSWT register
input debug_ack // Clear debug register
);
 
 
134,7 → 135,7
begin
xgss <= 1'b0;
xgsweif_c <= 1'b0;
xgdbg_set <= 1'b0;
xgdbg_set <= xgdbg_set && !debug_ack;
xgdbg_clear <= 1'b0;
end
 
/xgate_risc.v
61,6 → 61,8
output xg_sw_irq, // Xgate Software interrupt
output [ 7:0] host_semap, // Semaphore status for host
output reg debug_active, // Latch to control debug mode in the RISC state machine
output debug_ack, // Clear debug register
output single_step, // Pulse to trigger a single instruction execution in debug mode
 
 
input [15:0] read_mem_data,
68,9 → 70,10
input risc_clk,
input async_rst_b,
input mem_req_ack, // Memory Bus available - data good
input ss_mem_ack, // WISHBONE Bus has granted single step memory access
input xge, // XGATE Module Enable
input debug_mode_i, // Force RISC core into debug mode
input xgdbg_set, // Enter XGATE Debug Mode
input xgdbg_set, // Enter XGATE Debug Mode, pulse
input xgdbg_clear, // Leave XGATE Debug Mode
input xgss, // XGATE Single Step
input [15:1] xgvbr, // XGATE vector Base Address Register
188,6 → 191,7
reg shift_left;
reg [ 4:0] shift_ammount;
reg [15:0] shift_filler;
reg [15:0] bf_mux_mask; // Mask for controlling mux's in Bit Field Insert Instructions
 
wire start_thread; // Signle to pop RISC core out of IDLE State
 
195,9 → 199,9
wire perif_wrt_ena; // Enable for Salve writes to CPU registers
 
reg xgss_edge; // Flop for edge detection
wire single_step; // Pulse to trigger a single instruction execution in debug mode
reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
reg cmd_change_pc; // Debug write to PC register
reg debug_edge; // Reg for edge detection
 
reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
reg [ 1:0] chid_sm; //
214,7 → 218,9
 
assign xgate_address = data_access ? data_address : program_counter;
assign mem_access = data_access || load_next_inst;
//assign mem_access = data_access || load_next_inst || (start_thread);
assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
(cpu_state == BREAK_2) || (start_thread);
 
// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
284,7 → 290,6
default : rs2_data = 16'h0; // XGR0 is always Zero
endcase
 
reg [15:0] bf_mux_mask; // Mask for controlling mux's in Bit Field Insert Instructions
// Decode mux select mask for Bit Field Insert Instructions
always @*
begin
311,9 → 316,17
// Latch the debug state, set by eather xgdb or BRK instructions
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
begin
debug_active <= 1'b0;
debug_edge <= 0;
end
else
debug_active <= !xgdbg_clear && (xgdbg_set || brk_set_dbg || op_code_error || debug_active);
begin
debug_active <= !xgdbg_clear && ((xgdbg_set && mem_req_ack && (next_cpu_state == CONT)) || brk_set_dbg || op_code_error || debug_active);
debug_edge <= debug_active;
end
assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
 
// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
always @(posedge risc_clk or negedge async_rst_b)
322,7 → 335,7
else
xgss_edge <= xgss;
 
assign single_step = xgss && !xgss_edge;
assign single_step = (xgss && !xgss_edge) || (!debug_active && debug_edge);
 
 
// CPU State Register
330,7 → 343,7
if ( !async_rst_b )
cpu_state <= IDLE;
else
cpu_state <= mem_req_ack ? next_cpu_state : cpu_state;
cpu_state <= (mem_req_ack || (chid_sm != CHID_IDLE)) ? next_cpu_state : cpu_state;
 
// CPU Instruction Register
always @(posedge risc_clk or negedge async_rst_b)
396,7 → 409,7
if ( !async_rst_b )
cmd_change_pc <= 1'b0;
else
cmd_change_pc <= |write_xgpc && perif_wrt_ena;
cmd_change_pc <= (|write_xgpc && perif_wrt_ena) || (cmd_change_pc && !mem_req_ack);
 
// ALU Flag Bits
always @(posedge risc_clk or negedge async_rst_b)
564,7 → 577,7
begin
if (!xge)
next_cpu_state = IDLE;
else if (single_step || !debug_active)
else if (ss_mem_ack || !debug_active)
next_cpu_state = BOOT_1;
else
next_cpu_state = CHG_CHID;
613,7 → 626,7
begin
if (!xge)
next_cpu_state = IDLE;
else if (single_step || !debug_active)
else if (ss_mem_ack || !debug_active)
next_cpu_state = BREAK_2;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
641,7 → 654,7
begin
if (!xge)
next_cpu_state = IDLE;
else if (single_step || !debug_active)
else if (ss_mem_ack || !debug_active)
next_cpu_state = CONT;
else if (cmd_change_pc)
next_cpu_state = LD_INST;
/xgate_top.v
46,6 → 46,7
// Wishbone Slave Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output
output wbs_ack_o, // bus cycle acknowledge output
output wbs_err_o, // bus error, lost module select durning wait state
input wbs_clk_i, // master clock input
input wbs_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
143,6 → 144,9
wire mem_req_ack; //
 
wire debug_active; // RISC state machine in Debug mode
wire debug_ack; // Clear debug register
wire single_step; // Pulse to trigger a single instruction execution in debug mode
wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
wire [ 7:0] host_semap; // Semaphore status for host
// wire [15:0] write_mem_data;
157,6 → 161,7
wishbone_s(
.wbs_dat_o( wbs_dat_o ),
.wbs_ack_o( wbs_ack_o ),
.wbs_err_o( wbs_err_o ),
.wbs_clk_i( wbs_clk_i ),
.wbs_rst_i( wbs_rst_i ),
.arst_i( arst_i ),
265,7 → 270,8
.write_xgif_2( write_xgif_2 ),
.write_xgif_1( write_xgif_1 ),
.write_xgif_0( write_xgif_0 ),
.write_xgswt( write_xgswt )
.write_xgswt( write_xgswt ),
.debug_ack( debug_ack )
);
 
// ---------------------------------------------------------------------------
291,8 → 297,10
.xgr7( xgr7 ),
.xgif_status( xgif_status ),
.debug_active( debug_active ),
.debug_ack( debug_ack ),
.xg_sw_irq( xg_sw_irq ),
.mem_access( mem_access ),
.single_step( single_step ),
// inputs
.risc_clk( risc_clk ),
300,6 → 308,7
.async_rst_b( async_rst_b ),
.read_mem_data( read_mem_data ),
.mem_req_ack( mem_req_ack ),
.ss_mem_ack( ss_mem_ack ),
.xge( xge ),
.xgdbg_set( xgdbg_set ),
.xgdbg_clear( xgdbg_clear ),
357,8 → 366,12
.wbs_rst_i( wbs_rst_i ),
.arst_i( arst_i ),
// XGATE Control Signals
.risc_clk( risc_clk ),
.async_rst_b( async_rst_b ),
.xge( xge ),
.mem_access( mem_access ),
.single_step( single_step ),
.ss_mem_ack( ss_mem_ack ),
.read_mem_data( read_mem_data ),
.xgate_address( xgate_address ),
.mem_req_ack( mem_req_ack ),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.