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    /xgate/trunk/rtl/verilog
    from Rev 88 to Rev 89
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Rev 88 → Rev 89

/xgate_wbs_bus.v
39,9 → 39,9
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_wbs_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter DWIDTH = 16,
parameter WB_RD_DEFAULT = 0, // WISHBONE Read Bus default state
parameter SINGLE_CYCLE = 1'b0)
parameter DWIDTH = 16,
parameter WB_RD_DEFAULT = 0, // WISHBONE Read Bus default state
parameter SINGLE_CYCLE = 1'b0)
(
// Wishbone Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output - Pseudo Register
98,11 → 98,11
 
// registers
reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
reg [5:0] addr_latch; // Capture WISHBONE Address
reg [5:0] addr_latch; // Capture WISHBONE Address
 
reg write_reserv1; // Dummy Reg decode for Reserved address
reg write_reserv2; // Dummy Reg decode for Reserved address
 
reg [DWIDTH-1:0] read_mux_irq; // Psudo register for WISHBONE IRQ read data bus mux
 
// Wires
110,9 → 110,9
wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal)
wire wbs_racc; // WISHBONE Read Access (Clock gating signal)
wire [5:0] address; // Select either direct or latched address
reg [DWIDTH-1:0] read_mux_risc; // Pseudo regester for WISHBONE RISC read data bus mux
 
reg [DWIDTH-1:0] read_mux_risc; // Pseudo regester for WISHBONE RISC read data bus mux
 
//
// module body
//
128,7 → 128,7
assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state;
assign address = SINGLE_CYCLE ? wbs_adr_i : addr_latch;
 
assign wbs_dat_o = read_mux_risc | read_mux_irq;
 
// generate acknowledge output signal, By using register all accesses takes two cycles.
146,41 → 146,41
always @(posedge wbs_clk_i)
if ( module_sel ) // Clock gate for power saving
addr_latch <= wbs_adr_i;
 
// WISHBONE Read Data Mux for RISC status and control registers
always @*
case ({wbs_racc, address}) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
7'b100_0000: read_mux_risc = read_risc_regs[ 15: 0];
7'b100_0001: read_mux_risc = read_risc_regs[ 31: 16];
7'b100_0010: read_mux_risc = read_risc_regs[ 47: 32];
7'b100_0011: read_mux_risc = read_risc_regs[ 63: 48];
7'b100_0100: read_mux_risc = read_risc_regs[ 79: 64];
7'b100_0101: read_mux_risc = read_risc_regs[ 95: 80];
7'b100_0110: read_mux_risc = read_risc_regs[111: 96];
7'b100_0111: read_mux_risc = read_risc_regs[127:112];
7'b100_1000: read_mux_risc = read_risc_regs[143:128];
7'b100_1001: read_mux_risc = read_risc_regs[159:144];
7'b100_1010: read_mux_risc = read_risc_regs[175:160];
7'b100_1011: read_mux_risc = read_risc_regs[191:176];
7'b100_1100: read_mux_risc = read_risc_regs[207:192];
7'b100_1101: read_mux_risc = read_risc_regs[223:208];
7'b100_1110: read_mux_risc = read_risc_regs[239:224];
7'b100_1111: read_mux_risc = read_risc_regs[255:240];
7'b101_0000: read_mux_risc = read_risc_regs[271:256];
7'b101_0001: read_mux_risc = read_risc_regs[287:272];
7'b101_0010: read_mux_risc = read_risc_regs[303:288];
7'b101_0011: read_mux_risc = read_risc_regs[319:304];
7'b101_0100: read_mux_risc = read_risc_regs[335:320];
7'b101_0101: read_mux_risc = read_risc_regs[351:336];
7'b101_0110: read_mux_risc = read_risc_regs[367:352];
7'b101_0111: read_mux_risc = read_risc_regs[383:368];
7'b101_1000: read_mux_risc = read_risc_regs[399:384];
7'b101_1001: read_mux_risc = read_risc_regs[415:400];
default: read_mux_risc = {DWIDTH{WB_RD_DEFAULT}};
// 16 bit Bus, 16 bit Granularity
7'b100_0000: read_mux_risc = read_risc_regs[ 15: 0];
7'b100_0001: read_mux_risc = read_risc_regs[ 31: 16];
7'b100_0010: read_mux_risc = read_risc_regs[ 47: 32];
7'b100_0011: read_mux_risc = read_risc_regs[ 63: 48];
7'b100_0100: read_mux_risc = read_risc_regs[ 79: 64];
7'b100_0101: read_mux_risc = read_risc_regs[ 95: 80];
7'b100_0110: read_mux_risc = read_risc_regs[111: 96];
7'b100_0111: read_mux_risc = read_risc_regs[127:112];
7'b100_1000: read_mux_risc = read_risc_regs[143:128];
7'b100_1001: read_mux_risc = read_risc_regs[159:144];
7'b100_1010: read_mux_risc = read_risc_regs[175:160];
7'b100_1011: read_mux_risc = read_risc_regs[191:176];
7'b100_1100: read_mux_risc = read_risc_regs[207:192];
7'b100_1101: read_mux_risc = read_risc_regs[223:208];
7'b100_1110: read_mux_risc = read_risc_regs[239:224];
7'b100_1111: read_mux_risc = read_risc_regs[255:240];
7'b101_0000: read_mux_risc = read_risc_regs[271:256];
7'b101_0001: read_mux_risc = read_risc_regs[287:272];
7'b101_0010: read_mux_risc = read_risc_regs[303:288];
7'b101_0011: read_mux_risc = read_risc_regs[319:304];
7'b101_0100: read_mux_risc = read_risc_regs[335:320];
7'b101_0101: read_mux_risc = read_risc_regs[351:336];
7'b101_0110: read_mux_risc = read_risc_regs[367:352];
7'b101_0111: read_mux_risc = read_risc_regs[383:368];
7'b101_1000: read_mux_risc = read_risc_regs[399:384];
7'b101_1001: read_mux_risc = read_risc_regs[415:400];
default: read_mux_risc = {DWIDTH{WB_RD_DEFAULT}};
endcase
 
// generate wishbone write register strobes for Xgate RISC
// generate wishbone write register strobes for Xgate RISC
always @*
begin
write_reserv1 = 1'b0;
210,51 → 210,51
write_xgr2 = 2'b00;
write_xgr1 = 2'b00;
if (wbs_wacc)
case (address) // synopsys parallel_case
case (address) // synopsys parallel_case
// 16 bit Bus, 8 bit Granularity
6'b00_0000 : write_xgmctl = &wbs_sel_i;
6'b00_0001 : write_xgchid = wbs_sel_i[0];
6'b00_0010 : write_xgisp74 = 1'b1;
6'b00_0011 : write_xgisp30 = 1'b1;
6'b00_0100 : write_xgvbr = wbs_sel_i;
6'b00_0101 : write_xgif_7 = wbs_sel_i;
6'b00_0110 : write_xgif_6 = wbs_sel_i;
6'b00_0111 : write_xgif_5 = wbs_sel_i;
6'b00_1000 : write_xgif_4 = wbs_sel_i;
6'b00_1001 : write_xgif_3 = wbs_sel_i;
6'b00_1010 : write_xgif_2 = wbs_sel_i;
6'b00_1011 : write_xgif_1 = wbs_sel_i;
6'b00_1100 : write_xgif_0 = wbs_sel_i;
6'b00_1101 : write_xgswt = &wbs_sel_i;
6'b00_1110 : write_xgsem = &wbs_sel_i;
6'b00_1111 : write_reserv1 = 1'b1;
6'b01_0000 : write_xgccr = wbs_sel_i[0];
6'b01_0001 : write_xgpc = wbs_sel_i;
6'b01_0010 : write_reserv2 = 1'b1;
6'b01_0011 : write_xgr1 = wbs_sel_i;
6'b01_0100 : write_xgr2 = wbs_sel_i;
6'b01_0101 : write_xgr3 = wbs_sel_i;
6'b01_0110 : write_xgr4 = wbs_sel_i;
6'b01_0111 : write_xgr5 = wbs_sel_i;
6'b01_1000 : write_xgr6 = wbs_sel_i;
6'b01_1001 : write_xgr7 = wbs_sel_i;
default: ;
endcase
6'b00_0000 : write_xgmctl = &wbs_sel_i;
6'b00_0001 : write_xgchid = wbs_sel_i[0];
6'b00_0010 : write_xgisp74 = 1'b1;
6'b00_0011 : write_xgisp30 = 1'b1;
6'b00_0100 : write_xgvbr = wbs_sel_i;
6'b00_0101 : write_xgif_7 = wbs_sel_i;
6'b00_0110 : write_xgif_6 = wbs_sel_i;
6'b00_0111 : write_xgif_5 = wbs_sel_i;
6'b00_1000 : write_xgif_4 = wbs_sel_i;
6'b00_1001 : write_xgif_3 = wbs_sel_i;
6'b00_1010 : write_xgif_2 = wbs_sel_i;
6'b00_1011 : write_xgif_1 = wbs_sel_i;
6'b00_1100 : write_xgif_0 = wbs_sel_i;
6'b00_1101 : write_xgswt = &wbs_sel_i;
6'b00_1110 : write_xgsem = &wbs_sel_i;
6'b00_1111 : write_reserv1 = 1'b1;
6'b01_0000 : write_xgccr = wbs_sel_i[0];
6'b01_0001 : write_xgpc = wbs_sel_i;
6'b01_0010 : write_reserv2 = 1'b1;
6'b01_0011 : write_xgr1 = wbs_sel_i;
6'b01_0100 : write_xgr2 = wbs_sel_i;
6'b01_0101 : write_xgr3 = wbs_sel_i;
6'b01_0110 : write_xgr4 = wbs_sel_i;
6'b01_0111 : write_xgr5 = wbs_sel_i;
6'b01_1000 : write_xgr6 = wbs_sel_i;
6'b01_1001 : write_xgr7 = wbs_sel_i;
default: ;
endcase
end
 
// WISHBONE Read Data Mux for IRQ control registers
always @*
case ({wbs_racc, address}) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
7'b110_0000: read_mux_irq = {irq_bypass[ 15: 1], 1'b0};
7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
7'b110_0110: read_mux_irq = irq_bypass[111: 96];
7'b110_0111: read_mux_irq = irq_bypass[127:112];
default: read_mux_irq = {DWIDTH{WB_RD_DEFAULT}};
// 16 bit Bus, 16 bit Granularity
7'b110_0000: read_mux_irq = {irq_bypass[ 15: 1], 1'b0};
7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
7'b110_0110: read_mux_irq = irq_bypass[111: 96];
7'b110_0111: read_mux_irq = irq_bypass[127:112];
default: read_mux_irq = {DWIDTH{WB_RD_DEFAULT}};
endcase
 
// generate wishbone write register strobes for interrupt control
269,18 → 269,18
write_irw_en_1 = 2'b00;
write_irw_en_0 = 2'b00;
if (wbs_wacc)
case (address) // synopsys parallel_case
case (address) // synopsys parallel_case
// 16 bit Bus, 8 bit Granularity
6'b10_0000 : write_irw_en_0 = wbs_sel_i;
6'b10_0001 : write_irw_en_1 = wbs_sel_i;
6'b10_0010 : write_irw_en_2 = wbs_sel_i;
6'b10_0011 : write_irw_en_3 = wbs_sel_i;
6'b10_0100 : write_irw_en_4 = wbs_sel_i;
6'b10_0101 : write_irw_en_5 = wbs_sel_i;
6'b10_0110 : write_irw_en_6 = wbs_sel_i;
6'b10_0111 : write_irw_en_7 = wbs_sel_i;
default: ;
endcase
6'b10_0000 : write_irw_en_0 = wbs_sel_i;
6'b10_0001 : write_irw_en_1 = wbs_sel_i;
6'b10_0010 : write_irw_en_2 = wbs_sel_i;
6'b10_0011 : write_irw_en_3 = wbs_sel_i;
6'b10_0100 : write_irw_en_4 = wbs_sel_i;
6'b10_0101 : write_irw_en_5 = wbs_sel_i;
6'b10_0110 : write_irw_en_6 = wbs_sel_i;
6'b10_0111 : write_irw_en_7 = wbs_sel_i;
default: ;
endcase
end
 
endmodule // xgate_wbs_bus
/xgate_wbm_bus.v
39,7 → 39,7
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_wbm_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter DWIDTH = 16,
parameter DWIDTH = 16,
parameter SINGLE_CYCLE = 1'b0)
(
// Wishbone Signals
63,7 → 63,7
input single_step, // Pulse to trigger a single instruction execution in debug mode
output ss_mem_ack, // WISHBONE Bus has granted single step memory access
input [15:0] xgate_address, // Address to system memory
input mem_access, //
input mem_access, //
input write_mem_strb_l, // Strobe for writing low data byte
input write_mem_strb_h, // Strobe for writing high data bye
input [DWIDTH-1:0] write_mem_data // Data to system memory
77,7 → 77,7
//
// Module body
//
 
// Latch Single Step Request and ask for memory access
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
84,22 → 84,22
ss_mem_req <= 1'b0;
else
ss_mem_req <= (single_step || ss_mem_req) && !wbm_ack_i && xge;
 
assign ss_mem_ack = ss_mem_req && wbm_ack_i;
 
 
assign wbm_dat_o = write_mem_data;
assign read_mem_data = wbm_dat_i;
assign wbm_adr_o = xgate_address;
 
assign mem_req_ack = wbm_ack_i;
 
assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
 
assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
 
assign wbm_cyc_o = xge && (mem_access || ss_mem_req);
 
assign wbm_stb_o = xge && (mem_access || ss_mem_req);
 
endmodule // xgate_wbm_bus
/xgate_regs.v
230,47 → 230,47
begin
k = 1; // WISHBONE Bus bit counter [15:0]
for (j = 1; j <= 127; j = j + 1)
begin
if (j <= MAX_CHANNEL)
begin
if ((j >= 0) && (j < 8))
irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 8) && (j < 16))
irq_bypass_d[j] = write_irw_en_0[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 16) && (j < 24))
irq_bypass_d[j] = write_irw_en_1[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 24) && (j < 32))
irq_bypass_d[j] = write_irw_en_1[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 32) && (j < 40))
irq_bypass_d[j] = write_irw_en_2[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 40) && (j < 48))
irq_bypass_d[j] = write_irw_en_2[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 48) && (j < 56))
irq_bypass_d[j] = write_irw_en_3[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 56) && (j < 64))
irq_bypass_d[j] = write_irw_en_3[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 64) && (j < 72))
irq_bypass_d[j] = write_irw_en_4[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 72) && (j < 80))
irq_bypass_d[j] = write_irw_en_4[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 80) && (j < 88))
irq_bypass_d[j] = write_irw_en_5[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 88) && (j < 96))
irq_bypass_d[j] = write_irw_en_5[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 96) && (j < 104))
irq_bypass_d[j] = write_irw_en_6[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 104) && (j < 112))
irq_bypass_d[j] = write_irw_en_6[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 112) && (j < 120))
irq_bypass_d[j] = write_irw_en_7[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 120) && (j < 128))
irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j];
end
else
irq_bypass_d[j] = 1'b0;
k = k + 1;
if (k > 15)
k = 0;
begin
if (j <= MAX_CHANNEL)
begin
if ((j >= 0) && (j < 8))
irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 8) && (j < 16))
irq_bypass_d[j] = write_irw_en_0[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 16) && (j < 24))
irq_bypass_d[j] = write_irw_en_1[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 24) && (j < 32))
irq_bypass_d[j] = write_irw_en_1[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 32) && (j < 40))
irq_bypass_d[j] = write_irw_en_2[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 40) && (j < 48))
irq_bypass_d[j] = write_irw_en_2[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 48) && (j < 56))
irq_bypass_d[j] = write_irw_en_3[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 56) && (j < 64))
irq_bypass_d[j] = write_irw_en_3[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 64) && (j < 72))
irq_bypass_d[j] = write_irw_en_4[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 72) && (j < 80))
irq_bypass_d[j] = write_irw_en_4[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 80) && (j < 88))
irq_bypass_d[j] = write_irw_en_5[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 88) && (j < 96))
irq_bypass_d[j] = write_irw_en_5[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 96) && (j < 104))
irq_bypass_d[j] = write_irw_en_6[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 104) && (j < 112))
irq_bypass_d[j] = write_irw_en_6[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 112) && (j < 120))
irq_bypass_d[j] = write_irw_en_7[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 120) && (j < 128))
irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j];
end
else
irq_bypass_d[j] = 1'b0;
k = k + 1;
if (k > 15)
k = 0;
end
end
 
283,7 → 283,7
irq_bypass <= irq_bypass_d;
 
// Alias the register name to the output pin name so only the used bit are carried out
assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
 
endmodule // xgate_regs
 
/xgate_risc.v
49,7 → 49,7
output reg [15:0] xgr7,
output [15:0] xgate_address,
output [15:0] write_mem_data, // Data for Memory write
output mem_access, //
output mem_access, //
output write_mem_strb_l, // Strobe for writing low data byte
output write_mem_strb_h, // Strobe for writing high data bye
output reg zero_flag,
205,7 → 205,7
reg debug_edge; // Reg for edge detection
 
reg cmd_dbg;
 
reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
reg [ 1:0] chid_sm; //
wire chid_goto_idle; //
215,13 → 215,13
CHID_TEST = 2'b10,
CHID_WAIT = 2'b11;
 
 
assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};
assign bra_offset = {{5{op_code[9]}}, op_code[9:0], 1'b0};
assign pc_sum = program_counter + pc_incr_mux;
 
assign xgate_address = data_access ? data_address : program_counter;
 
//assign mem_access = data_access || load_next_inst || start_thread;
assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
(cpu_state == BREAK_2) || start_thread;
326,9 → 326,9
else
begin
cmd_dbg <= !((cpu_state == LD_INST) || (cpu_state == DEBUG)) &&
(cmd_dbg || (xgdbg_set && mem_req_ack && (next_cpu_state == CONT)));
(cmd_dbg || (xgdbg_set && mem_req_ack && (next_cpu_state == CONT)));
end
 
// Latch the debug state, set by eather xgdb or BRK instructions
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
342,7 → 342,7
brk_set_dbg || op_code_error || debug_active);
debug_edge <= debug_active;
end
 
assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
 
// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
390,7 → 390,7
CHID_IDLE:
if ( write_xgchid && debug_active )
chid_sm_ns = CHID_TEST;
else
else
chid_sm_ns = CHID_IDLE;
CHID_TEST:
if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
404,7 → 404,7
chid_sm_ns = CHID_WAIT;
default : chid_sm_ns = CHID_IDLE;
endcase
 
assign chid_goto_idle = (chid_sm == CHID_WAIT);
 
// CPU Read Data Buffer Register
459,21 → 459,21
j = j + 1;
end
if (clear_xgif_0)
xgif_d[15: 1] = ~clear_xgif_data & xgif_status[15: 1];
xgif_d[15: 1] = ~clear_xgif_data & xgif_status[15: 1];
if (clear_xgif_1)
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
if (clear_xgif_2)
xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
if (clear_xgif_3)
xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48];
xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48];
if (clear_xgif_4)
xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64];
xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64];
if (clear_xgif_5)
xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80];
xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80];
if (clear_xgif_6)
xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96];
xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96];
if (clear_xgif_7)
xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
end
 
// Interrupt Flag Registers
498,53 → 498,53
end
else
begin
xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
{(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
{(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
(write_xgr1[0] ? perif_data[ 7:0]: xgr1[ 7:0])} :
{((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
((wrt_sel_xgr1 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr1[ 7:0])};
xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
{(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
{(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
(write_xgr2[0] ? perif_data[ 7:0]: xgr2[ 7:0])} :
{((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
((wrt_sel_xgr2 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr2[ 7:0])};
xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
{(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
{(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
(write_xgr3[0] ? perif_data[ 7:0]: xgr3[ 7:0])} :
{((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
((wrt_sel_xgr3 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr3[ 7:0])};
xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
{(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
{(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
(write_xgr4[0] ? perif_data[ 7:0]: xgr4[ 7:0])} :
{((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
((wrt_sel_xgr4 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr4[ 7:0])};
xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
{(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
{(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
(write_xgr5[0] ? perif_data[ 7:0]: xgr5[ 7:0])} :
{((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
((wrt_sel_xgr5 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr5[ 7:0])};
xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
{(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
{(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
(write_xgr6[0] ? perif_data[ 7:0]: xgr6[ 7:0])} :
{((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
((wrt_sel_xgr6 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr6[ 7:0])};
xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
{(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
{(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
(write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
end
 
 
 
 
 
 
 
 
 
// V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
// P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
// r - 8-bit data read: lasts for at least one RISC core cycle
// R - 16-bit data read: lasts for at least one RISC core cycle
// w - 8-bit data write: lasts for at least one RISC core cycle
// W - 16-bit data write: lasts for at least one RISC core cycle
// A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
// f - Free cycle: no read or write, lasts for one RISC core cycles
// Special Cases
 
// PP/P - Branch: PP if branch taken, P if not taken
 
always @*
begin
579,9 → 579,9
 
set_irq_flag = 7'b0;
 
set_semaph = 1'b0;
clear_semaph = 1'b0;
semaph_risc = 3'b0;
set_semaph = 1'b0;
clear_semaph = 1'b0;
semaph_risc = 3'b0;
 
casez ({cpu_state, op_code})
 
595,12 → 595,12
 
{CHG_CHID, 16'b????????????????} :
begin
if (!xge)
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
else if (ss_mem_ack || !debug_active)
next_cpu_state = BOOT_1;
else
next_cpu_state = CHG_CHID;
else
next_cpu_state = CHG_CHID;
 
pc_incr_mux = 16'h0000;
next_pc = pc_sum;
644,14 → 644,14
 
{BREAK, 16'b????????????????} :
begin
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = BREAK_2;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = BREAK;
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = BREAK_2;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = BREAK;
load_next_inst = 1'b0;
pc_incr_mux = 16'h0000;
next_pc = pc_sum;
672,16 → 672,16
 
{DEBUG, 16'b????????????????} :
begin
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = CONT;
else if (cmd_change_pc)
next_cpu_state = LD_INST;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = DEBUG;
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = CONT;
else if (cmd_change_pc)
next_cpu_state = LD_INST;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = DEBUG;
 
load_next_inst = cmd_change_pc;
pc_incr_mux = 16'h0000;
784,7 → 784,7
set_semaph = 1'b1;
semaph_risc = op_code[10:8];
 
next_carry = semaph_stat;
next_carry = semaph_stat;
end
 
// Instruction = SSEM RS, Op Code = 0 0 0 0 0 RS 1 1 1 1 0 0 1 1
798,7 → 798,7
set_semaph = 1'b1;
semaph_risc = rd_data[2:0];
 
next_carry = semaph_stat;
next_carry = semaph_stat;
end
 
// -----------------------------------------------------------------------
850,9 → 850,7
// contained in RS[6:0] is set. The content of RS[15:7] is ignored
// Cycles - P
{CONT, 16'b00000???11110111} :
begin
set_irq_flag = rd_data[6:0];
end
set_irq_flag = rd_data[6:0];
 
// -----------------------------------------------------------------------
// Instruction Group -- Special Move instructions
1309,15 → 1307,13
// If C = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010000?????????} :
begin
if (!carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum; // There is a race condition when the default declaration is used
end
end
if (!carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum; // There is a race condition when the default declaration is used
end
 
// Instruction = BCS REL9, Op Code = 0 0 1 0 0 0 1 REL9
// Branch if Carry Set
1324,15 → 1320,13
// If C = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010001?????????} :
begin
if (carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BNE REL9, Op Code = 0 0 1 0 0 1 0 REL9
// Branch if Not Equal
1339,15 → 1333,13
// If Z = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010010?????????} :
begin
if (!zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BEQ REL9, Op Code = 0 0 1 0 0 1 1 REL9
// Branch if Equal
1354,15 → 1346,13
// If Z = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010011?????????} :
begin
if (zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BPL REL9, Op Code = 0 0 1 0 1 0 0 REL9
// Branch if Plus
1369,15 → 1359,13
// If N = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010100?????????} :
begin
if (!negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BMI REL9, Op Code = 0 0 1 0 1 0 1 REL9
// Branch if Minus
1384,15 → 1372,13
// If N = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010101?????????} :
begin
if (negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BVC REL9, Op Code = 0 0 1 0 1 1 0 REL9
// Branch if Overflow Cleared
1399,15 → 1385,13
// If V = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010110?????????} :
begin
if (!overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BVS REL9, Op Code = 0 0 1 0 1 1 1 REL9
// Branch if Overflow Set
1414,15 → 1398,13
// If V = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010111?????????} :
begin
if (overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BHI REL9, Op Code = 0 0 1 1 0 0 0 REL9
// Branch if Higher
1429,15 → 1411,13
// If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011000?????????} :
begin
if (!(carry_flag || zero_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!(carry_flag || zero_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BLS REL9, Op Code = 0 0 1 1 0 0 1 REL9
// Branch if Lower or Same
1444,15 → 1424,13
// If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011001?????????} :
begin
if (carry_flag || zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (carry_flag || zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BGE REL9, Op Code = 0 0 1 1 0 1 0 REL9
// Branch if Greater than or Equal to Zero
1459,15 → 1437,13
// If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011010?????????} :
begin
if (!(negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!(negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BLT REL9, Op Code = 0 0 1 1 0 1 1 REL9
// Branch if Lower than Zero
1474,15 → 1450,13
// If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011011?????????} :
begin
if (negative_flag ^ overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (negative_flag ^ overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BGT REL9, Op Code = 0 0 1 1 1 0 0 REL9
// Branch if Greater than Zero
1489,15 → 1463,13
// If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011100?????????} :
begin
if (!(zero_flag || (negative_flag ^ overflow_flag)))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!(zero_flag || (negative_flag ^ overflow_flag)))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BLE REL9, Op Code = 0 0 1 1 1 0 1 REL9
// Branch if Less or Equal to Zero
1504,15 → 1476,13
// If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011101?????????} :
begin
if (zero_flag || (negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (zero_flag || (negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BRA REL10, Op Code = 0 0 1 1 1 1 REL10
// Branch Always, signed offset
2126,9 → 2096,9
end
default :
begin
// synopsys translate_off
// synopsys translate_off
$display("\nOP Code Error\n");
// synopsys translate_on
// synopsys translate_on
next_cpu_state = DEBUG;
pc_incr_mux = 16'h0000;
next_pc = pc_sum;
2136,7 → 2106,7
op_code_error = 1'b1;
end
endcase
 
end // always
 
xgate_barrel_shift barrel_shift(
2170,20 → 2140,20
generate
for (sem_gen_count = 0; sem_gen_count < 8; sem_gen_count = sem_gen_count + 1)
begin:semaphore_
semaphore_bit bit(
// outputs
.host_status( host_semap[sem_gen_count] ),
.risc_status( risc_semap[sem_gen_count] ),
// inputs
.risc_clk( risc_clk ),
.async_rst_b( async_rst_b ),
.risc_bit_sel( semap_risc_bit[sem_gen_count] ),
.csem( clear_semaph ),
.ssem( set_semaph ),
.host_wrt( write_xgsem ),
.host_bit_mask( perif_data[sem_gen_count+8] ),
.host_bit( perif_data[sem_gen_count] )
);
semaphore_bit sbit(
// outputs
.host_status( host_semap[sem_gen_count] ),
.risc_status( risc_semap[sem_gen_count] ),
// inputs
.risc_clk( risc_clk ),
.async_rst_b( async_rst_b ),
.risc_bit_sel( semap_risc_bit[sem_gen_count] ),
.csem( clear_semaph ),
.ssem( set_semaph ),
.host_wrt( write_xgsem ),
.host_bit_mask( perif_data[sem_gen_count+8] ),
.host_bit( perif_data[sem_gen_count] )
);
end
endgenerate
 
/xgate_top.v
39,9 → 39,10
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter SINGLE_CYCLE = 1'b0, //
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
parameter DWIDTH = 16, // define the wishbone bus data size
parameter SINGLE_CYCLE = 1'b0, //
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
(
// Wishbone Slave Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output
76,7 → 77,6
input scantestmode // Chip in in scan test mode
);
 
parameter DWIDTH = 16; // Data bus width
 
wire zero_flag;
wire negative_flag;
147,7 → 147,7
 
wire [15:1] xgvbr; // XGATE vector Base Address Register
wire brk_irq_ena; // Enable BRK instruction to generate interrupt
 
wire [15:0] xgate_address; //
wire [15:0] write_mem_data; //
wire [15:0] read_mem_data; //
154,20 → 154,20
wire mem_access; //
wire mem_req_ack; //
 
wire debug_active; // RISC state machine in Debug mode
wire debug_active; // RISC state machine in Debug mode
wire debug_ack; // Clear debug register
wire single_step; // Pulse to trigger a single instruction execution in debug mode
wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
 
wire [ 7:0] host_semap; // Semaphore status for host
wire write_mem_strb_l; // Strobe for writing low data byte
wire write_mem_strb_h; // Strobe for writing high data bye
 
// ---------------------------------------------------------------------------
// Wishbone Slave Bus interface
xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
.SINGLE_CYCLE(SINGLE_CYCLE),
.WB_RD_DEFAULT(WB_RD_DEFAULT))
.WB_RD_DEFAULT(WB_RD_DEFAULT))
wishbone_s(
.wbs_dat_o( wbs_dat_o ),
.wbs_ack_o( wbs_ack_o ),
181,7 → 181,7
.wbs_stb_i( wbs_stb_i ),
.wbs_cyc_i( wbs_cyc_i ),
.wbs_sel_i( wbs_sel_i ),
 
// outputs
.sync_reset( sync_reset ),
.write_xgmctl( write_xgmctl ),
214,37 → 214,37
.write_irw_en_2( write_irw_en_2 ),
.write_irw_en_1( write_irw_en_1 ),
.write_irw_en_0( write_irw_en_0 ),
// inputs
// inputs
.async_rst_b( async_rst_b ),
.read_risc_regs( // in -- read register bits
{ xgr7, // XGR7
xgr6, // XGR6
xgr5, // XGR5
xgr4, // XGR4
xgr3, // XGR3
xgr2, // XGR2
xgr1, // XGR1
16'b0, // Reserved (XGR0)
xgate_address, // XGPC
{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
16'b0, // Reserved
{8'h00, host_semap}, // XGSEM
{8'h00, xgswt}, // XGSWT
{xgif_status[ 15: 1], 1'b0}, // XGIF_0
xgif_status[ 31: 16], // XGIF_1
xgif_status[ 47: 32], // XGIF_2
xgif_status[ 63: 48], // XGIF_3
xgif_status[ 79: 64], // XGIF_4
xgif_status[ 95: 80], // XGIF_5
xgif_status[111: 96], // XGIF_6
xgif_status[127:112], // XGIF_7
{xgvbr[15:1], 1'b0}, // XGVBR
16'b0, // Reserved
16'b0, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
}
),
{ xgr7, // XGR7
xgr6, // XGR6
xgr5, // XGR5
xgr4, // XGR4
xgr3, // XGR3
xgr2, // XGR2
xgr1, // XGR1
16'b0, // Reserved (XGR0)
xgate_address, // XGPC
{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
16'b0, // Reserved
{8'h00, host_semap}, // XGSEM
{8'h00, xgswt}, // XGSWT
{xgif_status[ 15: 1], 1'b0}, // XGIF_0
xgif_status[ 31: 16], // XGIF_1
xgif_status[ 47: 32], // XGIF_2
xgif_status[ 63: 48], // XGIF_3
xgif_status[ 79: 64], // XGIF_4
xgif_status[ 95: 80], // XGIF_5
xgif_status[111: 96], // XGIF_6
xgif_status[127:112], // XGIF_7
{xgvbr[15:1], 1'b0}, // XGVBR
16'b0, // Reserved
16'b0, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
}
),
.irq_bypass( irq_bypass )
 
);
331,7 → 331,7
.xg_sw_irq( xg_sw_irq ),
.mem_access( mem_access ),
.single_step( single_step ),
 
// inputs
.risc_clk( risc_clk ),
.perif_data( wbs_dat_i ),
371,7 → 371,7
.clear_xgif_data( clear_xgif_data )
);
 
xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
irq_encode(
// outputs
.xgif( xgif ),

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