OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

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    /xgate/trunk/rtl
    from Rev 2 to Rev 5
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Rev 2 → Rev 5

/verilog/xgate_wbs_bus.v
54,7 → 54,7
input wbs_stb_i, // stobe/core select signal
input wbs_cyc_i, // valid bus cycle input
input [1:0] wbs_sel_i, // Select byte in word bus transaction
// COP Control Signals
// XGATE Control Signals
output reg write_xgmctl, // Write Strobe for XGMCTL register
output reg write_xgisp74,// Write Strobe for XGISP74 register
output reg write_xgisp30,// Write Strobe for XGISP30 register
/verilog/xgate_risc.v
64,6 → 64,7
input [15:0] perif_data,
input risc_clk,
input async_rst_b,
input mem_req_ack, // Memory Bus available - data good
input xge, // XGATE Module Enable
input xgfrz, // Stop XGATE in Freeze Mode
input xgdbg, // XGATE Debug Mode
96,15 → 97,16
integer bfi, bfii, bfix; // Loop counter for Bit Field Insert function
 
// State machine sequence
parameter [2:0] //synopsys enum state_info
IDLE = 3'b000, // waiting for interrupt
CONT = 3'b001, // Instruction processing state, first state
STALL = 3'b010, // Second step in 2 state instruction (Memory Read/Write)
DEBUG = 3'b011, //
BOOT_1 = 3'b100, //
BOOT_2 = 3'b101, //
BOOT_3 = 3'b110, //
UNDEF5 = 3'b111; //
parameter [3:0] //synopsys enum state_info
IDLE = 4'b0000, // waiting for interrupt
CONT = 4'b0001, // Instruction processing state, first state
DEBUG = 4'b0011, //
BOOT_1 = 4'b0100, //
BOOT_2 = 4'b0101, //
BOOT_3 = 4'b0110, //
S_STALL = 4'b0111, // Simple Stall while updating PC after change of flow
W_STALL = 4'b1000, // Stall while doing memory word read access
B_STALL = 4'b1001; // Stall while doing memory byte read access
// Semaphore states
113,8 → 115,8
HOST_LOCK = 2'b11;
reg [ 2:0] cpu_state;
reg [ 2:0] next_cpu_state; // Pseudo Register,
reg [ 3:0] cpu_state;
reg [ 3:0] next_cpu_state; // Pseudo Register,
reg load_next_inst; // Pseudo Register,
reg [15:0] program_counter;
reg [15:0] next_pc; // Pseudo Register,
206,13 → 208,13
wrt_sel_xgr6 = 1'b0;
wrt_sel_xgr7 = 1'b0;
case (wrt_reg_sel)
3'b001 : wrt_sel_xgr1 = 1'b1;
3'b010 : wrt_sel_xgr2 = 1'b1;
3'b011 : wrt_sel_xgr3 = 1'b1;
3'b100 : wrt_sel_xgr4 = 1'b1;
3'b101 : wrt_sel_xgr5 = 1'b1;
3'b110 : wrt_sel_xgr6 = 1'b1;
3'b111 : wrt_sel_xgr7 = 1'b1;
3'b001 : wrt_sel_xgr1 = mem_req_ack;
3'b010 : wrt_sel_xgr2 = mem_req_ack;
3'b011 : wrt_sel_xgr3 = mem_req_ack;
3'b100 : wrt_sel_xgr4 = mem_req_ack;
3'b101 : wrt_sel_xgr5 = mem_req_ack;
3'b110 : wrt_sel_xgr6 = mem_req_ack;
3'b111 : wrt_sel_xgr7 = mem_req_ack;
endcase
end
 
256,13 → 258,12
end
end
 
 
// CPU State Register
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
cpu_state <= IDLE;
else
cpu_state <= next_cpu_state;
cpu_state <= mem_req_ack ? next_cpu_state : cpu_state;
 
// CPU Instruction Register
always @(posedge risc_clk or negedge async_rst_b)
269,7 → 270,7
if ( !async_rst_b )
op_code <= 16'h0000;
else
op_code <= load_next_inst ? read_mem_data : op_code;
op_code <= (load_next_inst && mem_req_ack) ? read_mem_data : op_code;
// Active Channel Latch
always @(posedge risc_clk or negedge async_rst_b)
276,7 → 277,7
if ( !async_rst_b )
xgchid <= 7'b0;
else
xgchid <= (cpu_state == IDLE) ? int_req : xgchid;
xgchid <= ((cpu_state == IDLE) && mem_req_ack) ? int_req : xgchid;
 
// CPU Read Data Buffer Register
always @(posedge risc_clk or negedge async_rst_b)
283,7 → 284,7
if ( !async_rst_b )
load_data <= 16'h0000;
else
load_data <= (data_access && !data_write) ? read_mem_data : load_data;
load_data <= (data_access && !data_write && mem_req_ack) ? read_mem_data : load_data;
 
// Program Counter Register
always @(posedge risc_clk or negedge async_rst_b)
290,7 → 291,7
if ( !async_rst_b )
program_counter <= 16'h0000;
else
program_counter <= next_pc;
program_counter <= mem_req_ack ? next_pc : program_counter;
 
// ALU Flag Bits
always @(posedge risc_clk or negedge async_rst_b)
303,10 → 304,10
end
else
begin
carry_flag <= write_xgccr ? perif_data[0] : next_carry;
overflow_flag <= write_xgccr ? perif_data[1] : next_overflow;
zero_flag <= write_xgccr ? perif_data[2] : next_zero;
negative_flag <= write_xgccr ? perif_data[3] : next_negative;
carry_flag <= write_xgccr ? perif_data[0] : (mem_req_ack ? next_carry : carry_flag);
overflow_flag <= write_xgccr ? perif_data[1] : (mem_req_ack ? next_overflow : overflow_flag);
zero_flag <= write_xgccr ? perif_data[2] : (mem_req_ack ? next_zero : zero_flag);
negative_flag <= write_xgccr ? perif_data[3] : (mem_req_ack ? next_negative : negative_flag);
end
 
// Interrupt Flag next value
480,6 → 481,31
next_pc = program_counter;
end
 
// Pause here while program counter change of flow or memory write access
// Load next instruction and increment PC
{S_STALL, 16'b????????????????} :
begin
next_cpu_state = CONT;
end
 
// Pause here for memory read word access
// Load next instruction and increment PC
{W_STALL, 16'b????????????????} :
begin
alu_result = load_data;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Pause here for memory read byte access
// Load next instruction and increment PC
{B_STALL, 16'b????????????????} :
begin
alu_result = {8'h00, load_data[15:8]};
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// -----------------------------------------------------------------------
// Instruction Group -- Return to Scheduler and Others
// -----------------------------------------------------------------------
601,7 → 627,7
// Cycles - PP
{CONT, 16'b00000???11110110} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
609,11 → 635,6
next_pc = rd_data;
end
 
{STALL, 16'b00000???11110110} :
begin
next_cpu_state = CONT;
end
 
// Instruction = SIF RS, Op Code = 0 0 0 0 0 RS 1 1 1 1 0 1 1 1
// Sets the Interrupt Flag associated with the channel id number
// contained in RS[6:0] is set. The content of RS[15:7] is ignored
1081,17 → 1102,12
begin
if (!carry_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010000?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BCS REL9, Op Code = 0 0 1 0 0 0 1 REL9
// Branch if Carry Set
// If C = 1, then PC + $0002 + (REL9 << 1) => PC
1100,17 → 1116,12
begin
if (carry_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010001?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BNE REL9, Op Code = 0 0 1 0 0 1 0 REL9
// Branch if Not Equal
// If Z = 0, then PC + $0002 + (REL9 << 1) => PC
1119,17 → 1130,12
begin
if (!zero_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010010?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BEQ REL9, Op Code = 0 0 1 0 0 1 1 REL9
// Branch if Equal
// If Z = 1, then PC + $0002 + (REL9 << 1) => PC
1138,17 → 1144,12
begin
if (zero_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010011?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BPL REL9, Op Code = 0 0 1 0 1 0 0 REL9
// Branch if Plus
// If N = 0, then PC + $0002 + (REL9 << 1) => PC
1157,17 → 1158,12
begin
if (!negative_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010100?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BMI REL9, Op Code = 0 0 1 0 1 0 1 REL9
// Branch if Minus
// If N = 1, then PC + $0002 + (REL9 << 1) => PC
1176,17 → 1172,12
begin
if (negative_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010101?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BVC REL9, Op Code = 0 0 1 0 1 1 0 REL9
// Branch if Overflow Cleared
// If V = 0, then PC + $0002 + (REL9 << 1) => PC
1195,17 → 1186,12
begin
if (!overflow_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010110?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BVS REL9, Op Code = 0 0 1 0 1 1 1 REL9
// Branch if Overflow Set
// If V = 1, then PC + $0002 + (REL9 << 1) => PC
1214,17 → 1200,12
begin
if (overflow_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0010111?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BHI REL9, Op Code = 0 0 1 1 0 0 0 REL9
// Branch if Higher
// If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
1233,17 → 1214,12
begin
if (!(carry_flag || zero_flag))
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0011000?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BLS REL9, Op Code = 0 0 1 1 0 0 1 REL9
// Branch if Lower or Same
// If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
1252,17 → 1228,12
begin
if (carry_flag || zero_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0011001?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BGE REL9, Op Code = 0 0 1 1 0 1 0 REL9
// Branch if Greater than or Equal to Zero
// If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
1271,17 → 1242,12
begin
if (!(negative_flag ^ overflow_flag))
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0011010?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BLT REL9, Op Code = 0 0 1 1 0 1 1 REL9
// Branch if Lower than Zero
// If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
1290,17 → 1256,12
begin
if (negative_flag ^ overflow_flag)
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0011011?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BGT REL9, Op Code = 0 0 1 1 1 0 0 REL9
// Branch if Greater than Zero
// If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
1309,17 → 1270,12
begin
if (!(zero_flag || (negative_flag ^ overflow_flag)))
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0011100?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BLE REL9, Op Code = 0 0 1 1 1 0 1 REL9
// Branch if Less or Equal to Zero
// If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
1328,17 → 1284,12
begin
if (zero_flag || (negative_flag ^ overflow_flag))
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0};
end
end
 
{STALL, 16'b0011101?????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = BRA REL10, Op Code = 0 0 1 1 1 1 REL10
// Branch Always, signed offset
// PC + $0002 + (REL10 << 1) => PC
1345,15 → 1296,11
// Cycles - PP
{CONT, 16'b001111??????????} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter + {{5{op_code[9]}}, op_code[9:0], 1'b0};
end
 
{STALL, 16'b001111??????????} :
begin
next_cpu_state = CONT;
end
 
// -----------------------------------------------------------------------
// Instruction Group -- Load and Store Instructions
1366,7 → 1313,7
// Cycles - Pr
{CONT, 16'b01000???????????} :
begin
next_cpu_state = STALL;
next_cpu_state = B_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1373,14 → 1320,6
data_address = rs1_data + {11'b0, op_code[4:0]};
end
 
{STALL, 16'b01000???????????} :
begin
next_cpu_state = CONT;
alu_result = {8'h00, load_data[15:8]};
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = LDW RD, (RB, #OFFS5), Op Code = 0 1 0 0 1 RD RB OFFS5
// Load Word from Memory, unsigned offset
// M[RB, #OFFS5] => RD
1388,7 → 1327,7
// Cycles - PR
{CONT, 16'b01001???????????} :
begin
next_cpu_state = STALL;
next_cpu_state = W_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1396,14 → 1335,6
data_word_op = 1'b1;
end
 
{STALL, 16'b01001???????????} :
begin
next_cpu_state = CONT;
alu_result = load_data;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = STB RS, (RB, #OFFS5), Op Code = 0 1 0 1 0 RS RB OFFS5
// Store Byte to Memory, unsigned offset
// RS.L => M[RB, #OFFS5]
1411,7 → 1342,7
// Cycles - Pw
{CONT, 16'b01010???????????} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1419,12 → 1350,6
data_address = rs1_data + {11'b0, op_code[4:0]};
end
 
{STALL, 16'b01010???????????} :
begin
next_cpu_state = CONT;
end
 
 
// Instruction = STW RS, (RB, #OFFS5), Op Code = 0 1 0 1 1 RS RB OFFS5
// Store Word to Memory, unsigned offset
// RS => M[RB, #OFFS5]
1432,7 → 1357,7
// Cycles - PW
{CONT, 16'b01011???????????} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1441,11 → 1366,6
data_word_op = 1'b1;
end
 
{STALL, 16'b01011???????????} :
begin
next_cpu_state = CONT;
end
 
// Instruction = LDB RD, (RB, RI), Op Code = 0 1 1 0 0 RD RB RI 0 0
// Load Byte from Memory
// M[RB, RI] => RD.L; $00 => RD.H
1453,7 → 1373,7
// Cycles - Pr
{CONT, 16'b01100?????????00} :
begin
next_cpu_state = STALL;
next_cpu_state = B_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1460,14 → 1380,6
data_address = rs1_data + rs2_data;
end
 
{STALL, 16'b01100?????????00} :
begin
next_cpu_state = CONT;
alu_result = {8'h00, load_data[15:8]};
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = LDW RD, (RB, RI), Op Code = 0 1 1 0 1 RD RB RI 0 0
// Load Word from Memory
// M[RB, RI] => RD
1475,7 → 1387,7
// Cycles - PR
{CONT, 16'b01101?????????00} :
begin
next_cpu_state = STALL;
next_cpu_state = W_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1483,14 → 1395,6
data_word_op = 1'b1;
end
 
{STALL, 16'b01101?????????00} :
begin
next_cpu_state = CONT;
alu_result = load_data;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = STB RS, (RB, RI), Op Code = 0 1 1 1 0 RS RB RI 0 0
// RS.L => M[RB, RI]
// Store Byte to Memory
1498,7 → 1402,7
// Cycles - Pw
{CONT, 16'b01110?????????00} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1506,11 → 1410,6
data_address = rs1_data + rs2_data;
end
 
{STALL, 16'b01110?????????00} :
begin
next_cpu_state = CONT;
end
 
// Instruction = STW RS, (RB, RI), Op Code = 0 1 1 1 1 RS RB RI 0 0
// Store Word to Memory
// RS => M[RB, RI]
1518,7 → 1417,7
// Cycles - PW
{CONT, 16'b01111?????????00} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1527,11 → 1426,6
data_word_op = 1'b1;
end
 
{STALL, 16'b01111?????????00} :
begin
next_cpu_state = CONT;
end
 
// Instruction = LDB RD, (RB, RI+), Op Code = 0 1 1 0 0 RD RB RI 0 1
// Load Byte from Memory
// M[RB, RI] => RD.L; $00 => RD.H; RI+1 => RI
1541,7 → 1435,7
// Cycles - Pr
{CONT, 16'b01100?????????01} :
begin
next_cpu_state = STALL;
next_cpu_state = B_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1552,14 → 1446,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01100?????????01} :
begin
next_cpu_state = CONT;
alu_result = {8'h00, load_data[15:8]};
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = LDW RD, (RB, RI+), Op Code = 0 1 1 0 1 RD RB RI 0 1
// Load Word from Memory
// M[RB, RI] => RD; RI+2 => RI
1569,7 → 1455,7
// Cycles - PR
{CONT, 16'b01101?????????01} :
begin
next_cpu_state = STALL;
next_cpu_state = W_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1581,14 → 1467,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01101?????????01} :
begin
next_cpu_state = CONT;
alu_result = load_data;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = STB RS, (RB, RI+), Op Code = 0 1 1 1 0 RS RB RI 0 1
// Store Byte to Memory
// RS.L => M[RB, RI]; RI+1 => RI
1596,7 → 1474,7
// Cycles - Pw
{CONT, 16'b01110?????????01} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1608,11 → 1486,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01110?????????01} :
begin
next_cpu_state = CONT;
end
 
// Instruction = STW RS, (RB, RI+), Op Code = 0 1 1 1 1 RS RB RI 0 1
// Store Word to Memory
// RS => M[RB, RI]; RI+2 => RI
1620,7 → 1493,7
// Cycles - PW
{CONT, 16'b01111?????????01} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1633,11 → 1506,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01111?????????01} :
begin
next_cpu_state = CONT;
end
 
// Instruction = LDB RD, (RB, -RI), Op Code = 0 1 1 0 0 RD RB RI 1 0
// Load Byte from Memory
// RI-1 => RI; M[RS, RI] => RD.L; $00 => RD.H
1645,7 → 1513,7
// Cycles - Pr
{CONT, 16'b01100?????????10} :
begin
next_cpu_state = STALL;
next_cpu_state = B_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1656,14 → 1524,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01100?????????10} :
begin
next_cpu_state = CONT;
alu_result = {8'h00, load_data[15:8]};
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = LDW RD, (RB, -RI), Op Code = 0 1 1 0 1 RD RB RI 1 0
// Load Word from Memory
// RI-2 => RI; M[RS, RI] => RD
1671,7 → 1531,7
// Cycles - PR
{CONT, 16'b01101?????????10} :
begin
next_cpu_state = STALL;
next_cpu_state = W_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1683,14 → 1543,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01101?????????10} :
begin
next_cpu_state = CONT;
alu_result = load_data;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
end
 
// Instruction = STB RS, (RB, -RI), Op Code = 0 1 1 1 0 RS RB RI 1 0
// Store Byte to Memory
// RI-1 => RI; RS.L => M[RB, RI]
1700,7 → 1552,7
// Cycles - Pw
{CONT, 16'b01110?????????10} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1712,11 → 1564,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01110?????????10} :
begin
next_cpu_state = CONT;
end
 
// Instruction = STW RS, (RB, -RI), Op Code = 0 1 1 1 1 RS RB RI 1 0
// Store Word to Memory
// RI-2 => RI; RS => M[RB, RI]
1726,7 → 1573,7
// Cycles - PW
{CONT, 16'b01111?????????10} :
begin
next_cpu_state = STALL;
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
next_pc = program_counter;
data_access = 1'b1;
1739,11 → 1586,6
ena_rd_high_byte = 1'b1;
end
 
{STALL, 16'b01111?????????10} :
begin
next_cpu_state = CONT;
end
 
// -----------------------------------------------------------------------
// Instruction Group -- Bit Field Instructions
// -----------------------------------------------------------------------
1754,7 → 1596,7
// Cycles - P
{CONT, 16'b01100?????????11} :
begin
ena_rd_low_byte = 1'b1;
ena_rd_low_byte = 1'b1;
ena_rd_high_byte = 1'b1;
shift_ammount = {1'b0, rs2_data[3:0]};
for (bfi = 0; bfi <= 15; bfi = bfi + 1)
2074,6 → 1916,7
assign semaph_stat = |risc_semap;
 
// A "generate" statment would be good here but it's not supported in iverilog
// Semaphore Bit
semaphore_bit semaphore_0(
// outputs
/verilog/xgate_top.v
43,32 → 43,37
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter DWIDTH = 16) // Data bus width
(
// Wishbone Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output
output wbs_ack_o, // bus cycle acknowledge output
input wbs_clk_i, // master clock input
input wbs_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [4:0] wbs_adr_i, // lower address bits
input [DWIDTH-1:0] wbs_dat_i, // databus input
input wbs_we_i, // write enable input
input wbs_stb_i, // stobe/core select signal
input wbs_cyc_i, // valid bus cycle input
input [1:0] wbs_sel_i, // Select byte in word bus transaction
// Wishbone Slave Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output
output wbs_ack_o, // bus cycle acknowledge output
input wbs_clk_i, // master clock input
input wbs_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [4:0] wbs_adr_i, // lower address bits
input [DWIDTH-1:0] wbs_dat_i, // databus input
input wbs_we_i, // write enable input
input wbs_stb_i, // stobe/core select signal
input wbs_cyc_i, // valid bus cycle input
input [1:0] wbs_sel_i, // Select byte in word bus transaction
// Wishbone Master Signals
output [DWIDTH-1:0] wbm_dat_o, // databus output
output wbm_we_o, // write enable output
output wbm_stb_o, // stobe/core select signal
output wbm_cyc_o, // valid bus cycle output
output [ 1:0] wbm_sel_o, // Select byte in word bus transaction
output [15:0] wbm_adr_o, // Address bits
input [DWIDTH-1:0] wbm_dat_i, // databus input
input wbm_ack_i, // bus cycle acknowledge input
// XGATE IO Signals
output [ 7:0] xgswt, // XGATE Software Trigger Register
output [15:0] xgate_address,
output [ 7:0] xgswt, // XGATE Software Trigger Register
output write_mem_strb_l, // Strobe for writing low data byte
output write_mem_strb_h, // Strobe for writing high data bye
output [15:0] write_mem_data,
output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
input [15:0] read_mem_data,
input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
input risc_clk, // Clock for RISC core
input scantestmode // Chip in in scan test mode
);
 
wire zero_flag;
wire negative_flag;
wire carry_flag;
128,7 → 133,11
wire [ 6:0] xgchid; // Channel actively being processed
wire [15:1] xgvbr; // XGATE vector Base Address Register
wire [ 2:0] semaph_risc; // Semaphore register select from RISC
wire [15:0] xgate_address; //
wire [15:0] write_mem_data; //
wire [15:0] read_mem_data; //
wire mem_req_ack; //
wire [ 7:0] host_semap; // Semaphore status for host
// wire [15:0] write_mem_data;
// wire [15:0] read_mem_data;
138,7 → 147,7
// ---------------------------------------------------------------------------
// Wishbone Slave Bus interface
xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
.SINGLE_CYCLE(SINGLE_CYCLE))
.SINGLE_CYCLE(SINGLE_CYCLE))
wishbone_s(
.wbs_dat_o( wbs_dat_o ),
.wbs_ack_o( wbs_ack_o ),
285,12 → 294,13
.perif_data( wbs_dat_i ),
.async_rst_b( async_rst_b ),
.read_mem_data( read_mem_data ),
.mem_req_ack( mem_req_ack ),
.xge( xge ),
.xgfrz( xgfrz ),
.xgdbg( xgdbg ),
.xgss( xgss ),
.xgvbr( xgvbr ),
.int_req(int_req),
.int_req( int_req ),
.write_xgsem( write_xgsem ),
.write_xgccr( write_xgccr ),
.write_xgpc( write_xgpc ),
320,6 → 330,31
.chan_req_i( chan_req_i )
);
 
// ---------------------------------------------------------------------------
// Wishbone Master Bus interface
xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
wishbone_m(
// Wishbone Master Signals
.wbm_dat_o( wbm_dat_o ),
.wbm_we_o( wbm_we_o ),
.wbm_stb_o( wbm_stb_o ),
.wbm_cyc_o( wbm_cyc_o ),
.wbm_sel_o( wbm_sel_o ),
.wbm_adr_o( wbm_adr_o ),
.wbm_dat_i( wbm_dat_i ),
.wbm_ack_i( wbm_ack_i ),
.wbs_clk_i( wbs_clk_i ),
.wbs_rst_i( wbs_rst_i ),
.arst_i( arst_i ),
// XGATE Control Signals
.read_mem_data( read_mem_data ),
.xgate_address( xgate_address ),
.mem_req_ack( mem_req_ack ),
.write_mem_strb_l( write_mem_strb_l ),
.write_mem_strb_h( write_mem_strb_h ),
.write_mem_data( write_mem_data )
);
 
 
endmodule // xgate_top
 

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