URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
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- This comparison shows the changes necessary to convert path
/xgate/trunk
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/bench/verilog/wb_master_model.v
51,29 → 51,26
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module wb_master_model #(parameter dwidth = 32, |
parameter awidth = 32) |
(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); |
( |
output reg cyc, |
output reg stb, |
output reg we, |
output reg [dwidth/8 -1:0] sel, |
output reg [awidth -1:0] adr, |
output reg [dwidth -1:0] dout, |
input [dwidth -1:0] din, |
input clk, |
input ack, |
input rst, // No Connect |
input err, // No Connect |
input rty // No Connect |
); |
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input clk, rst; |
output [awidth -1:0] adr; |
input [dwidth -1:0] din; |
output [dwidth -1:0] dout; |
output cyc, stb; |
output we; |
output [dwidth/8 -1:0] sel; |
input ack, err, rty; |
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//////////////////////////////////////////////////////////////////// |
// |
// Local Wires |
// |
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reg [awidth -1:0] adr; |
reg [dwidth -1:0] dout; |
reg cyc, stb; |
reg we; |
reg [dwidth/8 -1:0] sel; |
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reg [dwidth -1:0] q; |
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event test_command_start; |
80,6 → 77,8
event test_command_mid; |
event test_command_end; |
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event cmp_error_detect; |
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//////////////////////////////////////////////////////////////////// |
// |
// Memory Logic |
87,8 → 86,6
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initial |
begin |
//adr = 32'hxxxx_xxxx; |
//adr = 0; |
adr = {awidth{1'bx}}; |
dout = {dwidth{1'bx}}; |
cyc = 1'b0; |
99,6 → 96,7
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)"); |
end |
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//////////////////////////////////////////////////////////////////// |
// |
// Wishbone write cycle |
203,7 → 201,10
wb_read (delay, a, q); |
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if (d_exp !== q) |
begin |
-> cmp_error_detect; |
$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time); |
end |
end |
endtask |
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