URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
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- This comparison shows the changes necessary to convert path
/xgate/trunk
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/bench/xgate_test_code/inst_test/make_core.scr
1,3 → 1,3
../../../bench/tools/HSW12ASM/hsw12asm.pl inst_test.s |
../../../bench/tools/a.out shift_test_pag.s28 |
../../../bench/tools/a.out inst_test_pag.s28 |
mv temp1.v ../../../bench/verilog/jump_mem.v |
/bench/xgate_test_code/inst_test/inst_test.s
183,6 → 183,11
STB R3,(R2,#0) |
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register |
|
; LDL R2,#$04 ; Sent Message to Testbench Error Register |
; LDH R2,#$80 |
; LDL R3,#$00 |
; STB R3,(R2,#0) |
|
SIF |
RTS |
|
375,6 → 380,11
RTS |
|
_FAIL |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$02 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
583,6 → 593,11
RTS |
|
_FAIL2 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$04 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
747,6 → 762,11
RTS |
|
_FAIL3 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$06 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
871,6 → 891,11
RTS |
|
_FAIL4 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$08 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
1049,6 → 1074,11
|
|
_BR_ERR |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$0a |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
1091,6 → 1121,11
RTS |
|
_FAIL6 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$0c |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
1245,6 → 1280,11
RTS |
|
_FAIL7 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$0e |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
1414,6 → 1454,11
RTS |
|
_FAIL8 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$10 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
1601,6 → 1646,11
RTS |
|
_FAIL9 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$12 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
1644,6 → 1694,11
RTS |
|
_FAIL10 |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$14 |
STB R3,(R2,#0) |
|
SIF |
RTS |
|
/bench/verilog/tst_bench_top.v
44,6 → 44,7
module tst_bench_top(); |
|
parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number |
parameter STOP_ON_ERROR = 1'b0; |
|
// |
// wires && regs |
59,6 → 60,8
reg wait_mode; |
reg debug_mode; |
reg scantestmode; |
|
reg wbm_ack_i; |
|
|
wire [31:0] adr; |
84,6 → 87,11
wire [15:0] xgate_address; |
wire [15:0] write_mem_data; |
wire [15:0] read_mem_data; |
|
wire [15:0] wbm_dat_o; |
wire [15:0] wbm_dat_i; |
wire [15:0] wbm_adr_o; |
wire [ 1:0] wbm_sel_o; |
|
wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen; |
wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen; |
120,6 → 128,16
|
parameter COP_CNTRL_COP_EVENT = 16'h0100; // COP Enable interrupt request |
|
parameter CHECK_POINT = 16'h8000; |
parameter CHANNEL_ACK = CHECK_POINT + 2; |
parameter CHANNEL_ERR = CHECK_POINT + 4; |
reg [ 7:0] check_point_reg; |
reg [ 7:0] channel_ack_reg; |
reg [ 7:0] channel_err_reg; |
event check_point_wrt; |
event channel_ack_wrt; |
event channel_err_wrt; |
reg [15:0] error_count; |
|
// initial values and testbench setup |
initial |
132,6 → 150,11
wait_mode = 0; |
debug_mode = 0; |
scantestmode = 0; |
check_point_reg = 0; |
channel_ack_reg = 0; |
channel_err_reg = 0; |
error_count = 0; |
wbm_ack_i = 0; |
// channel_req = 0; |
|
`ifdef WAVES |
152,52 → 175,72
// generate clock |
always #20 mstr_test_clk = ~mstr_test_clk; |
|
// Keep a count of how many clocks we've simulated |
always @(posedge mstr_test_clk) |
vector = vector + 1; |
vector <= vector + 1; |
|
// Throw in some wait states from the memory |
always @(posedge mstr_test_clk) |
// if (((vector % 7) == 0) && (xgate.risc.cpu_state == 4'b0001)) |
// if (((vector % 5) == 0) && (xgate.risc.load_next_inst)) |
if ((vector % 5) == 0) |
wbm_ack_i <= 1'b0; |
else |
wbm_ack_i <= 1'b1; |
|
// Write memory interface to RAM |
always @(posedge mstr_test_clk) |
begin |
if (write_mem_strb_l && !write_mem_strb_h) |
ram_8[xgate_address] = write_mem_data[7:0]; |
if (write_mem_strb_h && !write_mem_strb_l) |
ram_8[xgate_address] = write_mem_data[7:0]; |
if (write_mem_strb_h && write_mem_strb_l) |
if (write_mem_strb_l && !write_mem_strb_h && wbm_ack_i) |
ram_8[xgate_address] <= write_mem_data[7:0]; |
if (write_mem_strb_h && !write_mem_strb_l && wbm_ack_i) |
ram_8[xgate_address] <= write_mem_data[7:0]; |
if (write_mem_strb_h && write_mem_strb_l && wbm_ack_i) |
begin |
ram_8[xgate_address] = write_mem_data[15:8]; |
ram_8[xgate_address+1] = write_mem_data[7:0]; |
ram_8[xgate_address] <= write_mem_data[15:8]; |
ram_8[xgate_address+1] <= write_mem_data[7:0]; |
end |
end |
|
parameter CHECK_POINT = 16'h8000; |
parameter CHANNEL_ACK = CHECK_POINT + 2; |
parameter CHANNEL_ERR = CHECK_POINT + 4; |
reg [ 7:0] check_point_reg; |
reg [ 7:0] channel_ack_reg; |
reg [ 7:0] channel_err_reg; |
// Special Memory Mapped Testbench Registers |
always @(posedge mstr_test_clk or negedge rstn) |
begin |
if (!rstn) |
begin |
check_point_reg = 0; |
channel_ack_reg = 0; |
channel_err_reg = 0; |
check_point_reg <= 0; |
channel_ack_reg <= 0; |
channel_err_reg <= 0; |
end |
if (write_mem_strb_l && (xgate_address == CHECK_POINT)) |
check_point_reg = write_mem_data[7:0]; |
if (write_mem_strb_l && (xgate_address == CHANNEL_ACK)) |
channel_ack_reg = write_mem_data[7:0]; |
if (write_mem_strb_l && (xgate_address == CHANNEL_ERR)) |
channel_err_reg = write_mem_data[7:0]; |
if (write_mem_strb_l && wbm_ack_i && (xgate_address == CHECK_POINT)) |
begin |
check_point_reg <= write_mem_data[7:0]; |
-> check_point_wrt; |
end |
if (write_mem_strb_l && wbm_ack_i && (xgate_address == CHANNEL_ACK)) |
begin |
channel_ack_reg <= write_mem_data[7:0]; |
-> channel_ack_wrt; |
end |
if (write_mem_strb_l && wbm_ack_i && (xgate_address == CHANNEL_ERR)) |
begin |
channel_err_reg <= write_mem_data[7:0]; |
-> channel_err_wrt; |
end |
end |
|
always @check_point_reg |
always @check_point_wrt |
$display("\nSoftware Checkpoint #%d -- at vector=%d\n", check_point_reg, vector); |
|
always @channel_err_wrt |
begin |
$display("\n ------ !!!!! Software Error #%d -- at vector=%d\n -------", channel_err_reg, vector); |
error_count = error_count + 1; |
if (STOP_ON_ERROR == 1'b1) |
wrap_up; |
end |
|
wire [ 6:0] current_active_channel = xgate.risc.xgchid; |
always @channel_ack_reg |
always @channel_ack_wrt |
clear_channel(current_active_channel); |
|
|
242,33 → 285,40
|
assign read_mem_data = {ram_8[xgate_address], ram_8[xgate_address+1]}; |
|
// hookup wishbone_COP_master core - Parameters take all default values |
// hookup XGATE core - Parameters take all default values |
// Async Reset, 16 bit Bus, 16 bit Granularity |
xgate_top #(.SINGLE_CYCLE(1'b0), |
.MAX_CHANNEL(MAX_CHANNEL)) // Max XGATE Interrupt Channel Number |
xgate( |
// wishbone interface |
.wbs_clk_i(mstr_test_clk), |
.wbs_rst_i(1'b0), // sync_reset |
.arst_i(rstn), // rstn |
.wbs_adr_i(adr[4:0]), |
.wbs_dat_i(dat_o), |
.wbs_dat_o(dat0_i), |
.wbs_we_i(we), |
.wbs_stb_i(stb0), |
.wbs_cyc_i(cyc), |
// Wishbone slave interface |
.wbs_clk_i( mstr_test_clk ), |
.wbs_rst_i( 1'b0 ), // sync_reset |
.arst_i( rstn ), // async resetn |
.wbs_adr_i( adr[4:0] ), |
.wbs_dat_i( dat_o ), |
.wbs_dat_o( dat0_i ), |
.wbs_we_i( we ), |
.wbs_stb_i( stb0 ), |
.wbs_cyc_i( cyc ), |
.wbs_sel_i( 2'b11 ), |
.wbs_ack_o(ack_1), |
.wbs_ack_o( ack_1 ), |
|
// Wishbone master Signals |
.wbm_dat_o( write_mem_data ), |
.wbm_we_o( wbm_we_o ), |
.wbm_stb_o( wbm_stb_o ), |
.wbm_cyc_o( wbm_cyc_o ), |
.wbm_sel_o( wbm_sel_o ), |
.wbm_adr_o( xgate_address ), |
.wbm_dat_i( read_mem_data ), |
.wbm_ack_i( wbm_ack_i ), |
|
.xgif( xgif ), // XGATE Interrupt Flag |
.risc_clk( mstr_test_clk ), |
.xgswt( xgswt), |
.xgswt( xgswt ), |
.chan_req_i( {channel_req[127:40], xgswt, channel_req[31:0]} ), |
.xgate_address( xgate_address ), |
.write_mem_strb_l( write_mem_strb_l ), |
.write_mem_strb_h( write_mem_strb_h ), |
.write_mem_data( write_mem_data ), |
.read_mem_data( read_mem_data ), |
.scantestmode( scantestmode ) |
); |
|
359,8 → 409,7
repeat(20) @(posedge mstr_test_clk); |
|
dump_ram(0); |
$display("\nTestbench done at vector=%d\n", vector); |
$finish; |
wrap_up; |
// |
// program core |
// |
369,8 → 418,7
|
repeat(10) @(posedge mstr_test_clk); |
|
$display("\nTestbench done at vector=%d\n", vector); |
$finish; |
wrap_up; |
end |
|
// Poll for XGATE Interrupt set |
554,6 → 602,18
end |
endtask |
|
task wrap_up; |
begin |
$display("\nSimulation Finished!! - vector =%d", vector); |
if (error_count == 0) |
$display("Simulation Passed"); |
else |
$display("Simulation Failed"); |
|
$finish; |
end |
endtask |
|
function [15:0] four_2_16; |
input [3:0] vector; |
begin |
/bench/verilog/jump_mem.v
1,44 → 1,45
|
@2000 29 3A |
@2000 29 8A |
@2012 56 FF |
@201E F2 00 FA 80 F3 FF 53 40 53 42 03 00 02 00 F2 00 FA 80 F3 01 53 40 53 42 F5 01 FD 4F 0C B0 2E 8C F6 0E 18 D0 24 89 0C 10 20 87 FD 00 0C B0 22 84 2E 83 18 10 24 81 F5 04 FD 81 F3 03 0D 71 20 7C |
@205E 2E 7B F4 20 FC F0 18 B0 24 77 F5 10 FD 88 F3 05 0D 72 20 72 F4 00 FC 02 18 B0 24 6E F5 88 FD 10 F3 04 0D 73 20 69 F4 08 FC 01 18 B0 24 65 F2 FF FA 07 F1 06 0A 34 20 60 F4 C0 FC FF 18 50 24 5C |
@209E F7 02 FF C3 F6 02 0F D5 20 57 F4 C0 FC 30 18 F0 24 53 F7 62 FF C3 F6 04 0F D6 2E 4E F4 2C FC 36 18 F0 24 4A F7 62 FF C3 F6 08 0F D6 2E 45 F4 C3 FC 62 18 F0 24 41 F5 00 FD 80 0D 09 20 3D 2E 3C |
@20DE F4 FF FC FF 18 B0 24 38 F5 01 FD 0F 0D 0A 20 34 F4 00 FC 00 18 B0 24 30 F5 FF FD 80 0D FB 22 2C F4 01 FC 00 18 B0 24 28 F2 1A FA FF 0A CC 20 24 F4 00 FC A0 18 50 24 20 F7 8F FF B2 0F 8D 20 1C |
@211E F4 B2 FC 00 18 F0 24 18 F7 62 FF C3 0F 8E 2E 14 F4 C3 FC 62 18 F0 24 10 F7 62 FF C3 0F CE 2E 0C F4 36 FC 2C 18 F0 24 08 F2 00 FA 80 F3 02 53 40 01 00 01 00 03 00 02 00 03 00 02 00 F2 00 FA 80 |
@215E F3 03 53 40 F3 02 53 42 F7 55 FF A5 87 00 24 AA 2E A9 2A A8 F3 00 FB A5 18 EC 24 A4 F7 C5 FF A5 87 80 28 A0 26 9F 2E 9E F3 80 FB A5 18 EC 24 9A F7 55 FF A5 8F 00 24 96 2E 95 2A 94 F3 55 FB 00 |
@219E 18 EC 24 90 F7 C5 FF A5 8F 80 28 8C 26 8B 2E 8A F3 C5 FB 80 18 EC 24 86 F7 55 FF A5 97 00 24 82 2E 81 2A 80 F7 C5 FF A5 97 80 28 7C 26 7B 2E 7A F7 55 FF A5 9F 00 24 76 2E 75 2A 74 F7 C5 FF A5 |
@21DE 9F 80 28 70 26 6F 2E 6E F2 0B 02 F9 F7 00 FF A5 A7 00 2A 68 24 67 2E 66 20 65 F3 00 FB A5 18 EC 24 61 F2 06 02 F9 F7 9F FF A5 A7 60 28 5B 26 5A 2E 59 22 58 F3 FF FB A5 18 EC 24 54 F2 0B 02 F9 |
@221E F7 88 FF 00 AF 00 2A 4E 24 4D 2E 4C 20 4B F3 88 FB 00 18 EC 24 47 F2 06 02 F9 F7 36 FF A1 AF 50 28 41 26 40 2E 3F 22 3E F3 36 FB F1 18 EC 24 3A F2 0B 02 F9 F7 C3 FF 96 B7 3C 2A 34 24 33 2E 32 |
@225E 20 31 F3 00 FB 96 18 EC 24 2D F2 06 02 F9 F6 00 FE A5 B6 73 28 27 26 26 2E 25 22 24 F3 8C FB A5 18 CC 24 20 F2 0B 02 F9 F7 C3 FF 96 BF 69 2A 1A 24 19 2E 18 20 17 F3 C3 FB 00 18 EC 24 13 F2 06 |
@229E 02 F9 F6 66 FE 66 BE 66 28 0D 26 0C 2E 0B 22 0A F3 66 FB FF 18 CC 24 06 F2 00 FA 80 F3 04 53 40 03 00 02 00 03 00 02 00 F2 00 FA 80 F3 05 53 40 F3 03 53 42 F2 0B 02 F9 F3 00 FB FF 03 F4 2A 82 |
@22DE 24 81 2E 80 20 7F F6 00 FE 00 18 CC 24 7B F2 06 02 F9 F6 83 FE 00 06 F4 28 75 26 74 2E 73 22 72 F3 83 FB FF 18 CC 24 6E F2 0A 02 F9 F4 00 FC 00 04 F5 2A 68 24 67 2E 66 22 65 F6 00 FE 00 18 D0 |
@231E 24 61 F2 0E 02 F9 F6 01 FE 03 06 F5 2A 5B 26 5A 2E 59 20 58 F3 01 FB 03 18 CC 24 54 F2 0A 02 F9 F6 55 FE AA F5 AA FD 55 13 B8 2A 4C 24 4B 2E 4A 22 49 18 0C 24 47 F7 55 FF AA F2 07 02 F9 14 DC |
@235E 28 41 26 40 2E 3F 20 3E 18 9C 25 AC F2 0A 02 F9 F6 00 F5 00 13 BA 2A 36 24 35 2E 34 22 33 18 0C 24 31 F7 55 FF AA F6 8A FE 10 F2 07 02 F9 14 DE 28 29 26 28 2E 27 20 26 F3 DF FB BA 18 8C 24 22 |
@239E F2 0A 02 F9 F1 55 F9 AA F5 AA FD 55 13 A7 2A 1A 24 19 2E 18 22 17 18 0C 24 15 F7 CC FF 33 F2 01 FA 40 02 F9 14 EB 28 0E 26 0D 2E 0C 20 0B F3 32 FB 8C 18 8C 24 07 F2 00 FA 80 F3 06 53 40 01 00 |
@23DE 03 00 02 00 03 00 02 00 F2 00 FA 80 F3 07 53 40 F3 04 53 42 F2 0E 02 F9 F6 34 F5 A6 FD C3 F4 FF 04 F4 64 BB 2A 54 26 53 2E 52 22 51 F7 0A 18 F0 24 4E F6 B8 64 BB F7 C3 18 F0 24 49 F2 06 02 F9 |
@241E F6 34 F5 A6 FD C3 F4 FF 04 F4 6C BB 28 40 26 3F 2E 3E 22 3D F7 6F FF FF 18 F0 24 39 F6 B0 6C BB F7 A6 FF F3 18 F0 24 33 F2 06 02 F9 F6 3C F5 A6 FD C3 F4 FF 04 F4 74 BB 28 2A 26 29 2E 28 22 27 |
@245E F7 FF FF 9F 18 F0 24 23 F6 78 74 BB F7 FF FF 59 18 F0 24 1D F2 06 02 F9 F6 38 F5 A6 FD C3 F4 FF FC FA 7C BB 28 14 26 13 2E 12 22 11 F7 FF FF F3 18 F0 24 0D F6 70 7C BB F7 A6 FF F3 18 F0 24 07 |
@249E F2 00 FA 80 F3 08 53 40 01 00 03 00 02 00 03 00 02 00 F2 00 FA 80 F3 09 53 40 F3 05 53 42 F2 00 02 F9 20 01 3C 66 F2 01 02 F9 20 63 F2 01 02 F9 22 01 3C 5F F2 00 02 F9 22 5C F2 04 02 F9 26 01 |
@24DE 3C 58 F2 00 02 F9 26 55 F2 00 02 F9 24 01 3C 51 F2 04 02 F9 24 4E F2 00 02 F9 28 01 3C 4A F2 08 02 F9 28 47 F2 08 02 F9 2A 01 3C 43 F2 00 02 F9 2A 40 F2 00 02 F9 2C 01 3C 3C F2 02 02 F9 2C 39 |
@251E F2 02 02 F9 2E 01 3C 35 F2 00 02 F9 2E 32 F2 01 02 F9 32 01 3C 2E F2 04 02 F9 32 01 3C 2A F2 00 02 F9 32 27 F2 0A 02 F9 34 01 3C 23 F2 05 02 F9 34 01 3C 1F F2 08 02 F9 34 1C F2 0A 02 F9 30 01 |
@255E 3C 18 F2 0B 02 F9 30 15 F2 0E 02 F9 30 12 F2 0A 02 F9 38 01 3C 0E F2 01 02 F9 38 01 3C 0A F2 0E 02 F9 38 07 F2 02 02 F9 38 04 F2 08 02 F9 38 01 3C 08 03 00 02 00 F2 00 FA 80 F3 0A 53 40 03 00 |
@259E 02 00 3F F9 F2 00 FA 80 F3 0B 53 40 F3 06 53 42 F4 00 05 FA 3C 08 F2 00 FA 80 F3 0C 53 40 03 00 02 00 03 00 02 00 F4 88 FC 99 F7 88 FF 99 18 F0 25 F8 05 F6 F2 00 FA 80 F3 0D 53 40 F3 07 53 42 |
@25DE F4 0F FC 01 F7 0E FF 01 F2 0F 02 F9 19 9C 2A 66 26 65 2E 64 22 63 F3 01 18 2C 24 60 F7 0F FF 01 F2 0B 02 F9 19 9C 2A 5A 24 59 2E 58 22 57 F4 11 FC 01 F7 0E FF 01 F2 0F 02 F9 19 9D 2A 4F 26 4E |
@261E 2E 4D 22 4C F3 02 18 2C 24 49 F4 0F FC 01 F7 0F FF 01 F2 0A 02 F9 19 9D 2A 41 24 40 2E 3F 22 3E F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9E 28 36 26 35 2C 34 22 33 F3 10 FB 80 18 2C 24 2F F4 00 |
@265E FC 80 F7 00 FF 80 F2 0F 02 F9 19 9E 2A 27 24 26 2C 25 20 24 18 20 24 22 F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9F 28 1A 26 19 2C 18 22 17 F3 11 FB 80 18 2C 24 13 F4 00 FC 80 F7 00 FF 80 F2 0C |
@269E 02 F9 19 9F 2A 0B 24 0A 2C 09 20 08 18 20 24 06 F2 00 FA 80 F3 0E 53 40 03 00 02 00 03 00 02 00 F2 00 FA 80 F3 0F 53 40 F3 08 53 42 F5 0F F2 0F 02 F9 C5 0E 2A 7C 26 7B 2E 7A 22 79 F3 01 18 AC |
@26DE 24 76 F7 0F F2 0D 02 F9 C7 10 28 71 26 70 2E 6F 20 6E F6 11 FE 81 F2 0D 02 F9 CE 70 2A 68 26 67 2C 66 22 65 F3 11 FB 11 18 CC 24 61 F6 00 FE 01 F2 06 02 F9 CE 02 28 5B 26 5A 2E 59 20 58 F5 0F |
@271E F2 0B 02 F9 D5 0F 2A 53 24 52 2E 51 22 50 F7 0F F2 07 02 F9 D7 10 28 4B 26 4A 2E 49 20 48 F5 00 FD 01 F2 0F 02 F9 DD 00 2A 42 24 41 2E 40 22 3F F2 06 02 F9 DD 02 28 3B 26 3A 2E 39 20 38 F5 0F |
@275E FD 70 F2 0E 02 F9 ED A0 2A 32 26 31 2E 30 20 2F F3 0F FB 10 18 AC 24 2B F2 07 02 F9 ED 70 28 27 26 26 2C 25 22 24 F3 0F FB 80 18 AC 24 20 F4 FF FC 70 F2 0E 02 F9 E4 01 2A 1A 26 19 2E 18 20 17 |
@279E F5 00 FD 71 18 94 24 13 F4 8E FC 7F F2 0C 02 F9 E4 81 28 0D 26 0C 2C 0B 20 0A F6 0F FE 80 18 98 24 06 F2 00 FA 80 F3 10 53 40 03 00 02 00 03 00 02 00 F2 00 FA 80 F3 11 53 40 F3 09 53 42 F1 AA |
@27DE F9 7F F2 55 FA 6F F3 66 FB 5F F7 FF FF FF 51 00 52 01 53 1F F4 00 45 80 46 81 47 9F D5 AA 24 83 D6 55 24 81 D7 66 24 7F F6 66 18 DC 24 7C 59 04 5A 06 5B 0A F4 00 F5 00 F6 00 F7 00 4D 84 4E 86 |
@281E 4F 8A 18 34 24 70 18 58 24 6E 18 7C 24 6C F1 CC F9 1F F2 99 FA 2F F4 20 F5 02 F6 07 71 94 72 98 65 94 66 98 D5 CC 24 5F F3 99 18 78 24 5C F1 CC F9 1F F2 99 FA 2F F4 30 F5 02 F6 08 79 94 7A 98 |
@285E 6D 94 6E 98 18 A4 24 4F 18 C8 24 4D F1 33 F9 1F F2 55 FA 2F F4 40 F5 02 F6 07 71 95 72 99 D5 03 24 42 D6 08 24 40 63 96 67 9A D5 02 24 3C D6 07 24 3A D3 33 24 38 F3 55 18 7C 24 35 F1 66 F9 1F |
@289E F2 99 FA 2F F4 50 F5 04 F6 09 71 96 72 9A D5 03 24 2A D6 08 24 28 63 95 67 99 D5 04 24 24 D6 09 24 22 D3 66 24 20 F3 99 18 7C 24 1D F1 AA F9 1F F2 CC FA 2F F4 60 F5 02 F6 08 79 95 7A 99 D5 04 |
@28DE 24 12 D6 0A 24 10 6B 96 6F 9A D5 02 24 0C D6 08 24 0A 18 2C 24 08 18 5C 24 06 F2 00 FA 80 F3 12 53 40 03 00 02 00 03 00 02 00 F2 00 FA 80 F3 13 53 40 F3 0A 53 42 F1 05 07 F2 20 0D 01 F3 20 0B |
@291E 06 F2 22 09 07 F0 01 F1 03 F2 F2 00 FA 80 F3 14 53 40 03 00 02 00 03 00 02 00 02 F8 01 F0 01 F1 07 F7 00 00 |
@FE04 20 2C 00 7B 21 5A 00 7B 22 C6 00 7B 23 E6 00 7B 24 B0 00 7B 25 A2 00 7B 25 D2 00 7B 26 BE 00 7B 27 D0 00 7B 29 08 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B |
@211E F4 B2 FC 00 18 F0 24 18 F7 62 FF C3 0F 8E 2E 14 F4 C3 FC 62 18 F0 24 10 F7 62 FF C3 0F CE 2E 0C F4 36 FC 2C 18 F0 24 08 F2 00 FA 80 F3 02 53 40 01 00 01 00 03 00 02 00 F2 04 FA 80 F3 02 53 40 |
@215E 03 00 02 00 F2 00 FA 80 F3 03 53 40 F3 02 53 42 F7 55 FF A5 87 00 24 AA 2E A9 2A A8 F3 00 FB A5 18 EC 24 A4 F7 C5 FF A5 87 80 28 A0 26 9F 2E 9E F3 80 FB A5 18 EC 24 9A F7 55 FF A5 8F 00 24 96 |
@219E 2E 95 2A 94 F3 55 FB 00 18 EC 24 90 F7 C5 FF A5 8F 80 28 8C 26 8B 2E 8A F3 C5 FB 80 18 EC 24 86 F7 55 FF A5 97 00 24 82 2E 81 2A 80 F7 C5 FF A5 97 80 28 7C 26 7B 2E 7A F7 55 FF A5 9F 00 24 76 |
@21DE 2E 75 2A 74 F7 C5 FF A5 9F 80 28 70 26 6F 2E 6E F2 0B 02 F9 F7 00 FF A5 A7 00 2A 68 24 67 2E 66 20 65 F3 00 FB A5 18 EC 24 61 F2 06 02 F9 F7 9F FF A5 A7 60 28 5B 26 5A 2E 59 22 58 F3 FF FB A5 |
@221E 18 EC 24 54 F2 0B 02 F9 F7 88 FF 00 AF 00 2A 4E 24 4D 2E 4C 20 4B F3 88 FB 00 18 EC 24 47 F2 06 02 F9 F7 36 FF A1 AF 50 28 41 26 40 2E 3F 22 3E F3 36 FB F1 18 EC 24 3A F2 0B 02 F9 F7 C3 FF 96 |
@225E B7 3C 2A 34 24 33 2E 32 20 31 F3 00 FB 96 18 EC 24 2D F2 06 02 F9 F6 00 FE A5 B6 73 28 27 26 26 2E 25 22 24 F3 8C FB A5 18 CC 24 20 F2 0B 02 F9 F7 C3 FF 96 BF 69 2A 1A 24 19 2E 18 20 17 F3 C3 |
@229E FB 00 18 EC 24 13 F2 06 02 F9 F6 66 FE 66 BE 66 28 0D 26 0C 2E 0B 22 0A F3 66 FB FF 18 CC 24 06 F2 00 FA 80 F3 04 53 40 03 00 02 00 F2 04 FA 80 F3 04 53 40 03 00 02 00 F2 00 FA 80 F3 05 53 40 |
@22DE F3 03 53 42 F2 0B 02 F9 F3 00 FB FF 03 F4 2A 82 24 81 2E 80 20 7F F6 00 FE 00 18 CC 24 7B F2 06 02 F9 F6 83 FE 00 06 F4 28 75 26 74 2E 73 22 72 F3 83 FB FF 18 CC 24 6E F2 0A 02 F9 F4 00 FC 00 |
@231E 04 F5 2A 68 24 67 2E 66 22 65 F6 00 FE 00 18 D0 24 61 F2 0E 02 F9 F6 01 FE 03 06 F5 2A 5B 26 5A 2E 59 20 58 F3 01 FB 03 18 CC 24 54 F2 0A 02 F9 F6 55 FE AA F5 AA FD 55 13 B8 2A 4C 24 4B 2E 4A |
@235E 22 49 18 0C 24 47 F7 55 FF AA F2 07 02 F9 14 DC 28 41 26 40 2E 3F 20 3E 18 9C 25 A8 F2 0A 02 F9 F6 00 F5 00 13 BA 2A 36 24 35 2E 34 22 33 18 0C 24 31 F7 55 FF AA F6 8A FE 10 F2 07 02 F9 14 DE |
@239E 28 29 26 28 2E 27 20 26 F3 DF FB BA 18 8C 24 22 F2 0A 02 F9 F1 55 F9 AA F5 AA FD 55 13 A7 2A 1A 24 19 2E 18 22 17 18 0C 24 15 F7 CC FF 33 F2 01 FA 40 02 F9 14 EB 28 0E 26 0D 2E 0C 20 0B F3 32 |
@23DE FB 8C 18 8C 24 07 F2 00 FA 80 F3 06 53 40 01 00 03 00 02 00 F2 04 FA 80 F3 06 53 40 03 00 02 00 F2 00 FA 80 F3 07 53 40 F3 04 53 42 F2 0E 02 F9 F6 34 F5 A6 FD C3 F4 FF 04 F4 64 BB 2A 54 26 53 |
@241E 2E 52 22 51 F7 0A 18 F0 24 4E F6 B8 64 BB F7 C3 18 F0 24 49 F2 06 02 F9 F6 34 F5 A6 FD C3 F4 FF 04 F4 6C BB 28 40 26 3F 2E 3E 22 3D F7 6F FF FF 18 F0 24 39 F6 B0 6C BB F7 A6 FF F3 18 F0 24 33 |
@245E F2 06 02 F9 F6 3C F5 A6 FD C3 F4 FF 04 F4 74 BB 28 2A 26 29 2E 28 22 27 F7 FF FF 9F 18 F0 24 23 F6 78 74 BB F7 FF FF 59 18 F0 24 1D F2 06 02 F9 F6 38 F5 A6 FD C3 F4 FF FC FA 7C BB 28 14 26 13 |
@249E 2E 12 22 11 F7 FF FF F3 18 F0 24 0D F6 70 7C BB F7 A6 FF F3 18 F0 24 07 F2 00 FA 80 F3 08 53 40 01 00 03 00 02 00 F2 04 FA 80 F3 08 53 40 03 00 02 00 F2 00 FA 80 F3 09 53 40 F3 05 53 42 F2 00 |
@24DE 02 F9 20 01 3C 66 F2 01 02 F9 20 63 F2 01 02 F9 22 01 3C 5F F2 00 02 F9 22 5C F2 04 02 F9 26 01 3C 58 F2 00 02 F9 26 55 F2 00 02 F9 24 01 3C 51 F2 04 02 F9 24 4E F2 00 02 F9 28 01 3C 4A F2 08 |
@251E 02 F9 28 47 F2 08 02 F9 2A 01 3C 43 F2 00 02 F9 2A 40 F2 00 02 F9 2C 01 3C 3C F2 02 02 F9 2C 39 F2 02 02 F9 2E 01 3C 35 F2 00 02 F9 2E 32 F2 01 02 F9 32 01 3C 2E F2 04 02 F9 32 01 3C 2A F2 00 |
@255E 02 F9 32 27 F2 0A 02 F9 34 01 3C 23 F2 05 02 F9 34 01 3C 1F F2 08 02 F9 34 1C F2 0A 02 F9 30 01 3C 18 F2 0B 02 F9 30 15 F2 0E 02 F9 30 12 F2 0A 02 F9 38 01 3C 0E F2 01 02 F9 38 01 3C 0A F2 0E |
@259E 02 F9 38 07 F2 02 02 F9 38 04 F2 08 02 F9 38 01 3C 0C F2 04 FA 80 F3 0A 53 40 03 00 02 00 F2 00 FA 80 F3 0A 53 40 03 00 02 00 3F F9 F2 00 FA 80 F3 0B 53 40 F3 06 53 42 F4 00 05 FA 3C 0C F2 00 |
@25DE FA 80 F3 0C 53 40 03 00 02 00 F2 04 FA 80 F3 0C 53 40 03 00 02 00 F4 88 FC 99 F7 88 FF 99 18 F0 25 F4 05 F6 F2 00 FA 80 F3 0D 53 40 F3 07 53 42 F4 0F FC 01 F7 0E FF 01 F2 0F 02 F9 19 9C 2A 66 |
@261E 26 65 2E 64 22 63 F3 01 18 2C 24 60 F7 0F FF 01 F2 0B 02 F9 19 9C 2A 5A 24 59 2E 58 22 57 F4 11 FC 01 F7 0E FF 01 F2 0F 02 F9 19 9D 2A 4F 26 4E 2E 4D 22 4C F3 02 18 2C 24 49 F4 0F FC 01 F7 0F |
@265E FF 01 F2 0A 02 F9 19 9D 2A 41 24 40 2E 3F 22 3E F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9E 28 36 26 35 2C 34 22 33 F3 10 FB 80 18 2C 24 2F F4 00 FC 80 F7 00 FF 80 F2 0F 02 F9 19 9E 2A 27 24 26 |
@269E 2C 25 20 24 18 20 24 22 F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9F 28 1A 26 19 2C 18 22 17 F3 11 FB 80 18 2C 24 13 F4 00 FC 80 F7 00 FF 80 F2 0C 02 F9 19 9F 2A 0B 24 0A 2C 09 20 08 18 20 24 06 |
@26DE F2 00 FA 80 F3 0E 53 40 03 00 02 00 F2 04 FA 80 F3 0E 53 40 03 00 02 00 F2 00 FA 80 F3 0F 53 40 F3 08 53 42 F5 0F F2 0F 02 F9 C5 0E 2A 7C 26 7B 2E 7A 22 79 F3 01 18 AC 24 76 F7 0F F2 0D 02 F9 |
@271E C7 10 28 71 26 70 2E 6F 20 6E F6 11 FE 81 F2 0D 02 F9 CE 70 2A 68 26 67 2C 66 22 65 F3 11 FB 11 18 CC 24 61 F6 00 FE 01 F2 06 02 F9 CE 02 28 5B 26 5A 2E 59 20 58 F5 0F F2 0B 02 F9 D5 0F 2A 53 |
@275E 24 52 2E 51 22 50 F7 0F F2 07 02 F9 D7 10 28 4B 26 4A 2E 49 20 48 F5 00 FD 01 F2 0F 02 F9 DD 00 2A 42 24 41 2E 40 22 3F F2 06 02 F9 DD 02 28 3B 26 3A 2E 39 20 38 F5 0F FD 70 F2 0E 02 F9 ED A0 |
@279E 2A 32 26 31 2E 30 20 2F F3 0F FB 10 18 AC 24 2B F2 07 02 F9 ED 70 28 27 26 26 2C 25 22 24 F3 0F FB 80 18 AC 24 20 F4 FF FC 70 F2 0E 02 F9 E4 01 2A 1A 26 19 2E 18 20 17 F5 00 FD 71 18 94 24 13 |
@27DE F4 8E FC 7F F2 0C 02 F9 E4 81 28 0D 26 0C 2C 0B 20 0A F6 0F FE 80 18 98 24 06 F2 00 FA 80 F3 10 53 40 03 00 02 00 F2 04 FA 80 F3 10 53 40 03 00 02 00 F2 00 FA 80 F3 11 53 40 F3 09 53 42 F1 AA |
@281E F9 7F F2 55 FA 6F F3 66 FB 5F F7 FF FF FF 51 00 52 01 53 1F F4 00 45 80 46 81 47 9F D5 AA 24 83 D6 55 24 81 D7 66 24 7F F6 66 18 DC 24 7C 59 04 5A 06 5B 0A F4 00 F5 00 F6 00 F7 00 4D 84 4E 86 |
@285E 4F 8A 18 34 24 70 18 58 24 6E 18 7C 24 6C F1 CC F9 1F F2 99 FA 2F F4 20 F5 02 F6 07 71 94 72 98 65 94 66 98 D5 CC 24 5F F3 99 18 78 24 5C F1 CC F9 1F F2 99 FA 2F F4 30 F5 02 F6 08 79 94 7A 98 |
@289E 6D 94 6E 98 18 A4 24 4F 18 C8 24 4D F1 33 F9 1F F2 55 FA 2F F4 40 F5 02 F6 07 71 95 72 99 D5 03 24 42 D6 08 24 40 63 96 67 9A D5 02 24 3C D6 07 24 3A D3 33 24 38 F3 55 18 7C 24 35 F1 66 F9 1F |
@28DE F2 99 FA 2F F4 50 F5 04 F6 09 71 96 72 9A D5 03 24 2A D6 08 24 28 63 95 67 99 D5 04 24 24 D6 09 24 22 D3 66 24 20 F3 99 18 7C 24 1D F1 AA F9 1F F2 CC FA 2F F4 60 F5 02 F6 08 79 95 7A 99 D5 04 |
@291E 24 12 D6 0A 24 10 6B 96 6F 9A D5 02 24 0C D6 08 24 0A 18 2C 24 08 18 5C 24 06 F2 00 FA 80 F3 12 53 40 03 00 02 00 F2 04 FA 80 F3 12 53 40 03 00 02 00 F2 00 FA 80 F3 13 53 40 F3 0A 53 42 F1 05 |
@295E 07 F2 20 0D 01 F3 20 0B 06 F2 22 09 07 F0 01 F1 03 F2 F2 00 FA 80 F3 14 53 40 03 00 02 00 F2 04 FA 80 F3 14 53 40 03 00 02 00 02 F8 07 F7 00 00 |
@FE04 20 2C 00 7B 21 62 00 7B 22 D6 00 7B 23 FE 00 7B 24 D0 00 7B 25 CA 00 7B 26 02 00 7B 26 F6 00 7B 28 10 00 7B 29 50 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B |
@FE44 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B |
@FE84 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B |
@FEC4 20 1E 00 7B 20 1E 00 7B |
/rtl/verilog/xgate_wbs_bus.v
54,7 → 54,7
input wbs_stb_i, // stobe/core select signal |
input wbs_cyc_i, // valid bus cycle input |
input [1:0] wbs_sel_i, // Select byte in word bus transaction |
// COP Control Signals |
// XGATE Control Signals |
output reg write_xgmctl, // Write Strobe for XGMCTL register |
output reg write_xgisp74,// Write Strobe for XGISP74 register |
output reg write_xgisp30,// Write Strobe for XGISP30 register |
/rtl/verilog/xgate_risc.v
64,6 → 64,7
input [15:0] perif_data, |
input risc_clk, |
input async_rst_b, |
input mem_req_ack, // Memory Bus available - data good |
input xge, // XGATE Module Enable |
input xgfrz, // Stop XGATE in Freeze Mode |
input xgdbg, // XGATE Debug Mode |
96,15 → 97,16
integer bfi, bfii, bfix; // Loop counter for Bit Field Insert function |
|
// State machine sequence |
parameter [2:0] //synopsys enum state_info |
IDLE = 3'b000, // waiting for interrupt |
CONT = 3'b001, // Instruction processing state, first state |
STALL = 3'b010, // Second step in 2 state instruction (Memory Read/Write) |
DEBUG = 3'b011, // |
BOOT_1 = 3'b100, // |
BOOT_2 = 3'b101, // |
BOOT_3 = 3'b110, // |
UNDEF5 = 3'b111; // |
parameter [3:0] //synopsys enum state_info |
IDLE = 4'b0000, // waiting for interrupt |
CONT = 4'b0001, // Instruction processing state, first state |
DEBUG = 4'b0011, // |
BOOT_1 = 4'b0100, // |
BOOT_2 = 4'b0101, // |
BOOT_3 = 4'b0110, // |
S_STALL = 4'b0111, // Simple Stall while updating PC after change of flow |
W_STALL = 4'b1000, // Stall while doing memory word read access |
B_STALL = 4'b1001; // Stall while doing memory byte read access |
|
|
// Semaphore states |
113,8 → 115,8
HOST_LOCK = 2'b11; |
|
|
reg [ 2:0] cpu_state; |
reg [ 2:0] next_cpu_state; // Pseudo Register, |
reg [ 3:0] cpu_state; |
reg [ 3:0] next_cpu_state; // Pseudo Register, |
reg load_next_inst; // Pseudo Register, |
reg [15:0] program_counter; |
reg [15:0] next_pc; // Pseudo Register, |
206,13 → 208,13
wrt_sel_xgr6 = 1'b0; |
wrt_sel_xgr7 = 1'b0; |
case (wrt_reg_sel) |
3'b001 : wrt_sel_xgr1 = 1'b1; |
3'b010 : wrt_sel_xgr2 = 1'b1; |
3'b011 : wrt_sel_xgr3 = 1'b1; |
3'b100 : wrt_sel_xgr4 = 1'b1; |
3'b101 : wrt_sel_xgr5 = 1'b1; |
3'b110 : wrt_sel_xgr6 = 1'b1; |
3'b111 : wrt_sel_xgr7 = 1'b1; |
3'b001 : wrt_sel_xgr1 = mem_req_ack; |
3'b010 : wrt_sel_xgr2 = mem_req_ack; |
3'b011 : wrt_sel_xgr3 = mem_req_ack; |
3'b100 : wrt_sel_xgr4 = mem_req_ack; |
3'b101 : wrt_sel_xgr5 = mem_req_ack; |
3'b110 : wrt_sel_xgr6 = mem_req_ack; |
3'b111 : wrt_sel_xgr7 = mem_req_ack; |
endcase |
end |
|
256,13 → 258,12
end |
end |
|
|
// CPU State Register |
always @(posedge risc_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
cpu_state <= IDLE; |
else |
cpu_state <= next_cpu_state; |
cpu_state <= mem_req_ack ? next_cpu_state : cpu_state; |
|
// CPU Instruction Register |
always @(posedge risc_clk or negedge async_rst_b) |
269,7 → 270,7
if ( !async_rst_b ) |
op_code <= 16'h0000; |
else |
op_code <= load_next_inst ? read_mem_data : op_code; |
op_code <= (load_next_inst && mem_req_ack) ? read_mem_data : op_code; |
|
// Active Channel Latch |
always @(posedge risc_clk or negedge async_rst_b) |
276,7 → 277,7
if ( !async_rst_b ) |
xgchid <= 7'b0; |
else |
xgchid <= (cpu_state == IDLE) ? int_req : xgchid; |
xgchid <= ((cpu_state == IDLE) && mem_req_ack) ? int_req : xgchid; |
|
// CPU Read Data Buffer Register |
always @(posedge risc_clk or negedge async_rst_b) |
283,7 → 284,7
if ( !async_rst_b ) |
load_data <= 16'h0000; |
else |
load_data <= (data_access && !data_write) ? read_mem_data : load_data; |
load_data <= (data_access && !data_write && mem_req_ack) ? read_mem_data : load_data; |
|
// Program Counter Register |
always @(posedge risc_clk or negedge async_rst_b) |
290,7 → 291,7
if ( !async_rst_b ) |
program_counter <= 16'h0000; |
else |
program_counter <= next_pc; |
program_counter <= mem_req_ack ? next_pc : program_counter; |
|
// ALU Flag Bits |
always @(posedge risc_clk or negedge async_rst_b) |
303,10 → 304,10
end |
else |
begin |
carry_flag <= write_xgccr ? perif_data[0] : next_carry; |
overflow_flag <= write_xgccr ? perif_data[1] : next_overflow; |
zero_flag <= write_xgccr ? perif_data[2] : next_zero; |
negative_flag <= write_xgccr ? perif_data[3] : next_negative; |
carry_flag <= write_xgccr ? perif_data[0] : (mem_req_ack ? next_carry : carry_flag); |
overflow_flag <= write_xgccr ? perif_data[1] : (mem_req_ack ? next_overflow : overflow_flag); |
zero_flag <= write_xgccr ? perif_data[2] : (mem_req_ack ? next_zero : zero_flag); |
negative_flag <= write_xgccr ? perif_data[3] : (mem_req_ack ? next_negative : negative_flag); |
end |
|
// Interrupt Flag next value |
480,6 → 481,31
next_pc = program_counter; |
end |
|
// Pause here while program counter change of flow or memory write access |
// Load next instruction and increment PC |
{S_STALL, 16'b????????????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Pause here for memory read word access |
// Load next instruction and increment PC |
{W_STALL, 16'b????????????????} : |
begin |
alu_result = load_data; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Pause here for memory read byte access |
// Load next instruction and increment PC |
{B_STALL, 16'b????????????????} : |
begin |
alu_result = {8'h00, load_data[15:8]}; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// ----------------------------------------------------------------------- |
// Instruction Group -- Return to Scheduler and Others |
// ----------------------------------------------------------------------- |
601,7 → 627,7
// Cycles - PP |
{CONT, 16'b00000???11110110} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
609,11 → 635,6
next_pc = rd_data; |
end |
|
{STALL, 16'b00000???11110110} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = SIF RS, Op Code = 0 0 0 0 0 RS 1 1 1 1 0 1 1 1 |
// Sets the Interrupt Flag associated with the channel id number |
// contained in RS[6:0] is set. The content of RS[15:7] is ignored |
1081,17 → 1102,12
begin |
if (!carry_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010000?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BCS REL9, Op Code = 0 0 1 0 0 0 1 REL9 |
// Branch if Carry Set |
// If C = 1, then PC + $0002 + (REL9 << 1) => PC |
1100,17 → 1116,12
begin |
if (carry_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010001?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BNE REL9, Op Code = 0 0 1 0 0 1 0 REL9 |
// Branch if Not Equal |
// If Z = 0, then PC + $0002 + (REL9 << 1) => PC |
1119,17 → 1130,12
begin |
if (!zero_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010010?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BEQ REL9, Op Code = 0 0 1 0 0 1 1 REL9 |
// Branch if Equal |
// If Z = 1, then PC + $0002 + (REL9 << 1) => PC |
1138,17 → 1144,12
begin |
if (zero_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010011?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BPL REL9, Op Code = 0 0 1 0 1 0 0 REL9 |
// Branch if Plus |
// If N = 0, then PC + $0002 + (REL9 << 1) => PC |
1157,17 → 1158,12
begin |
if (!negative_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010100?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BMI REL9, Op Code = 0 0 1 0 1 0 1 REL9 |
// Branch if Minus |
// If N = 1, then PC + $0002 + (REL9 << 1) => PC |
1176,17 → 1172,12
begin |
if (negative_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010101?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BVC REL9, Op Code = 0 0 1 0 1 1 0 REL9 |
// Branch if Overflow Cleared |
// If V = 0, then PC + $0002 + (REL9 << 1) => PC |
1195,17 → 1186,12
begin |
if (!overflow_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010110?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BVS REL9, Op Code = 0 0 1 0 1 1 1 REL9 |
// Branch if Overflow Set |
// If V = 1, then PC + $0002 + (REL9 << 1) => PC |
1214,17 → 1200,12
begin |
if (overflow_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0010111?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BHI REL9, Op Code = 0 0 1 1 0 0 0 REL9 |
// Branch if Higher |
// If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC |
1233,17 → 1214,12
begin |
if (!(carry_flag || zero_flag)) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0011000?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BLS REL9, Op Code = 0 0 1 1 0 0 1 REL9 |
// Branch if Lower or Same |
// If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC |
1252,17 → 1228,12
begin |
if (carry_flag || zero_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0011001?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BGE REL9, Op Code = 0 0 1 1 0 1 0 REL9 |
// Branch if Greater than or Equal to Zero |
// If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC |
1271,17 → 1242,12
begin |
if (!(negative_flag ^ overflow_flag)) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0011010?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BLT REL9, Op Code = 0 0 1 1 0 1 1 REL9 |
// Branch if Lower than Zero |
// If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC |
1290,17 → 1256,12
begin |
if (negative_flag ^ overflow_flag) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0011011?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BGT REL9, Op Code = 0 0 1 1 1 0 0 REL9 |
// Branch if Greater than Zero |
// If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC |
1309,17 → 1270,12
begin |
if (!(zero_flag || (negative_flag ^ overflow_flag))) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0011100?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BLE REL9, Op Code = 0 0 1 1 1 0 1 REL9 |
// Branch if Less or Equal to Zero |
// If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC |
1328,17 → 1284,12
begin |
if (zero_flag || (negative_flag ^ overflow_flag)) |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{6{op_code[8]}}, op_code[8:0], 1'b0}; |
end |
end |
|
{STALL, 16'b0011101?????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = BRA REL10, Op Code = 0 0 1 1 1 1 REL10 |
// Branch Always, signed offset |
// PC + $0002 + (REL10 << 1) => PC |
1345,15 → 1296,11
// Cycles - PP |
{CONT, 16'b001111??????????} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter + {{5{op_code[9]}}, op_code[9:0], 1'b0}; |
end |
|
{STALL, 16'b001111??????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// ----------------------------------------------------------------------- |
// Instruction Group -- Load and Store Instructions |
1366,7 → 1313,7
// Cycles - Pr |
{CONT, 16'b01000???????????} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = B_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1373,14 → 1320,6
data_address = rs1_data + {11'b0, op_code[4:0]}; |
end |
|
{STALL, 16'b01000???????????} : |
begin |
next_cpu_state = CONT; |
alu_result = {8'h00, load_data[15:8]}; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = LDW RD, (RB, #OFFS5), Op Code = 0 1 0 0 1 RD RB OFFS5 |
// Load Word from Memory, unsigned offset |
// M[RB, #OFFS5] => RD |
1388,7 → 1327,7
// Cycles - PR |
{CONT, 16'b01001???????????} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = W_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1396,14 → 1335,6
data_word_op = 1'b1; |
end |
|
{STALL, 16'b01001???????????} : |
begin |
next_cpu_state = CONT; |
alu_result = load_data; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = STB RS, (RB, #OFFS5), Op Code = 0 1 0 1 0 RS RB OFFS5 |
// Store Byte to Memory, unsigned offset |
// RS.L => M[RB, #OFFS5] |
1411,7 → 1342,7
// Cycles - Pw |
{CONT, 16'b01010???????????} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1419,12 → 1350,6
data_address = rs1_data + {11'b0, op_code[4:0]}; |
end |
|
{STALL, 16'b01010???????????} : |
begin |
next_cpu_state = CONT; |
end |
|
|
// Instruction = STW RS, (RB, #OFFS5), Op Code = 0 1 0 1 1 RS RB OFFS5 |
// Store Word to Memory, unsigned offset |
// RS => M[RB, #OFFS5] |
1432,7 → 1357,7
// Cycles - PW |
{CONT, 16'b01011???????????} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1441,11 → 1366,6
data_word_op = 1'b1; |
end |
|
{STALL, 16'b01011???????????} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = LDB RD, (RB, RI), Op Code = 0 1 1 0 0 RD RB RI 0 0 |
// Load Byte from Memory |
// M[RB, RI] => RD.L; $00 => RD.H |
1453,7 → 1373,7
// Cycles - Pr |
{CONT, 16'b01100?????????00} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = B_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1460,14 → 1380,6
data_address = rs1_data + rs2_data; |
end |
|
{STALL, 16'b01100?????????00} : |
begin |
next_cpu_state = CONT; |
alu_result = {8'h00, load_data[15:8]}; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = LDW RD, (RB, RI), Op Code = 0 1 1 0 1 RD RB RI 0 0 |
// Load Word from Memory |
// M[RB, RI] => RD |
1475,7 → 1387,7
// Cycles - PR |
{CONT, 16'b01101?????????00} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = W_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1483,14 → 1395,6
data_word_op = 1'b1; |
end |
|
{STALL, 16'b01101?????????00} : |
begin |
next_cpu_state = CONT; |
alu_result = load_data; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = STB RS, (RB, RI), Op Code = 0 1 1 1 0 RS RB RI 0 0 |
// RS.L => M[RB, RI] |
// Store Byte to Memory |
1498,7 → 1402,7
// Cycles - Pw |
{CONT, 16'b01110?????????00} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1506,11 → 1410,6
data_address = rs1_data + rs2_data; |
end |
|
{STALL, 16'b01110?????????00} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = STW RS, (RB, RI), Op Code = 0 1 1 1 1 RS RB RI 0 0 |
// Store Word to Memory |
// RS => M[RB, RI] |
1518,7 → 1417,7
// Cycles - PW |
{CONT, 16'b01111?????????00} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1527,11 → 1426,6
data_word_op = 1'b1; |
end |
|
{STALL, 16'b01111?????????00} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = LDB RD, (RB, RI+), Op Code = 0 1 1 0 0 RD RB RI 0 1 |
// Load Byte from Memory |
// M[RB, RI] => RD.L; $00 => RD.H; RI+1 => RI |
1541,7 → 1435,7
// Cycles - Pr |
{CONT, 16'b01100?????????01} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = B_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1552,14 → 1446,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01100?????????01} : |
begin |
next_cpu_state = CONT; |
alu_result = {8'h00, load_data[15:8]}; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = LDW RD, (RB, RI+), Op Code = 0 1 1 0 1 RD RB RI 0 1 |
// Load Word from Memory |
// M[RB, RI] => RD; RI+2 => RI |
1569,7 → 1455,7
// Cycles - PR |
{CONT, 16'b01101?????????01} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = W_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1581,14 → 1467,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01101?????????01} : |
begin |
next_cpu_state = CONT; |
alu_result = load_data; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = STB RS, (RB, RI+), Op Code = 0 1 1 1 0 RS RB RI 0 1 |
// Store Byte to Memory |
// RS.L => M[RB, RI]; RI+1 => RI |
1596,7 → 1474,7
// Cycles - Pw |
{CONT, 16'b01110?????????01} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1608,11 → 1486,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01110?????????01} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = STW RS, (RB, RI+), Op Code = 0 1 1 1 1 RS RB RI 0 1 |
// Store Word to Memory |
// RS => M[RB, RI]; RI+2 => RI |
1620,7 → 1493,7
// Cycles - PW |
{CONT, 16'b01111?????????01} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1633,11 → 1506,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01111?????????01} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = LDB RD, (RB, -RI), Op Code = 0 1 1 0 0 RD RB RI 1 0 |
// Load Byte from Memory |
// RI-1 => RI; M[RS, RI] => RD.L; $00 => RD.H |
1645,7 → 1513,7
// Cycles - Pr |
{CONT, 16'b01100?????????10} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = B_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1656,14 → 1524,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01100?????????10} : |
begin |
next_cpu_state = CONT; |
alu_result = {8'h00, load_data[15:8]}; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = LDW RD, (RB, -RI), Op Code = 0 1 1 0 1 RD RB RI 1 0 |
// Load Word from Memory |
// RI-2 => RI; M[RS, RI] => RD |
1671,7 → 1531,7
// Cycles - PR |
{CONT, 16'b01101?????????10} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = W_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1683,14 → 1543,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01101?????????10} : |
begin |
next_cpu_state = CONT; |
alu_result = load_data; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
end |
|
// Instruction = STB RS, (RB, -RI), Op Code = 0 1 1 1 0 RS RB RI 1 0 |
// Store Byte to Memory |
// RI-1 => RI; RS.L => M[RB, RI] |
1700,7 → 1552,7
// Cycles - Pw |
{CONT, 16'b01110?????????10} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1712,11 → 1564,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01110?????????10} : |
begin |
next_cpu_state = CONT; |
end |
|
// Instruction = STW RS, (RB, -RI), Op Code = 0 1 1 1 1 RS RB RI 1 0 |
// Store Word to Memory |
// RI-2 => RI; RS => M[RB, RI] |
1726,7 → 1573,7
// Cycles - PW |
{CONT, 16'b01111?????????10} : |
begin |
next_cpu_state = STALL; |
next_cpu_state = S_STALL; |
load_next_inst = 1'b0; |
next_pc = program_counter; |
data_access = 1'b1; |
1739,11 → 1586,6
ena_rd_high_byte = 1'b1; |
end |
|
{STALL, 16'b01111?????????10} : |
begin |
next_cpu_state = CONT; |
end |
|
// ----------------------------------------------------------------------- |
// Instruction Group -- Bit Field Instructions |
// ----------------------------------------------------------------------- |
1754,7 → 1596,7
// Cycles - P |
{CONT, 16'b01100?????????11} : |
begin |
ena_rd_low_byte = 1'b1; |
ena_rd_low_byte = 1'b1; |
ena_rd_high_byte = 1'b1; |
shift_ammount = {1'b0, rs2_data[3:0]}; |
for (bfi = 0; bfi <= 15; bfi = bfi + 1) |
2074,6 → 1916,7
|
assign semaph_stat = |risc_semap; |
|
// A "generate" statment would be good here but it's not supported in iverilog |
// Semaphore Bit |
semaphore_bit semaphore_0( |
// outputs |
/rtl/verilog/xgate_top.v
43,32 → 43,37
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number |
parameter DWIDTH = 16) // Data bus width |
( |
// Wishbone Signals |
output [DWIDTH-1:0] wbs_dat_o, // databus output |
output wbs_ack_o, // bus cycle acknowledge output |
input wbs_clk_i, // master clock input |
input wbs_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [4:0] wbs_adr_i, // lower address bits |
input [DWIDTH-1:0] wbs_dat_i, // databus input |
input wbs_we_i, // write enable input |
input wbs_stb_i, // stobe/core select signal |
input wbs_cyc_i, // valid bus cycle input |
input [1:0] wbs_sel_i, // Select byte in word bus transaction |
// Wishbone Slave Signals |
output [DWIDTH-1:0] wbs_dat_o, // databus output |
output wbs_ack_o, // bus cycle acknowledge output |
input wbs_clk_i, // master clock input |
input wbs_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [4:0] wbs_adr_i, // lower address bits |
input [DWIDTH-1:0] wbs_dat_i, // databus input |
input wbs_we_i, // write enable input |
input wbs_stb_i, // stobe/core select signal |
input wbs_cyc_i, // valid bus cycle input |
input [1:0] wbs_sel_i, // Select byte in word bus transaction |
// Wishbone Master Signals |
output [DWIDTH-1:0] wbm_dat_o, // databus output |
output wbm_we_o, // write enable output |
output wbm_stb_o, // stobe/core select signal |
output wbm_cyc_o, // valid bus cycle output |
output [ 1:0] wbm_sel_o, // Select byte in word bus transaction |
output [15:0] wbm_adr_o, // Address bits |
input [DWIDTH-1:0] wbm_dat_i, // databus input |
input wbm_ack_i, // bus cycle acknowledge input |
// XGATE IO Signals |
output [ 7:0] xgswt, // XGATE Software Trigger Register |
output [15:0] xgate_address, |
output [ 7:0] xgswt, // XGATE Software Trigger Register |
output write_mem_strb_l, // Strobe for writing low data byte |
output write_mem_strb_h, // Strobe for writing high data bye |
output [15:0] write_mem_data, |
output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag |
input [15:0] read_mem_data, |
input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request |
input risc_clk, // Clock for RISC core |
input scantestmode // Chip in in scan test mode |
); |
|
|
wire zero_flag; |
wire negative_flag; |
wire carry_flag; |
128,7 → 133,11
wire [ 6:0] xgchid; // Channel actively being processed |
wire [15:1] xgvbr; // XGATE vector Base Address Register |
|
wire [ 2:0] semaph_risc; // Semaphore register select from RISC |
wire [15:0] xgate_address; // |
wire [15:0] write_mem_data; // |
wire [15:0] read_mem_data; // |
wire mem_req_ack; // |
|
wire [ 7:0] host_semap; // Semaphore status for host |
// wire [15:0] write_mem_data; |
// wire [15:0] read_mem_data; |
138,7 → 147,7
// --------------------------------------------------------------------------- |
// Wishbone Slave Bus interface |
xgate_wbs_bus #(.ARST_LVL(ARST_LVL), |
.SINGLE_CYCLE(SINGLE_CYCLE)) |
.SINGLE_CYCLE(SINGLE_CYCLE)) |
wishbone_s( |
.wbs_dat_o( wbs_dat_o ), |
.wbs_ack_o( wbs_ack_o ), |
285,12 → 294,13
.perif_data( wbs_dat_i ), |
.async_rst_b( async_rst_b ), |
.read_mem_data( read_mem_data ), |
.mem_req_ack( mem_req_ack ), |
.xge( xge ), |
.xgfrz( xgfrz ), |
.xgdbg( xgdbg ), |
.xgss( xgss ), |
.xgvbr( xgvbr ), |
.int_req(int_req), |
.int_req( int_req ), |
.write_xgsem( write_xgsem ), |
.write_xgccr( write_xgccr ), |
.write_xgpc( write_xgpc ), |
320,6 → 330,31
.chan_req_i( chan_req_i ) |
); |
|
// --------------------------------------------------------------------------- |
// Wishbone Master Bus interface |
xgate_wbm_bus #(.ARST_LVL(ARST_LVL)) |
wishbone_m( |
// Wishbone Master Signals |
.wbm_dat_o( wbm_dat_o ), |
.wbm_we_o( wbm_we_o ), |
.wbm_stb_o( wbm_stb_o ), |
.wbm_cyc_o( wbm_cyc_o ), |
.wbm_sel_o( wbm_sel_o ), |
.wbm_adr_o( wbm_adr_o ), |
.wbm_dat_i( wbm_dat_i ), |
.wbm_ack_i( wbm_ack_i ), |
.wbs_clk_i( wbs_clk_i ), |
.wbs_rst_i( wbs_rst_i ), |
.arst_i( arst_i ), |
// XGATE Control Signals |
.read_mem_data( read_mem_data ), |
.xgate_address( xgate_address ), |
.mem_req_ack( mem_req_ack ), |
.write_mem_strb_l( write_mem_strb_l ), |
.write_mem_strb_h( write_mem_strb_h ), |
.write_mem_data( write_mem_data ) |
); |
|
|
endmodule // xgate_top |
|
/doc/src/xgate_Structure.ppt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/sim/verilog/run/run_iverilog
14,6 → 14,7
\ |
$xgate/rtl/verilog/xgate_top.v \ |
$xgate/rtl/verilog/xgate_wbs_bus.v \ |
$xgate/rtl/verilog/xgate_wbm_bus.v \ |
$xgate/rtl/verilog/xgate_regs.v \ |
$xgate/rtl/verilog/xgate_risc.v \ |
$xgate/rtl/verilog/xgate_irq_encode.v \ |
/README.txt
1,4 → 1,17
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
Sept 10,2009 |
Added WISHBONE master bus submodule and some related top level signals but still |
not much real functionality. |
|
Added code to allow for memory access stalls. |
|
Upgraded testbench to insert memory wait states. Added more error detection |
and summery. |
|
Improved instruction decoder. Still needs more work to remove redundant adders |
to improve synthesis results. |
|
|
Sept 1, 2009 |
This is a prerelease checkin and should be looked at as an incremental backup |
and not representative of what may be in the final release. |
14,4 → 27,5
All things related to debug mode. |
WISHBONE master bus interface. |
|
User Documentation - 30% done |
User Documentation - 30% done |
|