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https://opencores.org/ocsvn/xgate/xgate/trunk
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/xgate/trunk
- from Rev 66 to Rev 67
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Rev 66 → Rev 67
/rtl/verilog/xgate_wbs_bus.v
40,16 → 40,17
|
module xgate_wbs_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level |
parameter DWIDTH = 16, |
parameter WB_RD_DEFAULT = 0, // WISHBONE Read Bus default state |
parameter SINGLE_CYCLE = 1'b0) |
( |
// Wishbone Signals |
output reg [DWIDTH-1:0] wbs_dat_o, // databus output - Pseudo Register |
output [DWIDTH-1:0] wbs_dat_o, // databus output - Pseudo Register |
output wbs_ack_o, // bus cycle acknowledge output |
output wbs_err_o, // bus error, lost module select durning wait state |
input wbs_clk_i, // master clock input |
input wbs_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [ 5:1] wbs_adr_i, // lower address bits |
input [ 6:1] wbs_adr_i, // lower address bits |
input [DWIDTH-1:0] wbs_dat_i, // databus input |
input wbs_we_i, // write enable input |
input wbs_stb_i, // stobe/core select signal |
80,24 → 81,37
output reg [1:0] write_xgr3, // Write Strobe for XGATE Data Register R3 |
output reg [1:0] write_xgr2, // Write Strobe for XGATE Data Register R2 |
output reg [1:0] write_xgr1, // Write Strobe for XGATE Data Register R1 |
output async_rst_b, // |
output sync_reset, // |
input [415:0] read_regs // status register bits |
output reg [1:0] write_irw_en_7, // Write Strobe for Interrupt Bypass Control Register 7 |
output reg [1:0] write_irw_en_6, // Write Strobe for Interrupt Bypass Control Register 6 |
output reg [1:0] write_irw_en_5, // Write Strobe for Interrupt Bypass Control Register 5 |
output reg [1:0] write_irw_en_4, // Write Strobe for Interrupt Bypass Control Register 4 |
output reg [1:0] write_irw_en_3, // Write Strobe for Interrupt Bypass Control Register 3 |
output reg [1:0] write_irw_en_2, // Write Strobe for Interrupt Bypass Control Register 2 |
output reg [1:0] write_irw_en_1, // Write Strobe for Interrupt Bypass Control Register 1 |
output reg [1:0] write_irw_en_0, // Write Strobe for Interrupt Bypass Control Register 0 |
output async_rst_b, // |
output sync_reset, // |
input [415:0] read_risc_regs, // status register bits for WISHBONE Read bus |
input [127:0] irq_bypass // IRQ status bits WISHBONE Read bus |
); |
|
|
// registers |
reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state |
reg [4:0] addr_latch; // Capture WISHBONE Address |
reg [5:0] addr_latch; // Capture WISHBONE Address |
|
reg write_reserv1; // Dummy Reg decode for Reserved address |
reg write_reserv2; // Dummy Reg decode for Reserved address |
|
reg [DWIDTH-1:0] read_mux_irq; // Psudo register for WISHBONE IRQ read data bus mux |
|
// Wires |
wire module_sel; // This module is selected for bus transaction |
wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal) |
wire wbs_racc; // WISHBONE Read Access (Clock gating signal) |
wire [4:0] address; // Select either direct or latched address |
wire [5:0] address; // Select either direct or latched address |
|
reg [DWIDTH-1:0] read_mux_risc; // Pseudo regester for WISHBONE RISC read data bus mux |
|
// |
// module body |
114,9 → 128,11
assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel); |
assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state; |
assign address = SINGLE_CYCLE ? wbs_adr_i : addr_latch; |
|
assign wbs_dat_o = read_mux_risc | read_mux_irq; |
|
// generate acknowledge output signal, By using register all accesses takes two cycles. |
// Accesses in back to back clock cycles are not possable. |
// Accesses in back to back clock cycles are not possible. |
always @(posedge wbs_clk_i or negedge async_rst_b) |
if (!async_rst_b) |
bus_wait_state <= 1'b0; |
131,40 → 147,40
if ( module_sel ) // Clock gate for power saving |
addr_latch <= wbs_adr_i; |
|
// WISHBONE Read Data Mux |
// WISHBONE Read Data Mux for RISC status and control registers |
always @* |
case (address) // synopsys parallel_case |
case ({wbs_racc, address}) // synopsys parallel_case |
// 16 bit Bus, 16 bit Granularity |
5'b0_0000: wbs_dat_o = read_regs[ 15: 0]; |
5'b0_0001: wbs_dat_o = read_regs[ 31: 16]; |
5'b0_0010: wbs_dat_o = read_regs[ 47: 32]; |
5'b0_0011: wbs_dat_o = read_regs[ 63: 48]; |
5'b0_0100: wbs_dat_o = read_regs[ 79: 64]; |
5'b0_0101: wbs_dat_o = read_regs[ 95: 80]; |
5'b0_0110: wbs_dat_o = read_regs[111: 96]; |
5'b0_0111: wbs_dat_o = read_regs[127:112]; |
5'b0_1000: wbs_dat_o = read_regs[143:128]; |
5'b0_1001: wbs_dat_o = read_regs[159:144]; |
5'b0_1010: wbs_dat_o = read_regs[175:160]; |
5'b0_1011: wbs_dat_o = read_regs[191:176]; |
5'b0_1100: wbs_dat_o = read_regs[207:192]; |
5'b0_1101: wbs_dat_o = read_regs[223:208]; |
5'b0_1110: wbs_dat_o = read_regs[239:224]; |
5'b0_1111: wbs_dat_o = read_regs[255:240]; |
5'b1_0000: wbs_dat_o = read_regs[271:256]; |
5'b1_0001: wbs_dat_o = read_regs[287:272]; |
5'b1_0010: wbs_dat_o = read_regs[303:288]; |
5'b1_0011: wbs_dat_o = read_regs[319:304]; |
5'b1_0100: wbs_dat_o = read_regs[335:320]; |
5'b1_0101: wbs_dat_o = read_regs[351:336]; |
5'b1_0110: wbs_dat_o = read_regs[367:352]; |
5'b1_0111: wbs_dat_o = read_regs[383:368]; |
5'b1_1000: wbs_dat_o = read_regs[399:384]; |
5'b1_1001: wbs_dat_o = read_regs[415:400]; |
default: wbs_dat_o = 16'h0000; |
7'b100_0000: read_mux_risc = read_risc_regs[ 15: 0]; |
7'b100_0001: read_mux_risc = read_risc_regs[ 31: 16]; |
7'b100_0010: read_mux_risc = read_risc_regs[ 47: 32]; |
7'b100_0011: read_mux_risc = read_risc_regs[ 63: 48]; |
7'b100_0100: read_mux_risc = read_risc_regs[ 79: 64]; |
7'b100_0101: read_mux_risc = read_risc_regs[ 95: 80]; |
7'b100_0110: read_mux_risc = read_risc_regs[111: 96]; |
7'b100_0111: read_mux_risc = read_risc_regs[127:112]; |
7'b100_1000: read_mux_risc = read_risc_regs[143:128]; |
7'b100_1001: read_mux_risc = read_risc_regs[159:144]; |
7'b100_1010: read_mux_risc = read_risc_regs[175:160]; |
7'b100_1011: read_mux_risc = read_risc_regs[191:176]; |
7'b100_1100: read_mux_risc = read_risc_regs[207:192]; |
7'b100_1101: read_mux_risc = read_risc_regs[223:208]; |
7'b100_1110: read_mux_risc = read_risc_regs[239:224]; |
7'b100_1111: read_mux_risc = read_risc_regs[255:240]; |
7'b101_0000: read_mux_risc = read_risc_regs[271:256]; |
7'b101_0001: read_mux_risc = read_risc_regs[287:272]; |
7'b101_0010: read_mux_risc = read_risc_regs[303:288]; |
7'b101_0011: read_mux_risc = read_risc_regs[319:304]; |
7'b101_0100: read_mux_risc = read_risc_regs[335:320]; |
7'b101_0101: read_mux_risc = read_risc_regs[351:336]; |
7'b101_0110: read_mux_risc = read_risc_regs[367:352]; |
7'b101_0111: read_mux_risc = read_risc_regs[383:368]; |
7'b101_1000: read_mux_risc = read_risc_regs[399:384]; |
7'b101_1001: read_mux_risc = read_risc_regs[415:400]; |
default: read_mux_risc = {DWIDTH{WB_RD_DEFAULT}}; |
endcase |
|
// generate wishbone write register strobes |
// generate wishbone write register strobes for Xgate RISC |
always @* |
begin |
write_reserv1 = 1'b0; |
196,34 → 212,75
if (wbs_wacc) |
case (address) // synopsys parallel_case |
// 16 bit Bus, 8 bit Granularity |
5'b0_0000 : write_xgmctl = &wbs_sel_i; |
5'b0_0001 : write_xgchid = wbs_sel_i[0]; |
5'b0_0010 : write_xgisp74 = 1'b1; |
5'b0_0011 : write_xgisp30 = 1'b1; |
5'b0_0100 : write_xgvbr = wbs_sel_i; |
5'b0_0101 : write_xgif_7 = wbs_sel_i; |
5'b0_0110 : write_xgif_6 = wbs_sel_i; |
5'b0_0111 : write_xgif_5 = wbs_sel_i; |
5'b0_1000 : write_xgif_4 = wbs_sel_i; |
5'b0_1001 : write_xgif_3 = wbs_sel_i; |
5'b0_1010 : write_xgif_2 = wbs_sel_i; |
5'b0_1011 : write_xgif_1 = wbs_sel_i; |
5'b0_1100 : write_xgif_0 = wbs_sel_i; |
5'b0_1101 : write_xgswt = &wbs_sel_i; |
5'b0_1110 : write_xgsem = &wbs_sel_i; |
5'b0_1111 : write_reserv1 = 1'b1; |
5'b1_0000 : write_xgccr = wbs_sel_i[0]; |
5'b1_0001 : write_xgpc = wbs_sel_i; |
5'b1_0010 : write_reserv2 = 1'b1; |
5'b1_0011 : write_xgr1 = wbs_sel_i; |
5'b1_0100 : write_xgr2 = wbs_sel_i; |
5'b1_0101 : write_xgr3 = wbs_sel_i; |
5'b1_0110 : write_xgr4 = wbs_sel_i; |
5'b1_0111 : write_xgr5 = wbs_sel_i; |
5'b1_1000 : write_xgr6 = wbs_sel_i; |
5'b1_1001 : write_xgr7 = wbs_sel_i; |
6'b00_0000 : write_xgmctl = &wbs_sel_i; |
6'b00_0001 : write_xgchid = wbs_sel_i[0]; |
6'b00_0010 : write_xgisp74 = 1'b1; |
6'b00_0011 : write_xgisp30 = 1'b1; |
6'b00_0100 : write_xgvbr = wbs_sel_i; |
6'b00_0101 : write_xgif_7 = wbs_sel_i; |
6'b00_0110 : write_xgif_6 = wbs_sel_i; |
6'b00_0111 : write_xgif_5 = wbs_sel_i; |
6'b00_1000 : write_xgif_4 = wbs_sel_i; |
6'b00_1001 : write_xgif_3 = wbs_sel_i; |
6'b00_1010 : write_xgif_2 = wbs_sel_i; |
6'b00_1011 : write_xgif_1 = wbs_sel_i; |
6'b00_1100 : write_xgif_0 = wbs_sel_i; |
6'b00_1101 : write_xgswt = &wbs_sel_i; |
6'b00_1110 : write_xgsem = &wbs_sel_i; |
6'b00_1111 : write_reserv1 = 1'b1; |
6'b01_0000 : write_xgccr = wbs_sel_i[0]; |
6'b01_0001 : write_xgpc = wbs_sel_i; |
6'b01_0010 : write_reserv2 = 1'b1; |
6'b01_0011 : write_xgr1 = wbs_sel_i; |
6'b01_0100 : write_xgr2 = wbs_sel_i; |
6'b01_0101 : write_xgr3 = wbs_sel_i; |
6'b01_0110 : write_xgr4 = wbs_sel_i; |
6'b01_0111 : write_xgr5 = wbs_sel_i; |
6'b01_1000 : write_xgr6 = wbs_sel_i; |
6'b01_1001 : write_xgr7 = wbs_sel_i; |
default: ; |
endcase |
end |
|
// WISHBONE Read Data Mux for IRQ control registers |
always @* |
case ({wbs_racc, address}) // synopsys parallel_case |
// 16 bit Bus, 16 bit Granularity |
7'b110_0000: read_mux_irq = irq_bypass[ 15: 0]; |
7'b110_0001: read_mux_irq = irq_bypass[ 31: 16]; |
7'b110_0010: read_mux_irq = irq_bypass[ 47: 32]; |
7'b110_0011: read_mux_irq = irq_bypass[ 63: 48]; |
7'b110_0100: read_mux_irq = irq_bypass[ 79: 64]; |
7'b110_0101: read_mux_irq = irq_bypass[ 95: 80]; |
7'b110_0110: read_mux_irq = irq_bypass[111: 96]; |
7'b110_0111: read_mux_irq = irq_bypass[127:112]; |
default: read_mux_irq = {DWIDTH{WB_RD_DEFAULT}}; |
endcase |
|
// generate wishbone write register strobes for interrupt control |
always @* |
begin |
write_irw_en_7 = 2'b00; |
write_irw_en_6 = 2'b00; |
write_irw_en_5 = 2'b00; |
write_irw_en_4 = 2'b00; |
write_irw_en_3 = 2'b00; |
write_irw_en_2 = 2'b00; |
write_irw_en_1 = 2'b00; |
write_irw_en_0 = 2'b00; |
if (wbs_wacc) |
case (address) // synopsys parallel_case |
// 16 bit Bus, 8 bit Granularity |
6'b10_0000 : write_irw_en_0 = wbs_sel_i; |
6'b10_0001 : write_irw_en_1 = wbs_sel_i; |
6'b10_0010 : write_irw_en_2 = wbs_sel_i; |
6'b10_0011 : write_irw_en_3 = wbs_sel_i; |
6'b10_0100 : write_irw_en_4 = wbs_sel_i; |
6'b10_0101 : write_irw_en_5 = wbs_sel_i; |
6'b10_0110 : write_irw_en_6 = wbs_sel_i; |
6'b10_0111 : write_irw_en_7 = wbs_sel_i; |
default: ; |
endcase |
end |
|
endmodule // xgate_wbs_bus |
/rtl/verilog/xgate_irq_encode.v
41,23 → 41,33
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module xgate_irq_encode #(parameter MAX_CHANNEL = 127) // Max XGATE Interrupt Channel Number |
( |
output reg [ 6:0] int_req, // Encoded interrupt request |
output reg [ 6:0] int_req, // Encoded interrupt request to RISC |
output [MAX_CHANNEL:0] xgif, // Interrupt outputs to Host |
|
input [MAX_CHANNEL:0] chan_req_i // XGATE Interrupt request |
input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt requests from peropherials |
input [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt bypass |
input [MAX_CHANNEL:0] xgif_status // Interrupt outputs from RISC core |
); |
|
// Set int_reg to the index of the index of the highest chen_req_i input that is active |
wire [MAX_CHANNEL:0] chan_ena_gate; // Ouptut of channel enable gating |
|
// Pass non-bypassed interrupt inputs to XGATE RISC |
assign chan_ena_gate = ~chan_bypass & chan_req_i; |
|
// Set int_reg to the index of the index of the lowest chan_req_i input that is active |
integer i = 0; |
always @(chan_req_i) |
always @(chan_ena_gate) |
begin |
int_req = 0; |
for (i = 0; i <= MAX_CHANNEL; i = i + 1) |
if (chan_req_i[i] == 1'b1) |
for (i = MAX_CHANNEL; i >= 0; i = i - 1) |
if (chan_ena_gate[i] == 1'b1) |
int_req = i; |
end |
|
// XGATE output interrupt mux |
assign xgif = (chan_bypass & chan_req_i) | (~chan_bypass & xgif_status); |
|
|
|
endmodule // xgate_irq_encode |
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/rtl/verilog/xgate_regs.v
62,6 → 62,8
output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag |
output semaph_stat, // Return Status of Semaphore bit |
output reg brk_irq_ena, // Enable BRK instruction to generate interrupt |
output [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt enable or bypass |
output reg [127:0] irq_bypass, // Register to hold irq bypass control state |
|
input bus_clk, // Control register bus clock |
input async_rst_b, // Async reset signal |
77,12 → 79,24
input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2 |
input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1 |
input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0 |
input write_xgswt, // Write Strobe for XGSWT register |
input debug_ack // Clear debug register |
input [ 1:0] write_irw_en_7, // Write Strobe for Interrupt Bypass Control Register 7 |
input [ 1:0] write_irw_en_6, // Write Strobe for Interrupt Bypass Control Register 6 |
input [ 1:0] write_irw_en_5, // Write Strobe for Interrupt Bypass Control Register 5 |
input [ 1:0] write_irw_en_4, // Write Strobe for Interrupt Bypass Control Register 4 |
input [ 1:0] write_irw_en_3, // Write Strobe for Interrupt Bypass Control Register 3 |
input [ 1:0] write_irw_en_2, // Write Strobe for Interrupt Bypass Control Register 2 |
input [ 1:0] write_irw_en_1, // Write Strobe for Interrupt Bypass Control Register 1 |
input [ 1:0] write_irw_en_0, // Write Strobe for Interrupt Bypass Control Register 0 |
input write_xgswt, // Write Strobe for XGSWT register |
input debug_ack // Clear debug register |
); |
|
|
integer j; // Loop counter for channel bypass counter assigments |
integer k; // Loop counter for channel bypass counter assigments |
|
// registers |
reg [127:0] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register |
|
// Wires |
wire [ 1:0] write_any_xgif; |
103,7 → 117,7
xgdbg_clear <= 1'b0; |
xgss <= 1'b0; |
xgfact <= 1'b0; |
brk_irq_ena <= 1'b0; |
brk_irq_ena <= 1'b0; |
xgsweif_c <= 1'b0; |
xgie <= 1'b0; |
end |
115,7 → 129,7
xgdbg_clear <= 1'b0; |
xgss <= 1'b0; |
xgfact <= 1'b0; |
brk_irq_ena <= 1'b0; |
brk_irq_ena <= 1'b0; |
xgsweif_c <= 1'b0; |
xgie <= 1'b0; |
end |
208,18 → 222,70
else if (sync_reset) |
xgswt <= 8'h00; |
else if (write_xgswt) |
begin |
xgswt[7] <= write_bus[15] ? write_bus[7] : xgswt[7]; |
xgswt[6] <= write_bus[14] ? write_bus[6] : xgswt[6]; |
xgswt[5] <= write_bus[13] ? write_bus[5] : xgswt[5]; |
xgswt[4] <= write_bus[11] ? write_bus[4] : xgswt[4]; |
xgswt[3] <= write_bus[12] ? write_bus[3] : xgswt[3]; |
xgswt[2] <= write_bus[10] ? write_bus[2] : xgswt[2]; |
xgswt[1] <= write_bus[ 9] ? write_bus[1] : xgswt[1]; |
xgswt[0] <= write_bus[ 8] ? write_bus[0] : xgswt[0]; |
end |
xgswt <= (write_bus[15:8] & write_bus[7:0]) | (~write_bus[15:8] & xgswt[7:0]); |
|
|
// Channel Bypass Register input bits |
always @* |
begin |
k = 0; |
for (j = 0; j <= 127; j = j + 1) |
begin |
if (j <= MAX_CHANNEL) |
begin |
if ((j >= 0) && (j < 8)) |
irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 8) && (j < 16)) |
irq_bypass_d[j] = write_irw_en_0[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 16) && (j < 24)) |
irq_bypass_d[j] = write_irw_en_1[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 24) && (j < 32)) |
irq_bypass_d[j] = write_irw_en_1[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 32) && (j < 40)) |
irq_bypass_d[j] = write_irw_en_2[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 40) && (j < 48)) |
irq_bypass_d[j] = write_irw_en_2[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 48) && (j < 56)) |
irq_bypass_d[j] = write_irw_en_3[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 56) && (j < 64)) |
irq_bypass_d[j] = write_irw_en_3[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 64) && (j < 72)) |
irq_bypass_d[j] = write_irw_en_4[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 72) && (j < 80)) |
irq_bypass_d[j] = write_irw_en_4[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 80) && (j < 88)) |
irq_bypass_d[j] = write_irw_en_5[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 88) && (j < 96)) |
irq_bypass_d[j] = write_irw_en_5[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 96) && (j < 104)) |
irq_bypass_d[j] = write_irw_en_6[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 104) && (j < 112)) |
irq_bypass_d[j] = write_irw_en_6[1] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 112) && (j < 120)) |
irq_bypass_d[j] = write_irw_en_7[0] ? write_bus[k] : irq_bypass[j]; |
if ((j >= 120) && (j < 128)) |
irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j]; |
end |
else |
irq_bypass_d[j] = 1'b0; |
k = k + 1; |
if (k > 15) |
k = 0; |
end |
end |
|
// Channel Bypass Registers |
// Synthesys should eliminate bits that with D input tied to zero |
always @(posedge bus_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
irq_bypass <= {128{1'b1}}; |
else |
irq_bypass <= irq_bypass_d; |
|
// Alias the register name to the output pin name so only the used bit are carried out |
// assign chan_bypass = {(MAX_CHANNEL+1){1'b1}}; |
assign chan_bypass = irq_bypass[MAX_CHANNEL:0]; |
|
endmodule // xgate_regs |
|
|
/rtl/verilog/xgate_risc.v
456,22 → 456,22
xgif_d[j] = xgif_status[j] || (set_irq_flag == j); |
j = j + 1; |
end |
if (clear_xgif_0) |
xgif_d[15: 0] = ~clear_xgif_data & xgif_status[15: 0]; |
if (clear_xgif_1) |
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16]; |
if (clear_xgif_2) |
xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32]; |
if (clear_xgif_3) |
xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48]; |
if (clear_xgif_4) |
xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64]; |
if (clear_xgif_5) |
xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80]; |
if (clear_xgif_6) |
xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96]; |
if (clear_xgif_7) |
xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112]; |
if (clear_xgif_0) |
xgif_d[15: 0] = ~clear_xgif_data & xgif_status[15: 0]; |
if (clear_xgif_1) |
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16]; |
if (clear_xgif_2) |
xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32]; |
if (clear_xgif_3) |
xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48]; |
if (clear_xgif_4) |
xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64]; |
if (clear_xgif_5) |
xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80]; |
if (clear_xgif_6) |
xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96]; |
if (clear_xgif_7) |
xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112]; |
end |
|
// Interrupt Flag Registers |
/rtl/verilog/xgate_top.v
41,7 → 41,7
module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level |
parameter SINGLE_CYCLE = 1'b0, // |
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number |
parameter DWIDTH = 16) // Data bus width |
parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state |
( |
// Wishbone Slave Signals |
output [DWIDTH-1:0] wbs_dat_o, // databus output |
50,7 → 50,7
input wbs_clk_i, // master clock input |
input wbs_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [5:1] wbs_adr_i, // lower address bits |
input [6:1] wbs_adr_i, // lower address bits |
input [DWIDTH-1:0] wbs_dat_i, // databus input |
input wbs_we_i, // write enable input |
input wbs_stb_i, // stobe/core select signal |
68,7 → 68,7
// XGATE IO Signals |
output [ 7:0] xgswt, // XGATE Software Trigger Register |
output xg_sw_irq, // Xgate Software interrupt |
output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag |
output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag to Host |
input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request |
input risc_clk, // Clock for RISC core |
input debug_mode_i, // Force RISC core into debug mode |
76,6 → 76,8
input scantestmode // Chip in in scan test mode |
); |
|
parameter DWIDTH = 16; // Data bus width |
|
wire zero_flag; |
wire negative_flag; |
wire carry_flag; |
99,6 → 101,14
wire [1:0] write_xgif_2; // Write Strobe for Interrupt Flag Register 2 |
wire [1:0] write_xgif_1; // Write Strobe for Interrupt Flag Register 1 |
wire [1:0] write_xgif_0; // Write Strobe for Interrupt Flag Register 0 |
wire [1:0] write_irw_en_7; // Write Strobe for Interrupt Bypass Control Register 7 |
wire [1:0] write_irw_en_6; // Write Strobe for Interrupt Bypass Control Register 6 |
wire [1:0] write_irw_en_5; // Write Strobe for Interrupt Bypass Control Register 5 |
wire [1:0] write_irw_en_4; // Write Strobe for Interrupt Bypass Control Register 4 |
wire [1:0] write_irw_en_3; // Write Strobe for Interrupt Bypass Control Register 3 |
wire [1:0] write_irw_en_2; // Write Strobe for Interrupt Bypass Control Register 2 |
wire [1:0] write_irw_en_1; // Write Strobe for Interrupt Bypass Control Register 1 |
wire [1:0] write_irw_en_0; // Write Strobe for Interrupt Bypass Control Register 0 |
wire write_xgswt; // Write Strobe for XGSWT register |
wire write_xgsem; // Write Strobe for XGSEM register |
wire write_xgccr; // Write Strobe for XGATE Condition Code Register |
120,6 → 130,7
wire clear_xgif_1; // Strobe for decode to clear interrupt flag bank 1 |
wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0 |
wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag |
wire [MAX_CHANNEL:0] chan_bypass; // XGATE Interrupt enable or bypass |
|
wire xge; // XGATE Module Enable |
wire xgfrz; // Stop XGATE in Freeze Mode |
131,7 → 142,9
wire xgie; // XGATE Interrupt Enable |
wire [ 6:0] int_req; // Encoded interrupt request |
wire [ 6:0] xgchid; // Channel actively being processed |
wire [127:0] xgif_status; // Status bits of interrupt output flags that have been set |
wire [127:0] xgif_status; // Status bits of interrupt output flags that have been set |
wire [127:0] irq_bypass; // IRQ status bits WISHBONE Read bus |
|
wire [15:1] xgvbr; // XGATE vector Base Address Register |
wire brk_irq_ena; // Enable BRK instruction to generate interrupt |
|
150,11 → 163,11
wire write_mem_strb_l; // Strobe for writing low data byte |
wire write_mem_strb_h; // Strobe for writing high data bye |
|
assign xgif = xgif_status[MAX_CHANNEL:0]; |
// --------------------------------------------------------------------------- |
// Wishbone Slave Bus interface |
xgate_wbs_bus #(.ARST_LVL(ARST_LVL), |
.SINGLE_CYCLE(SINGLE_CYCLE)) |
.SINGLE_CYCLE(SINGLE_CYCLE), |
.WB_RD_DEFAULT(WB_RD_DEFAULT)) |
wishbone_s( |
.wbs_dat_o( wbs_dat_o ), |
.wbs_ack_o( wbs_ack_o ), |
193,9 → 206,17
.write_xgr3( write_xgr3 ), |
.write_xgr2( write_xgr2 ), |
.write_xgr1( write_xgr1 ), |
.write_irw_en_7( write_irw_en_7 ), |
.write_irw_en_6( write_irw_en_6 ), |
.write_irw_en_5( write_irw_en_5 ), |
.write_irw_en_4( write_irw_en_4 ), |
.write_irw_en_3( write_irw_en_3 ), |
.write_irw_en_2( write_irw_en_2 ), |
.write_irw_en_1( write_irw_en_1 ), |
.write_irw_en_0( write_irw_en_0 ), |
// inputs |
.async_rst_b ( async_rst_b ), |
.read_regs ( // in -- read register bits |
.async_rst_b( async_rst_b ), |
.read_risc_regs( // in -- read register bits |
{ xgr7, // XGR7 |
xgr6, // XGR6 |
xgr5, // XGR5 |
223,7 → 244,9
{8'b0, 1'b0, xgchid}, // XGCHID |
{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL |
} |
) |
), |
.irq_bypass( irq_bypass ) |
|
); |
|
// --------------------------------------------------------------------------- |
251,6 → 274,8
.clear_xgif_1( clear_xgif_1 ), |
.clear_xgif_0( clear_xgif_0 ), |
.clear_xgif_data( clear_xgif_data ), |
.irq_bypass( irq_bypass ), |
.chan_bypass( chan_bypass ), |
|
// inputs |
.async_rst_b( async_rst_b ), |
267,6 → 292,14
.write_xgif_2( write_xgif_2 ), |
.write_xgif_1( write_xgif_1 ), |
.write_xgif_0( write_xgif_0 ), |
.write_irw_en_7( write_irw_en_7 ), |
.write_irw_en_6( write_irw_en_6 ), |
.write_irw_en_5( write_irw_en_5 ), |
.write_irw_en_4( write_irw_en_4 ), |
.write_irw_en_3( write_irw_en_3 ), |
.write_irw_en_2( write_irw_en_2 ), |
.write_irw_en_1( write_irw_en_1 ), |
.write_irw_en_0( write_irw_en_0 ), |
.write_xgswt( write_xgswt ), |
.debug_ack( debug_ack ) |
); |
341,9 → 374,12
xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL)) |
irq_encode( |
// outputs |
.xgif( xgif ), |
.int_req( int_req ), |
// inputs |
.chan_req_i( chan_req_i ) |
.chan_req_i( chan_req_i ), |
.chan_bypass( chan_bypass ), |
.xgif_status( xgif_status ) |
); |
|
// --------------------------------------------------------------------------- |