URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
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- This comparison shows the changes necessary to convert path
/xgate
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/trunk/sw/tools/srec_2_verilog/srec_2_verilog.c
0,0 → 1,226
/* Verilog ROM Generator/Programer Rev B March 12 1996 Bob Hayes */ |
/* Started work on S-Record Writer Nov. 6, 1996 -- working except parity */ |
|
/* Rev 1.1 Sept. 11, 2009 - Bob Hayes - Update to create output file name */ |
/* from input file name by changing extension to .v */ |
|
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
|
FILE * open_read_file (char *); |
FILE * open_write_file (char *); |
int Get_ROM_Byte (FILE *, int *); |
void Make_Ref_Mem (FILE *, FILE *); |
|
|
/* ************************************************************************** */ |
|
/* ************************************************************************** */ |
int main(int argc, char *argv[]) |
{ |
int i, j, k = 0; |
char c; |
FILE *file1, *file2; |
file1 = NULL; |
file2 = NULL; |
|
printf("\nConvert S-record to Verilog memory file\n"); |
|
if (argc != 2) |
{ |
printf("Usage: %s filename\n", argv[0]); |
exit(1); |
} |
|
file1 = open_read_file(argv[1]); |
file2 = open_write_file(argv[1]); |
Make_Ref_Mem(file1, file2); |
fclose(file1); |
fclose(file2); |
|
printf("\n All done now!\n"); |
return 0; |
} |
|
|
/* ************************************************************************** */ |
/* 45678901234567890123456789012345678901234567890123456789012345678901234567 */ |
/* ************************************************************************** */ |
|
/* ************************************************************************** */ |
int Get_ROM_Byte (FILE *f1, int *S_Addr) |
{ |
static int Addr = 0, Count = 0, Sum = 0, Flag = 0; |
static int Max_Count = 0, Parity; |
static unsigned char c, *ch; |
static char EOL_str[80]; |
static int i, j, k, OK, Byte; |
static long int Line_cnt = 0, Byte_cnt = 0; |
|
if (Flag == 0 ) |
{ |
Flag = 1; |
/* This code is to read first line of miscellaneous data */ |
OK = fscanf(f1, "%c", &c); /* Read the "S" */ |
OK = fscanf(f1, "%1x", &i); /* Read the type number */ |
OK = fscanf(f1, "%2x", &Max_Count); /* Read the byte count */ |
if ( c != 'S' ) |
{ |
printf("Error in S-Records, No -S-, S = %c, i = %i, Max = %i\n", c, i, Max_Count); |
printf("Line Number = %i, Byte Number = %i\n", Line_cnt, Byte_cnt); |
} |
if ( i != 0 ) |
rewind(f1); /* Back-up if there is no comment line */ |
else |
{ |
printf("First S-Record info line is:\n"); |
for (j = 1; j <= Max_Count-1; ++j) |
{ |
fscanf(f1, "%2x", &k); |
if (( k >= ' ') && (k <= '~')) |
printf("%c",k); |
} |
printf("\n\n"); |
fgets(EOL_str, 10, f1); /* pick-up parity and other junk */ |
} |
} |
|
if ( Count == 0 ) |
{ |
Sum = 0; |
OK = fscanf(f1, "%c", &c); /* Read the "S" */ |
OK = fscanf(f1, "%1x", &i); /* Read the type number */ |
OK = fscanf(f1, "%2x", &Max_Count); /* Read the byte count */ |
if ( c != 'S' ) |
{ |
printf("Error in S-Records, No -S-, S = %c, i = %i, Max = %i\n", c, i, Max_Count); |
printf("Line Number = %i, Byte Number = %i\n", Line_cnt, Byte_cnt); |
} |
switch (i) |
{ |
case 1: |
case 9: |
Max_Count = Max_Count - 2; |
OK = fscanf(f1, "%4x", &Addr); |
break; |
case 2: |
case 8: |
Max_Count = Max_Count - 3; |
OK = fscanf(f1, "%6x", &Addr); |
break; |
case 3: |
case 7: |
Max_Count = Max_Count - 4; |
OK = fscanf(f1, "%8x", &Addr); |
break; |
default : |
printf("Error in S-Record file! Unrecognized TYPE Number\n"); |
break; |
} |
} |
|
if ( Max_Count > 1) /* Make sure there is at least one byte of data */ |
{ |
OK = fscanf(f1, "%2x", &Byte); /* Read a Byte of Data */ |
Sum = Sum + Byte; /* Increment the parity count */ |
++Count; |
++Byte_cnt; |
} |
|
if ( Count == (Max_Count - 1)) /* Do the parity check */ |
{ |
Count = 0; |
OK = fscanf(f1, "%2x", &Parity); /* Read the parity from the S-Record File */ |
Sum = 0xFF & ~Sum; |
/* printf("Line = %d, Sum = %2x, Parity = %2x\n", Line_cnt, Sum, Parity); */ |
++Line_cnt; |
|
c = ' '; |
while (( c != 'S') && ((k = feof(f1)) == 0)) |
OK = fscanf(f1, "%c", &c); /* Eat up end of line */ |
|
if (( k = feof(f1)) != 0) |
printf("found EOF in S-Record file\n %i Lines Processed\n", Line_cnt); |
else |
ungetc(c, f1); |
} |
|
/* printf("Read Byte = %x, Count = %i, Max_Count = %i \n", Byte, Count, Max_Count); */ |
|
*S_Addr = Addr; |
return Byte; |
} |
|
|
/* *************************************************************************************** */ |
/* Convert S-record to Verilog memory file *********************************************** */ |
|
void Make_Ref_Mem (FILE *f1, FILE *f2) |
{ |
|
int Byte, S_Addr, S_Addr_Old; |
int i, j, k; |
|
i = 0; |
S_Addr_Old = 1; |
printf("// Making Verilog Reference Memory File \n"); |
|
while (( i = feof(f1)) == 0) |
{ |
Byte = Get_ROM_Byte(f1, &S_Addr); |
if ( S_Addr != S_Addr_Old ) |
{ |
fprintf(f2, "\n@%4.4X", S_Addr ); |
S_Addr_Old = S_Addr; |
} |
fprintf(f2, " %2.2X", Byte); |
} |
|
printf("Conversion All Done Now\n"); |
return; |
} |
|
/* ************************************************************************** */ |
FILE * open_read_file (char file_name[80]) |
{ |
char c; |
FILE *file_num; |
|
file_num = NULL; |
printf("Input File Name => %s\n", file_name); |
file_num = fopen(file_name, "rb"); |
if (file_num == NULL) |
{ |
printf("\nError in opening read file!!\n"); |
} |
return file_num; |
} |
|
/* ************************************************************************** */ |
FILE * open_write_file (char file_name[80]) |
{ |
FILE *file_num; |
char c, out_file_name[80]; |
int i, j, k; |
|
i = strlen(file_name); |
strcpy(out_file_name, file_name); |
while (out_file_name[i] != '.') |
{ |
out_file_name[i] = 0; |
i--; |
} |
strcat(out_file_name, "v"); |
|
file_num = NULL; |
printf("Output File Name => %s\n", out_file_name); |
file_num = fopen(out_file_name, "w"); |
if (file_num == NULL) |
{ |
printf("\nError in opening write file!!\n"); |
} |
printf("\n"); |
return file_num; |
} |
|
/trunk/sw/tools/srec_2_verilog/README.txt
0,0 → 1,8
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
Sept 1, 2009 |
|
This is a fragment of code I wrote many years ago while waiting on some long |
synthesis and place and route runs to complete. It converts srecord files |
into a format that is ready for the "readmem" Verilog command. I don't |
believe that it calculates and checks srecord parity. It should compile with |
a simple command line entry. |
/trunk/sw/tools/HSW12ASM/README.txt
0,0 → 1,14
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
Sept 1, 2009 |
|
The hsw12asm assembler was used to create the object code srecord files for |
the test cases. This assembler is written in Perl so it should be usable on |
most computer systems. I don't plan on trying a copy as part of this project |
but please see to sites below for the most recent versions to download. |
|
Documentation: |
http://home.arcor.de/hotwolf/hsw12asm.html |
|
Source Code: |
http://sourceforge.net/projects/hsw12asm/ |
|
/trunk/sw/tools/misc/xgate_assembler.pl
0,0 → 1,110
#!/usr/bin/perl -w |
|
|
sub fill_field { |
my($prototype, $data) = $_; |
my($i, $j); |
$j = 0; |
$out_field = ""; |
for ($i = 0, $i <= 15, $i++) { |
if ($_[0][$i] eq "?") { |
$out_field = $_[1][$j] . $out_field; |
$j++; |
} else { |
$out_field = $_[0][$i] . $out_field; |
} |
} |
|
|
sub month_to_number { |
if ($_[0] eq "0") { |
$_[0] = "0"; |
} elsif ($_[0] eq "1") { |
$_[0] = "1"; |
} elsif ($_[0] eq "IMM3") { |
$_[0] = "???"; |
} elsif ($_[0] eq "RS") { |
$_[0] = "???"; |
} elsif ($_[0] eq "RD") { |
$_[0] = "???"; |
} elsif ($_[0] eq "IMM4") { |
$_[0] = "????"; |
} elsif ($_[0] eq "RS1") { |
$_[0] = "???"; |
} elsif ($_[0] eq "RS2") { |
$_[0] = "???"; |
} elsif ($_[0] eq "REL9") { |
$_[0] = "?????????"; |
} elsif ($_[0] eq "REL10") { |
$_[0] = "??????????"; |
} elsif ($_[0] eq "RB") { |
$_[0] = "???"; |
} elsif ($_[0] eq "OFFS5") { |
$_[0] = "?????"; |
} elsif ($_[0] eq "RI") { |
$_[0] = "???"; |
} elsif ($_[0] eq "IMM8") { |
$_[0] = "????????"; |
} else { |
printf "Bad Instruction Parameter: %s\n", $_[0]; |
$_[0] = ""; |
} |
} |
|
|
|
if( @ARGV < 1 ) { |
$progname = `basename $0`; |
chomp($progname); |
print "Syntax: $progname <Infile> <Outfile>\n"; |
die; |
} elsif ( @ARGV < 2 ) { |
print "Using default output file \"temp.v\"\n"; |
$Infile = shift @ARGV; |
$Outfile = 'temp.v'; |
} else { |
$Infile = shift @ARGV; |
$Outfile = shift @ARGV; |
} |
|
open( source_file, "<$Infile" ) || die "Could not open Input file"; |
open( verilog_file, ">$Outfile" ) || die "Could not open Output file"; |
|
$i = 1; |
@op_code_list = (); |
while (<source_file>) { |
chomp; |
#s/\\$//; # remove trailing \ |
#s/}$//; # remove trailing } |
#s/{.*//; # get rid of all the lines starting with { |
#s/\\\w*//g; # get rid of all words starting with \ |
s/;.*$//g; # get rid of everything after ; |
s/ *$//g; # get rid of trailing blanks |
s/^ *//g; # get rid of all leading blanks |
if ($_) { |
if (! / [01] [01] / ) { |
print "\n // Instruction Group -- $_ \n"; |
} else { |
/( [01] )/; |
$inst = index($_, $1); |
$instruction = substr($_, 0, $inst); |
$op_code = substr($_, $inst++); |
# print "Instruction Line = $_\n"; |
@bit_fields = split / /, $op_code; |
shift @bit_fields; # get rid of leading blank element |
$case_var = ""; |
foreach $field (@bit_fields) { |
$case_var = $case_var . &month_to_number($field); |
} |
push @op_code_list, $case_var; |
print "\n // Instruction = $instruction, Op Code = $op_code\n"; |
print " 16'b$case_var :\n"; |
$i++; |
} |
} |
} |
|
|
close( source_file ); |
close( verilog_file ); |
|
trunk/sw/tools/misc/xgate_assembler.pl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sw/tools/misc/srec.pl
===================================================================
--- trunk/sw/tools/misc/srec.pl (nonexistent)
+++ trunk/sw/tools/misc/srec.pl (revision 16)
@@ -0,0 +1,88 @@
+#!/usr/bin/perl -w
+use strict;
+use IO::File;
+
+use Getopt::Long;
+my $outfile="out";
+my $lenlen=2;
+my $dowordswap= 0;
+my $maxgap= 1;
+GetOptions(
+ "o=s" => \$outfile,
+ "l=i" => \$lenlen,
+ "m=s" => sub { $maxgap= eval($_[1]) },
+ "w" => \$dowordswap)
+ or die "Usage: srec [-o=OUTPREFIX] [-l={4|2}] [-w {swap}] [-m=MAXGAP]\n";
+my %data;
+
+# s-records have the following format:
+# "S" + 1 byte type
+# 2 hex digits : length ( of rest of line - incl address and checksum )
+# 4,6,8 hex digits address ( for type 1, 2, 3 )
+# hex data [ 0..64 bytes ]
+# checksum [ 1 byte ] such that unpack('%8C*', pack('H*', $line))==0xff
+# ( or checksum=0xff-sum(otherbytes)
+#
+#
+# type S0 : version : char mname[10], byte ver, byte rev, char description[18]
+# or usually : 00 00 + 'HDR'
+# type S1 : 2 byte address + data
+# type S2 : 3 byte address + data
+# type S3 : 4 byte address + data
+# type S5 : 2 byte count of S1, S2, S3 records transmitted
+# type S7 : 4 byte entrypoint address
+# type S8 : 3 byte entrypoint address
+# type S9 : 2 byte entrypoint address
+
+while (<>) {
+ my $type= hex(substr($_, 1,1));
+ my $length= hex(substr($_,2,$lenlen));
+
+ my $adrlen= $type eq "1" ? 4 : $type eq "2" ? 6 : $type eq "3" ? 8 : 0;
+ next if (!$adrlen);
+ my $address= hex(substr($_,2+$lenlen,$adrlen));
+ my $data= pack("H*", substr($_,2+$lenlen+$adrlen, 2*$length-$adrlen-2));
+ if ($dowordswap) {
+ $data= pack('v*', unpack('n*',$data));
+ }
+
+ $data{$address}= $data;
+}
+
+# |---------|...|
+# |-----|
+#
+my @addrs= sort { $a <=> $b } keys %data;
+my $fh;
+for (0..$#addrs) {
+ my $startcur= $addrs[$_];
+
+ if ($_>0) {
+ my $startlast= $addrs[$_-1];
+ my $endlast= length($data{$startlast})+ $startlast;
+
+ if ($endlast +$maxgap <= $startcur) {
+ printf(" %08lx-%08lx .. gap .. %08lx\n", $startlast, $endlast, $startcur);
+
+ $fh->close();
+ undef $fh;
+ }
+ elsif ($endlast < $startcur ) {
+ $fh->seek($startcur-$endlast, SEEK_CUR);
+ }
+ elsif ($endlast > $startcur) {
+ printf("WARNING: overlap found: %08lx-%08lx ~ %08lx\n", $startlast, $endlast, $startcur);
+ $fh->close();
+ undef $fh;
+ }
+ }
+
+ if (!$fh) {
+ $fh= IO::File->new(sprintf("%s-%08lx.bin", $outfile, $startcur), "w");
+ binmode($fh);
+ }
+ $fh->print($data{$startcur});
+}
+$fh->close();
+#print map { $data{$_} } sort keys %data;
+
Index: trunk/sw/tools/misc/test_assembler.pl
===================================================================
--- trunk/sw/tools/misc/test_assembler.pl (nonexistent)
+++ trunk/sw/tools/misc/test_assembler.pl (revision 16)
@@ -0,0 +1,594 @@
+#!/usr/bin/perl -w
+
+sub test_for_keyword {
+ foreach $keyword (@instruction_keyword_list) {
+ if ($_[0] eq $keyword) {
+ return 1;
+ }
+ }
+ return 0;
+}
+
+sub print_symbol_table {
+ while (($key, $value) = each %symbol_table) {
+ print "Symbol Name $key => $value\n";
+ }
+}
+
+sub do_expression {
+ print "Do Expersion input = $_[0]\n";
+ @expresion = split /([()+-])/, $_[0];
+ $converted = 0;
+ print "Do Expression - Expresion parts are: @expresion\n";
+ $i = 0;
+ foreach (@expresion) {
+ print "Foreach value is: $_\n";
+ s/ *$//g; # get rid of trailing blanks
+ s/^ *//g; # get rid of all leading blanks
+ if (/^\$/) {
+ $temp = &hex_to_num;
+ $expresion[$i] = $temp;
+ } elsif (/^[0-9]/) {
+ $temp = &dec_to_num;
+ $expresion[$i] = $temp;
+ } elsif (/^[a-zA-Z_]/) {
+ $temp = &symbol_to_num;
+ $expresion[$i] = $temp;
+ }
+ print " -- Expression part is: $expresion[$i]\n";
+ $i++;
+ }
+ $converted = @expresion[0];
+ print "Final Do Expression is: $converted, expression = @expresion\n";
+ return $converted;
+}
+
+sub hex_to_num {
+ my ($i, $temp, $converted);
+ s/^\$//;
+ $i = 1;
+ @chars = split //, $_;
+ @chars = reverse @chars;
+ $converted = 0;
+ foreach $c (@chars) {
+ if ($c =~ /[A-F]/) {
+ $temp = ord($c) - ord("A") + 10;
+ } elsif ($c =~ /[a-f]/) {
+ $temp = ord($c) - ord("a") + 10;
+ } elsif ($c =~ /[0-9]/) {
+ $temp = ord($c) - ord("0");
+ } else {
+ print "ERROR - in hex number conversion\n";
+ }
+ $temp = $temp * $i;
+ $converted = $converted + $temp;
+ $i = $i*16;
+ }
+ return $converted;
+}
+
+sub dec_to_num {
+ my ($i, $temp, $converted);
+ s/^\$//;
+ $i = 1;
+ @chars = split //, $_;
+ @chars = reverse @chars;
+ $converted = 0;
+ foreach $c (@chars) {
+ if ($c =~ /[0-9]/) {
+ $temp = ord($c) - ord("0");
+ } else {
+ print "ERROR - in dec number conversion\n";
+ }
+ $temp = $temp * $i;
+ $converted = $converted + $temp;
+ $i = $i*10;
+ }
+ return $converted;
+}
+
+sub symbol_to_num {
+ my $converted;
+ print "Symbol_convert - $_\n";
+ $converted = $symbol_table{$_};
+ if ($converted =~ /XXX/) {
+ print "ERROR - Undefined Symbol Conversion => $_/n";
+ }
+ return $converted;
+}
+
+sub print_memory_image {
+ $j = 0;
+ foreach $i (@memory_image) {
+ print "Address $j => $i\n";
+ $j++;
+ }
+}
+
+sub reg_to_num {
+ my $register = $_;
+ if ($register eq "R0") {
+ $register = "000";
+ } elsif ($register eq "R1") {
+ $register = "001";
+ } elsif ($register eq "R2") {
+ $register = "010";
+ } elsif ($register eq "R3") {
+ $register = "011";
+ } elsif ($register eq "R4") {
+ $register = "100";
+ } elsif ($register eq "R5") {
+ $register = "101";
+ } elsif ($register eq "R6") {
+ $register = "110";
+ } elsif ($register eq "R7") {
+ $register = "111";
+ } else {
+ printf "Bad Register Name: %s\n", $register;
+ $register = "";
+ }
+}
+
+sub translate_RD {
+ $rd_prototype = "00000???00000000";
+ &fill_field($rd_prototype, ®_to_num($_[0]));
+}
+
+sub do_compiler_command {
+ if ($white_split[0] eq "EQU") {
+ shift @white_split;
+ print "\nStarting EQU - Symbol = $current_symbol, @white_split\n";
+ $junk_temp = &do_expression(@white_split);
+ print "Ending EQU - value is $junk_temp\n\n";
+ $symbol_table{$current_symbol} = $junk_temp;
+ } elsif ($white_split[0] eq "ORG") {
+ $program_address = $white_split[1];
+ $symbol_table{$current_symbol} = $program_address;
+ } elsif ($white_split[0] eq "ALIGN") {
+ $program_address = $white_split[1];
+ $symbol_table{$current_symbol} = $program_address;
+ } elsif ($white_split[0] eq "DW") {
+ $symbol_table{$current_symbol} = $program_address;
+ $program_address = $program_address + 1;
+ } elsif ($white_split[0] eq "DB") {
+ $symbol_table{$current_symbol} = $program_address;
+ $program_address++;
+ } elsif ($white_split[0] eq "FCC") {
+ $program_address = $white_split[1];
+ $symbol_table{$current_symbol} = $program_address;
+ }
+}
+
+sub do_instruction {
+ if ($white_split[0] eq "BRK") {
+ $protype_op_code = "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0";
+ $xyzpp = "0000000000000000";
+
+ } elsif ($white_split[0] eq "NOP") {
+ $protype_op_code = "0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0";
+ $xyzpp = "0000000100000000";
+
+ } elsif ($white_split[0] eq "RTS") {
+ $protype_op_code = "0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0";
+ $xyzpp = "0000001000000000";
+
+ } elsif ($white_split[0] eq "SIF") {
+ $protype_op_code = "0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0";
+ $xyzpp = "0000001100000000";
+
+ } elsif ($white_split[0] eq "CSEM") {
+ $protype_op_code = "0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0";
+ $xyzpp = "00000???11110000";
+
+ $protype_op_code = "0 0 0 0 0 RS 1 1 1 1 0 0 0 1";
+ $xyzpp = "00000???11110001";
+
+ } elsif ($white_split[0] eq "SSEM") {
+ $protype_op_code = "0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0";
+ $xyzpp = "00000???11110010";
+
+ $protype_op_code = "0 0 0 0 0 RS 1 1 1 1 0 0 1 1";
+ $xyzpp = "00000???11110011";
+
+
+ } elsif ($white_split[0] eq "SEX") {
+ $protype_op_code = "0 0 0 0 0 RD 1 1 1 1 0 1 0 0";
+ $xyzpp = "00000???11110100";
+
+ } elsif ($white_split[0] eq "PAR") {
+ $protype_op_code = "0 0 0 0 0 RD 1 1 1 1 0 1 0 1";
+ $xyzpp = "00000???11110101";
+
+ } elsif ($white_split[0] eq "JAL") {
+ $protype_op_code = "0 0 0 0 0 RD 1 1 1 1 0 1 1 0";
+ $xyzpp = "00000???11110110";
+
+ } elsif ($white_split[0] eq "SIF") {
+ $protype_op_code = "0 0 0 0 0 RS 1 1 1 1 0 1 1 1";
+ $xyzpp = "00000???11110111";
+
+
+ } elsif ($white_split[0] eq "TFR") {
+ # RD,CCR
+ $protype_op_code = "0 0 0 0 0 RD 1 1 1 1 1 0 0 0";
+ $xyzpp = "00000???11111000";
+
+ } elsif ($white_split[0] eq "TFR") {
+ # CCR,RS
+ $protype_op_code = "0 0 0 0 0 RS 1 1 1 1 1 0 0 1";
+ $xyzpp = "00000???11111001";
+
+ } elsif ($white_split[0] eq "TFR") {
+ # RD,PC
+ $protype_op_code = "0 0 0 0 0 RD 1 1 1 1 1 0 1 0";
+ $xyzpp = "00000???11111010";
+
+
+ } elsif ($white_split[0] eq "BFFO") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 0 0 0";
+ $xyzpp = "00001??????10000";
+
+ } elsif ($white_split[0] eq "ASR") {
+ $_ = $white_space[2];
+ if (/R[0-7]/) {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 0 0 1";
+ $xyzpp = "00001??????10001";
+ } else {
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 0 0 1";
+ $xyzpp = "00001???????1001";
+ }
+ } elsif ($white_split[0] eq "CSL") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 0 1 0";
+ $xyzpp = "00001??????10010";
+
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 0 1 0";
+ $xyzpp = "00001???????1010";
+
+ } elsif ($white_split[0] eq "CSR") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 0 1 1";
+ $xyzpp = "00001??????10011";
+
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 0 1 1";
+ $xyzpp = "00001???????1011";
+
+ } elsif ($white_split[0] eq "LSL") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 1 0 0";
+ $xyzpp = "00001??????10100";
+
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 1 0 0";
+ $xyzpp = "00001???????1100";
+
+ } elsif ($white_split[0] eq "LSR") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 1 0 1";
+ $xyzpp = "00001??????10101";
+
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 1 0 1";
+ $xyzpp = "00001???????1101";
+
+ } elsif ($white_split[0] eq "ROL") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 1 1 0";
+ $xyzpp = "00001??????10110";
+
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 1 1 0";
+ $xyzpp = "00001???????1110";
+
+ } elsif ($white_split[0] eq "ROR") {
+ $protype_op_code = "0 0 0 0 1 RD RS 1 0 1 1 1";
+ $xyzpp = "00001??????10111";
+
+ $protype_op_code = "0 0 0 0 1 RD IMM4 1 1 1 1";
+ $xyzpp = "00001???????1111";
+
+ } elsif ($white_split[0] eq "AND") {
+ $protype_op_code = "0 0 0 1 0 RD RS1 RS2 0 0";
+ $xyzpp = "00010?????????00";
+
+ } elsif ($white_split[0] eq "OR") {
+ $protype_op_code = "0 0 0 1 0 RD RS1 RS2 1 0";
+ $xyzpp = "00010?????????10";
+
+ } elsif ($white_split[0] eq "XNOR") {
+ $protype_op_code = "0 0 0 1 0 RD RS1 RS2 1 1";
+ $xyzpp = "00010?????????11";
+
+ } elsif ($white_split[0] eq "SUB") {
+ $protype_op_code = "0 0 0 1 1 RD RS1 RS2 0 0";
+ $xyzpp = "00011?????????00";
+
+ } elsif ($white_split[0] eq "SBC") {
+ $protype_op_code = "0 0 0 1 1 RD RS1 RS2 0 1";
+ $xyzpp = "00011?????????01";
+
+ } elsif ($white_split[0] eq "ADD") {
+ $protype_op_code = "0 0 0 1 1 RD RS1 RS2 1 0";
+ $xyzpp = "00011?????????10";
+
+ } elsif ($white_split[0] eq "ADC") {
+ $protype_op_code = "0 0 0 1 1 RD RS1 RS2 1 1";
+ $xyzpp = "00011?????????11";
+
+
+ } elsif ($white_split[0] eq "BCC") {
+ $protype_op_code = "0 0 1 0 0 0 0 REL9";
+ $xyzpp = "0010000?????????";
+
+ } elsif ($white_split[0] eq "BCS") {
+ $protype_op_code = "0 0 1 0 0 0 1 REL9";
+ $xyzpp = "0010001?????????";
+
+ } elsif ($white_split[0] eq "BNE") {
+ $protype_op_code = "0 0 1 0 0 1 0 REL9";
+ $xyzpp = "0010010?????????";
+
+ } elsif ($white_split[0] eq "BEQ") {
+ $protype_op_code = "0 0 1 0 0 1 1 REL9";
+ $xyzpp = "0010011?????????";
+
+ } elsif ($white_split[0] eq "BPL") {
+ $protype_op_code = "0 0 1 0 1 0 0 REL9";
+ $xyzpp = "0010100?????????";
+
+ } elsif ($white_split[0] eq "BMI") {
+ $protype_op_code = "0 0 1 0 1 0 1 REL9";
+ $xyzpp = "0010101?????????";
+
+ } elsif ($white_split[0] eq "BVC") {
+ $protype_op_code = "0 0 1 0 1 1 0 REL9";
+ $xyzpp = "0010110?????????";
+
+ } elsif ($white_split[0] eq "BVS") {
+ $protype_op_code = "0 0 1 0 1 1 1 REL9";
+ $xyzpp = "0010111?????????";
+
+ } elsif ($white_split[0] eq "BHI") {
+ $protype_op_code = "0 0 1 1 0 0 0 REL9";
+ $xyzpp = "0011000?????????";
+
+ } elsif ($white_split[0] eq "BLS") {
+ $protype_op_code = "0 0 1 1 0 0 1 REL9";
+ $xyzpp = "0011001?????????";
+
+ } elsif ($white_split[0] eq "BGE") {
+ $protype_op_code = "0 0 1 1 0 1 0 REL9";
+ $xyzpp = "0011010?????????";
+
+ } elsif ($white_split[0] eq "BLT") {
+ $protype_op_code = "0 0 1 1 0 1 1 REL9";
+ $xyzpp = "0011011?????????";
+
+ } elsif ($white_split[0] eq "BGT") {
+ $protype_op_code = "0 0 1 1 1 0 0 REL9";
+ $xyzpp = "0011100?????????";
+
+ } elsif ($white_split[0] eq "BLE") {
+ $protype_op_code = "0 0 1 1 1 0 1 REL9";
+ $xyzpp = "0011101?????????";
+
+ } elsif ($white_split[0] eq "BRA") {
+ $protype_op_code = "0 0 1 1 1 1 REL10";
+ $xyzpp = "001111??????????";
+
+
+ } elsif ($white_split[0] eq "LDB") {
+ $_ = $white_space[3];
+ if (/\#/) {
+ $protype_op_code = "0 1 0 0 0 RD RB #OFFS5";
+ $xyzpp = "01000???????????";
+ }
+ $protype_op_code = "0 1 1 0 0 RD RB RI 0 0";
+ $xyzpp = "01100?????????00";
+
+ $protype_op_code = "0 1 1 0 0 RD RB RI+ 0 1";
+ $xyzpp = "01100?????????01";
+
+ $protype_op_code = "0 1 1 0 0 RD RB -RI 1 0";
+ $xyzpp = "01100?????????10";
+
+ } elsif ($white_split[0] eq "LDW") {
+ $protype_op_code = "0 1 0 0 1 RD RB #OFFS5";
+ $xyzpp = "01001???????????";
+
+ $protype_op_code = "0 1 1 0 1 RD RB RI 0 0";
+ $xyzpp = "01101?????????00";
+
+ $protype_op_code = "0 1 1 0 1 RD RB RI+ 0 1";
+ $xyzpp = "01101?????????01";
+
+ $protype_op_code = "0 1 1 0 1 RD RB -RI 1 0";
+ $xyzpp = "01101?????????10";
+
+ } elsif ($white_split[0] eq "STB") {
+ $protype_op_code = "0 1 0 1 0 RS RB #OFFS5";
+ $xyzpp = "01010???????????";
+
+ $protype_op_code = "0 1 1 1 0 RS RB RI 0 0";
+ $xyzpp = "01110?????????00";
+
+ $protype_op_code = "0 1 1 1 0 RS RB RI+ 0 1";
+ $xyzpp = "01110?????????01";
+
+ $protype_op_code = "0 1 1 1 0 RS RB -RI 1 0";
+ $xyzpp = "01110?????????10";
+
+ } elsif ($white_split[0] eq "STW") {
+ $protype_op_code = "0 1 0 1 1 RS RB #OFFS5";
+ $xyzpp = "01011???????????";
+
+ $protype_op_code = "0 1 1 1 1 RS RB RI 0 0";
+ $xyzpp = "01111?????????00";
+
+ $protype_op_code = "0 1 1 1 1 RS RB RI+ 0 1";
+ $xyzpp = "01111?????????01";
+
+ $protype_op_code = "0 1 1 1 1 RS RB -RI 1 0";
+ $xyzpp = "01111?????????10";
+
+
+ } elsif ($white_split[0] eq "BFEXT") {
+ $protype_op_code = "0 1 1 0 0 RD RS1 RS2 1 1";
+ $xyzpp = "01100?????????11";
+
+ } elsif ($white_split[0] eq "BFINS") {
+ $protype_op_code = "0 1 1 0 1 RD RS1 RS2 1 1";
+ $xyzpp = "01101?????????11";
+
+ } elsif ($white_split[0] eq "BFINSI") {
+ $protype_op_code = "0 1 1 1 0 RD RS1 RS2 1 1";
+ $xyzpp = "01110?????????11";
+
+ } elsif ($white_split[0] eq "BFINSX") {
+ $protype_op_code = "0 1 1 1 1 RD RS1 RS2 1 1";
+ $xyzpp = "01111?????????11";
+
+
+ } elsif ($white_split[0] eq "ANDL") {
+ $protype_op_code = "1 0 0 0 0 RD IMM8";
+ $xyzpp = "10000???????????";
+
+ } elsif ($white_split[0] eq "ANDH") {
+ $protype_op_code = "1 0 0 0 1 RD IMM8";
+ $xyzpp = "10001???????????";
+
+ } elsif ($white_split[0] eq "BITL") {
+ $protype_op_code = "1 0 0 1 0 RD IMM8";
+ $xyzpp = "10010???????????";
+
+ } elsif ($white_split[0] eq "BITH") {
+ $protype_op_code = "1 0 0 1 1 RD IMM8";
+ $xyzpp = "10011???????????";
+
+ } elsif ($white_split[0] eq "ORL") {
+ $protype_op_code = "1 0 1 0 0 RD IMM8";
+ $xyzpp = "10100???????????";
+
+ } elsif ($white_split[0] eq "ORH") {
+ $protype_op_code = "1 0 1 0 1 RD IMM8";
+ $xyzpp = "10101???????????";
+
+ } elsif ($white_split[0] eq "XNORL") {
+ $protype_op_code = "1 0 1 1 0 RD IMM8";
+ $xyzpp = "10110???????????";
+
+ } elsif ($white_split[0] eq "XNORH") {
+ $protype_op_code = "1 0 1 1 1 RD IMM8";
+ $xyzpp = "10111???????????";
+
+
+ } elsif ($white_split[0] eq "SUBL") {
+ $protype_op_code = "1 1 0 0 0 RD IMM8";
+ $xyzpp = "11000???????????";
+
+ } elsif ($white_split[0] eq "SUBH") {
+ $protype_op_code = "1 1 0 0 1 RD IMM8";
+ $xyzpp = "11001???????????";
+
+ } elsif ($white_split[0] eq "CMPL") {
+ $protype_op_code = "1 1 0 1 0 RS IMM8";
+ $xyzpp = "11010???????????";
+
+ } elsif ($white_split[0] eq "CPCH") {
+ $protype_op_code = "1 1 0 1 1 RS IMM8";
+ $xyzpp = "11011???????????";
+
+ } elsif ($white_split[0] eq "ADDL") {
+ $protype_op_code = "1 1 1 0 0 RD IMM8";
+ $xyzpp = "11100???????????";
+
+ } elsif ($white_split[0] eq "ADDH") {
+ $protype_op_code = "1 1 1 0 1 RD IMM8";
+ $xyzpp = "11101???????????";
+
+ } elsif ($white_split[0] eq "LDL") {
+ $protype_op_code = "1 1 1 1 0 RD IMM8";
+ $xyzpp = "11110???????????";
+
+ } elsif ($white_split[0] eq "LDH") {
+ $protype_op_code = "1 1 1 1 1 RD IMM8";
+ $xyzpp = "11111???????????";
+ }
+
+ $memory_image[$program_address] = $xyzpp;
+ $program_address = $program_address + 1;
+}
+
+################################################################################
+# Main
+################################################################################
+
+if( @ARGV < 1 ) {
+ $progname = `basename $0`;
+ chomp($progname);
+ print "Syntax: $progname \n";
+ die;
+} elsif ( @ARGV < 2 ) {
+ print "Using default output file \"temp.v\"\n";
+ $Infile = shift @ARGV;
+ $Outfile = 'temp.v';
+} else {
+ $Infile = shift @ARGV;
+ $Outfile = shift @ARGV;
+}
+
+open( source_file, "<$Infile" ) || die "Could not open Input file";
+open( verilog_file, ">$Outfile" ) || die "Could not open Output file";
+
+$source_line_number = 1;
+$program_address = 0;
+$cpu_type = "";
+@memory_image = "";
+@instruction_keyword_list = qw/ CPU ALIGN ORG EQU DW DB FCC /;
+push @instruction_keyword_list, qw/ BRK NOP RTS SIF CSEM SSEM SEX PAR /;
+push @instruction_keyword_list, qw/ JAL SIF TFR BFFO ASR CSL CSR LSL LSR /;
+push @instruction_keyword_list, qw/ ROL ROR AND OR XNOR SUB SBC ADD BCC BCS /;
+push @instruction_keyword_list, qw/ BNE BEQ BPL BMI BVC BVS BHI BLS BGE BLT /;
+push @instruction_keyword_list, qw/ BGT BLE BRA LDB LDW STB STW BFEXT BFINS /;
+push @instruction_keyword_list, qw/ BFINSI BFINSX ANDL ANDH BITL BITH ORL /;
+push @instruction_keyword_list, qw/ ORH XNORL XNORH SUBL SUBH CMPL CPCH /;
+push @instruction_keyword_list, qw/ ADDL ADDH LDL LDH /;
+
+while () {
+ chomp;
+ s/;.*$//g; # get rid of everything after ;
+ s/ *$//g; # get rid of trailing blanks
+ s/^ *//g; # get rid of all leading blanks
+ if ($_) {
+ print "Instruction Line = $_ number = $source_line_number\n";
+ #@white_split = split; # Breakout fields on white space
+ @white_split = split /\s+|,/; # Breakout fields on white space or ,
+ $i = 0;
+ foreach (@white_split) {
+ s/\(R/R/; # Remove leading "(" if it is part of Register name
+ s/\)\)/\)/; # Take of one of ")" of double "))"
+ if (/^\$/) { # Take care of the simple case of a hex number
+ $white_split[$i] = &hex_to_num($white_split[$i]);
+ }
+ if (/^[0-9]/) { # Take care of the simple case of a dec number
+ $white_split[$i] = &dec_to_num($white_split[$i]);
+ }
+ $i++;
+ }
+ if (! &test_for_keyword($white_split[0])) { # Line starts with a symbol name
+ $current_symbol = $white_split[0];
+ if ($symbol_table{$current_symbol}) {
+ print "Error Reused Symbol - $current_symbol - Source Line Number $source_line_number\n";
+ } else {
+ $symbol_table{$current_symbol} = "XXX"; # initilize to junk
+ }
+ shift @white_split;
+ }
+ if (! @white_split) { # The only thing in the line was a symbol
+ $symbol_table{$current_symbol} = $program_address;
+ } else {
+ &do_compiler_command(@white_split);
+ &do_instruction;
+ }
+ }
+ $source_line_number++;
+}
+
+&print_symbol_table;
+&print_memory_image;
+
+close( source_file );
+close( verilog_file );
+
trunk/sw/tools/misc/test_assembler.pl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sw/tools/misc/make_decode.pl
===================================================================
--- trunk/sw/tools/misc/make_decode.pl (nonexistent)
+++ trunk/sw/tools/misc/make_decode.pl (revision 16)
@@ -0,0 +1,147 @@
+#!/usr/bin/perl -w
+
+sub month_to_number {
+ if ($_[0] eq "0") {
+ $_[0] = "0";
+ } elsif ($_[0] eq "1") {
+ $_[0] = "1";
+ } elsif ($_[0] eq "IMM3") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "RS") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "RD") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "IMM4") {
+ $_[0] = "????";
+ } elsif ($_[0] eq "RS1") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "RS2") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "REL9") {
+ $_[0] = "?????????";
+ } elsif ($_[0] eq "REL10") {
+ $_[0] = "??????????";
+ } elsif ($_[0] eq "RB") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "OFFS5") {
+ $_[0] = "?????";
+ } elsif ($_[0] eq "RI") {
+ $_[0] = "???";
+ } elsif ($_[0] eq "IMM8") {
+ $_[0] = "????????";
+ } else {
+ printf "Bad Instruction Parameter: %s\n", $_[0];
+ $_[0] = "";
+ }
+}
+
+sub set_default_values {
+ print " always \@*\n";
+ print " begin\n";
+ print " enable_rd = 0;\n";
+ print " enable_imm3 = 0;\n";
+ print " enable_rs = 0;\n";
+ print " enable_imm4 = 0;\n";
+ print " enable_rs1 = 0;\n";
+ print " enable_rs2 = 0;\n";
+ print " enable_rel9 = 0;\n";
+ print " enable_rel10 = 0;\n";
+ print " enable_rb = 0;\n";
+ print " enable_offs5 = 0;\n";
+ print " enable_ri = 0;\n";
+ print " enable_imm8 = 0;\n";
+ print " ena_rd_low_byte = 0;\n";
+ print " ena_rd_high_byte = 0;\n";
+ print " ena_bra_ = 0;\n";
+ print " ena_alu_ = 0;\n";
+ print "\n";
+ print " case (op_code)\n";
+}
+
+
+if( @ARGV < 1 ) {
+ $progname = `basename $0`;
+ chomp($progname);
+ print "Syntax: $progname \n";
+ die;
+} elsif ( @ARGV < 2 ) {
+ print "Using default output file \"temp.v\"\n";
+ $Infile = shift @ARGV;
+ $Outfile = 'temp.v';
+} else {
+ $Infile = shift @ARGV;
+ $Outfile = shift @ARGV;
+}
+
+open( source_file, "<$Infile" ) || die "Could not open Input file";
+open( verilog_file, ">$Outfile" ) || die "Could not open Output file";
+
+$i = 1;
+@op_code_list = ();
+set_default_values;
+while () {
+ chomp;
+ s/\\$//; # remove trailing \
+ s/}$//; # remove trailing }
+ s/{.*//; # get rid of all the lines starting with {
+ s/\\\w*//g; # get rid of all words starting with \
+ s/^ *//g; # get rid of all leading blanks
+ s/'96RI/-RI/; # swap oddball minus sign format
+ if ($_) {
+ if (! / [01] [01] / ) {
+ print "\n // Instruction Group -- $_ \n";
+ } else {
+ /( [01] )/;
+ $inst = index($_, $1);
+ $instruction = substr($_, 0, $inst);
+ $op_code = substr($_, $inst++);
+ # print "Instruction Line = $_\n";
+ @bit_fields = split / /, $op_code;
+ shift @bit_fields; # get rid of leading blank element
+ $case_var = "";
+ foreach $field (@bit_fields) {
+ $case_var = $case_var . &month_to_number($field);
+ }
+ push @op_code_list, $case_var;
+ print "\n // Instruction = $instruction, Op Code = $op_code\n";
+ print " 16'b$case_var :\n";
+ print " begin\n";
+ print " ena_bra_ = 1;\n";
+ print " ena_alu_ = 1;\n";
+ if (index($instruction, "RD") != -1) {
+ print " ena_rd_low_byte = 1;\n";
+ print " ena_rd_high_byte = 1;\n";
+ }
+ if (index($instruction, "IMM3") != -1) {print " enable_imm3 = 1;\n"}
+ if (index($instruction, "RS") != -1) {print " enable_rs = 1;\n"}
+ if (index($instruction, "IMM4") != -1) {print " enable_imm4 = 1;\n"}
+ if (index($instruction, "RS1") != -1) {print " enable_rs1 = 1;\n"}
+ if (index($instruction, "RS2") != -1) {print " enable_rs2 = 1;\n"}
+ if (index($instruction, "REL9") != -1) {print " enable_rel9 = 1;\n"}
+ if (index($instruction, "REL10") != -1) {print " enable_rel10 = 1;\n"}
+ if (index($instruction, "RB") != -1) {print " enable_rb = 1;\n"}
+ if (index($instruction, "OFFS5") != -1) {print " enable_offs5 = 1;\n"}
+ if (index($instruction, "RI") != -1) {print " enable_ri = 1;\n"}
+ if (index($instruction, "IMM8") != -1) {print " enable_imm8 = 1;\n"}
+ print " end\n";
+ $i++;
+ }
+ }
+}
+
+print " default :\n";
+print " begin\n";
+print " end\n";
+print " endcase\n";
+
+print " end\n";
+
+
+close( source_file );
+close( verilog_file );
+
+sort @op_code_list;
+foreach $item (@op_code_list) {
+ print "$item\n"
+}
+
trunk/sw/tools/misc/make_decode.pl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sw/tools/misc/README.txt
===================================================================
--- trunk/sw/tools/misc/README.txt (nonexistent)
+++ trunk/sw/tools/misc/README.txt (revision 16)
@@ -0,0 +1,10 @@
+// 45678901234567890123456789012345678901234567890123456789012345678901234567890
+Sept 1, 2009
+
+I started writing my own Perl assembler and decided that I was going to be
+spending more time writing the assembler than writing the RTL. Google to the
+rescue and I found hsw12asm which fit my needs perefectly.
+
+Not sure what the state of the code is anymore.
+
+make_decode.pl - Perl script to read instructions.rtf and generate the Verilog case statement for the xgate instruction decoder.
\ No newline at end of file
Index: trunk/sw/tools/misc/instructions.rtf
===================================================================
--- trunk/sw/tools/misc/instructions.rtf (nonexistent)
+++ trunk/sw/tools/misc/instructions.rtf (revision 16)
@@ -0,0 +1,156 @@
+{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf460
+{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
+{\colortbl;\red255\green255\blue255;}
+\margl1440\margr1440\vieww19660\viewh14040\viewkind0
+\deftab720
+\pard\pardeftab720\ql\qnatural
+
+\f0\b\fs24 \cf0 Return to Scheduler and Others\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 BRK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\
+NOP 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0\
+RTS 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0\
+SIF 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Semaphore Instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 CSEM IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0\
+CSEM RS 0 0 0 0 0 RS 1 1 1 1 0 0 0 1\
+SSEM IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0\
+SSEM RS 0 0 0 0 0 RS 1 1 1 1 0 0 1 1\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Single Register Instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 SEX RD 0 0 0 0 0 RD 1 1 1 1 0 1 0 0\
+PAR RD 0 0 0 0 0 RD 1 1 1 1 0 1 0 1\
+JAL RD 0 0 0 0 0 RD 1 1 1 1 0 1 1 0\
+SIF RS 0 0 0 0 0 RS 1 1 1 1 0 1 1 1\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Special Move instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 TFR RD,CCR 0 0 0 0 0 RD 1 1 1 1 1 0 0 0\
+TFR CCR,RS 0 0 0 0 0 RS 1 1 1 1 1 0 0 1\
+TFR RD,PC 0 0 0 0 0 RD 1 1 1 1 1 0 1 0\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Shift instructions Dyadic\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 BFFO RD, RS 0 0 0 0 1 RD RS 1 0 0 0 0\
+ASR RD, RS 0 0 0 0 1 RD RS 1 0 0 0 1\
+CSL RD, RS 0 0 0 0 1 RD RS 1 0 0 1 0\
+CSR RD, RS 0 0 0 0 1 RD RS 1 0 0 1 1\
+LSL RD, RS 0 0 0 0 1 RD RS 1 0 1 0 0\
+LSR RD, RS 0 0 0 0 1 RD RS 1 0 1 0 1\
+ROL RD, RS 0 0 0 0 1 RD RS 1 0 1 1 0\
+ROR RD, RS 0 0 0 0 1 RD RS 1 0 1 1 1\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Shift instructions immediate\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 ASR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 0 1\
+CSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 0\
+CSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 1\
+LSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 0\
+LSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 1\
+ROL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 0\
+ROR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 1\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Logical Triadic\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 AND RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 0 0\
+OR RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 1 0\
+XNOR RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 1 1\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Arithmetic Triadic
+\b0 For compare use SUB R0,Rs1,Rs2\
+SUB RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 0\
+SBC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 1\
+ADD RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 0\
+ADC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 1\
+
+\b Branches\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 BCC REL9 0 0 1 0 0 0 0 REL9\
+BCS REL9 0 0 1 0 0 0 1 REL9\
+BNE REL9 0 0 1 0 0 1 0 REL9\
+BEQ REL9 0 0 1 0 0 1 1 REL9\
+BPL REL9 0 0 1 0 1 0 0 REL9\
+BMI REL9 0 0 1 0 1 0 1 REL9\
+BVC REL9 0 0 1 0 1 1 0 REL9\
+BVS REL9 0 0 1 0 1 1 1 REL9\
+BHI REL9 0 0 1 1 0 0 0 REL9\
+BLS REL9 0 0 1 1 0 0 1 REL9\
+BGE REL9 0 0 1 1 0 1 0 REL9\
+BLT REL9 0 0 1 1 0 1 1 REL9\
+BGT REL9 0 0 1 1 1 0 0 REL9\
+BLE REL9 0 0 1 1 1 0 1 REL9\
+BRA REL10 0 0 1 1 1 1 REL10\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Load and Store Instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 LDB RD, (RB, #OFFS5) 0 1 0 0 0 RD RB OFFS5\
+LDW RD, (RB, #OFFS5) 0 1 0 0 1 RD RB OFFS5\
+STB RS, (RB, #OFFS5) 0 1 0 1 0 RS RB OFFS5\
+STW RS, (RB, #OFFS5) 0 1 0 1 1 RS RB OFFS5\
+LDB RD, (RB, RI) 0 1 1 0 0 RD RB RI 0 0\
+LDW RD, (RB, RI) 0 1 1 0 1 RD RB RI 0 0\
+STB RS, (RB, RI) 0 1 1 1 0 RS RB RI 0 0\
+STW RS, (RB, RI) 0 1 1 1 1 RS RB RI 0 0\
+LDB RD, (RB, RI+) 0 1 1 0 0 RD RB RI 0 1\
+LDW RD, (RB, RI+) 0 1 1 0 1 RD RB RI 0 1\
+STB RS, (RB, RI+) 0 1 1 1 0 RS RB RI 0 1\
+STW RS, (RB, RI+) 0 1 1 1 1 RS RB RI 0 1\
+LDB RD, (RB, \'96RI) 0 1 1 0 0 RD RB RI 1 0\
+LDW RD, (RB, \'96RI) 0 1 1 0 1 RD RB RI 1 0\
+STB RS, (RB, \'96RI) 0 1 1 1 0 RS RB RI 1 0\
+STW RS, (RB, \'96RI) 0 1 1 1 1 RS RB RI 1 0\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Bit Field Instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 BFEXT RD, RS1, RS2 0 1 1 0 0 RD RS1 RS2 1 1\
+BFINS RD, RS1, RS2 0 1 1 0 1 RD RS1 RS2 1 1\
+BFINSI RD, RS1, RS2 0 1 1 1 0 RD RS1 RS2 1 1\
+BFINSX RD, RS1, RS2 0 1 1 1 1 RD RS1 RS2 1 1\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Logic Immediate Instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 ANDL RD, #IMM8 1 0 0 0 0 RD IMM8\
+ANDH RD, #IMM8 1 0 0 0 1 RD IMM8\
+BITL RD, #IMM8 1 0 0 1 0 RD IMM8\
+BITH RD, #IMM8 1 0 0 1 1 RD IMM8\
+ORL RD, #IMM8 1 0 1 0 0 RD IMM8\
+ORH RD, #IMM8 1 0 1 0 1 RD IMM8\
+XNORL RD, #IMM8 1 0 1 1 0 RD IMM8\
+XNORH RD, #IMM8 1 0 1 1 1 RD IMM8\
+\pard\pardeftab720\ql\qnatural
+
+\b \cf0 Arithmetic Immediate Instructions\
+\pard\pardeftab720\ql\qnatural
+
+\b0 \cf0 SUBL RD, #IMM8 1 1 0 0 0 RD IMM8\
+SUBH RD, #IMM8 1 1 0 0 1 RD IMM8\
+CMPL RS, #IMM8 1 1 0 1 0 RS IMM8\
+CPCH RS, #IMM8 1 1 0 1 1 RS IMM8\
+ADDL RD, #IMM8 1 1 1 0 0 RD IMM8\
+ADDH RD, #IMM8 1 1 1 0 1 RD IMM8\
+LDL RD, #IMM8 1 1 1 1 0 RD IMM8\
+LDH RD, #IMM8 1 1 1 1 1 RD IMM8}
\ No newline at end of file
Index: trunk/sw/xgate_test_code/debug_test/debug_test.s
===================================================================
--- trunk/sw/xgate_test_code/debug_test/debug_test.s (nonexistent)
+++ trunk/sw/xgate_test_code/debug_test/debug_test.s (revision 16)
@@ -0,0 +1,334 @@
+; 345678901234567890123456789012345678901234567890123456789012345678901234567890
+; Instruction set test for xgate RISC processor core
+; Bob Hayes - Sept 23 2009
+; Version 0.1 Basic tests of Debug Mode
+
+
+ CPU XGATE
+
+ ORG $fe00
+ DS.W 2 ; reserve two words at channel 0
+ ; channel 1
+ DC.W _START ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 2
+ DC.W _START2 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 3
+ DC.W _START3 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 4
+ DC.W _START4 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 5
+ DC.W _START5 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 6
+ DC.W _START6 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 7
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 8
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 9
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 10
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+
+ ORG $2000 ; with comment
+
+V_PTR EQU 123
+
+
+ DC.W BACK_
+ DS.W 8
+ DC.B $56
+ DS.B 11
+
+ ALIGN 1
+
+;-------------------------------------------------------------------------------
+; Place where undefined interrupts go
+;-------------------------------------------------------------------------------
+_ERROR
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$ff
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Debug Mode and Single Step instructions
+;
+; Note: The testbench checks the PC values so adding or removing instructions
+; from this test will also require a change to the testbench
+; expected values.
+;-------------------------------------------------------------------------------
+_START
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$01
+ STB R3,(R2,#0)
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+
+ ; Test
+ LDL R4,#$c3 ;
+ STW R4,(R0,#$08) ;
+ LDL R3,#$01 ; R3 = $01
+
+ BRK ; Enter Debug mode and start doing Single Step Commands
+ ; from the testbench. Verify PC and R3 values.
+
+ ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)
+ NOP
+ BRA _BRA_OK1 ; Do Foward Branch Single Step
+ ADDL R3,#$40 ; For error detection
+ NOP
+ ADDL R3,#$60 ; For error detection
+_BRA_OK2
+ STW R3,(R0,#$0c) ;
+ ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $04)
+
+ ; Testbench Clears Debug mode
+
+ CMP R4,R7 ; Check Load and Store commands received correct data
+ BNE _FAIL
+ LDW R5,(R0,#$0c) ;
+ ADDL R5,#$01 ; R5 + $01 => R5 (R5 = $04) Catch up to latest R3 value
+ CMP R3,R5 ;
+ BNE _FAIL
+
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$02
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_BRA_OK1
+ ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $03)
+ LDW R7,(R0,#$08) ;
+ BRA _BRA_OK2 ; Do Backward Branch
+
+_FAIL
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$01
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Debug Command
+;-------------------------------------------------------------------------------
+_START2
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$03
+ STB R3,(R2,#0)
+ LDL R3,#$02 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+
+ ; Test
+ LDL R3,#$01 ; R3 = $01
+ LDL R4,#$01 ; R4 = $01
+ LDL R7,#$03 ; R7 = $03
+
+_T2_LOOP
+ ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)
+ NOP
+ BRA _T2_LOOP ; Create an infinate loop. The testbench will
+ ; take control using the Debug bit and change
+ ; the PC to exit the loop.
+
+ NOP
+ NOP
+ ADDL R4,#$60 ; For error detection
+ ADDL R4,#$01 ; Test bench will set the PC to here
+ ADDL R4,#$01 ;
+
+ CMP R4,R7 ; Check Load and Store commands received correct data
+ BNE _FAIL2
+
+_END_2 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$04
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+_FAIL2
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$02
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; Test Debug and Change Channel ID Command
+;-------------------------------------------------------------------------------
+_START3
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$05
+ STB R3,(R2,#0)
+ LDL R3,#$03 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+
+ ; Test
+ LDL R3,#$01 ; R3 = $01
+ LDL R4,#$01 ; R4 = $01
+ LDL R7,#$03 ; R7 = $03
+
+ BRK ; Enter Debug mode
+
+ ; The testbench will use writes to the XGCHID reg to move to another
+ ; channel to complete the test.
+
+_FAIL3
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$03
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; Target for debug mode change CHID Command
+;-------------------------------------------------------------------------------
+_START4
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$06
+ STB R3,(R2,#0)
+
+
+ ; Test
+ BRK
+
+_END_4 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$07
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+_FAIL4
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$04
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; False Target for debug mode change CHID Command
+; Verify that when the CHID command is issued that a higher poririty interrup
+; dosn't slip in.
+;-------------------------------------------------------------------------------
+_START5
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$08
+ STB R3,(R2,#0)
+ LDL R3,#$05 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+
+ ; Test
+ BRK
+
+_END_5 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$09
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+_FAIL5
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$05
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; Test Debug and Change Channel ID Command
+;-------------------------------------------------------------------------------
+_START6
+ BRK ; Enter Debug mode
+ BRA _GO6
+ BRA _FAIL6
+_GO6
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0a
+ STB R3,(R2,#0)
+ LDL R3,#$06 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+
+ ; Test
+
+_END_6 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0b
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+_FAIL6
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$06
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+
+
+;empty line
+
+BACK_
+
+
+ SIF R7
+ BRK
+
+ ORG $8000 ; Special Testbench Addresses
+_BENCH DS.W 8
+
+
+
+
trunk/sw/xgate_test_code/debug_test/debug_test.s
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sw/xgate_test_code/debug_test/make_core.scr
===================================================================
--- trunk/sw/xgate_test_code/debug_test/make_core.scr (nonexistent)
+++ trunk/sw/xgate_test_code/debug_test/make_core.scr (revision 16)
@@ -0,0 +1,3 @@
+../../tools/HSW12ASM/hsw12asm.pl debug_test.s
+../../tools/s_2_verilog debug_test_pag.s28
+mv debug_test_pag.v ../../../bench/verilog/debug_test.v
trunk/sw/xgate_test_code/debug_test/make_core.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sw/xgate_test_code/inst_test/make_core.scr
===================================================================
--- trunk/sw/xgate_test_code/inst_test/make_core.scr (nonexistent)
+++ trunk/sw/xgate_test_code/inst_test/make_core.scr (revision 16)
@@ -0,0 +1,3 @@
+../../tools/HSW12ASM/hsw12asm.pl inst_test.s
+../../tools/s_2_verilog inst_test_pag.s28
+mv inst_test_pag.v ../../../bench/verilog/inst_test.v
trunk/sw/xgate_test_code/inst_test/make_core.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sw/xgate_test_code/inst_test/inst_test.s
===================================================================
--- trunk/sw/xgate_test_code/inst_test/inst_test.s (nonexistent)
+++ trunk/sw/xgate_test_code/inst_test/inst_test.s (revision 16)
@@ -0,0 +1,1715 @@
+; 345678901234567890123456789012345678901234567890123456789012345678901234567890
+; Instruction set test for xgate RISC processor core
+; Bob Hayes - Sept 1 2009
+; Version 0.1 Basic test of all instruction done. Need to improve Condition
+; Code function testing.
+
+
+ CPU XGATE
+
+ ORG $fe00
+ DS.W 2 ; reserve two words at channel 0
+ ; channel 1
+ DC.W _START ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 2
+ DC.W _START2 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 3
+ DC.W _START3 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 4
+ DC.W _START4 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 5
+ DC.W _START5 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 6
+ DC.W _START6 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 7
+ DC.W _START7 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 8
+ DC.W _START8 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 9
+ DC.W _START9 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 10
+ DC.W _START10 ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 11
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 12
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 13
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 14
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 15
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 16
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 17
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 18
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 19
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 20
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 21
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 22
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 23
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 24
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 25
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 26
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 27
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 28
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 29
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 30
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 31
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 32
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 33
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 34
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 35
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 36
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 37
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 38
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 39
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 40
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 41
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 42
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 43
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 44
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 45
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 46
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 47
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 48
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 49
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+ ; channel 50
+ DC.W _ERROR ; point to start address
+ DC.W V_PTR ; point to initial variables
+
+ ORG $2000 ; with comment
+
+V_PTR EQU 123
+
+ DC.W BACK_
+ DS.W 8
+ DC.B $56
+ DS.B 11
+
+ ALIGN 1
+
+;-------------------------------------------------------------------------------
+; Place where undefined interrupts go
+;-------------------------------------------------------------------------------
+_ERROR
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$ff
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Shift instructions
+;-------------------------------------------------------------------------------
+_START
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$01
+ STB R3,(R2,#0)
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+
+ ; Test Bit Field Find First One
+ LDL R5,#$01 ; R5=$0001
+ LDH R5,#$4f ; R5=$4f01
+ BFFO R4,R5
+ BVS _FAIL ; Negative Flag should be clear
+ LDL R6,#$0e ; First one should have been in bit position 14
+ SUB R0,R6,R4
+ BNE _FAIL
+ BFFO R4,R0 ; Zero Value should set Carry Bit
+ BCC _FAIL
+ LDH R5,#$00 ; R5=$0001
+ BFFO R4,R5
+ BCS _FAIL ; Carry should be clear
+ BVS _FAIL ; Overflow Flag should be clear
+ SUB R0,R0,R4 ; R4 Should be zero
+ BNE _FAIL
+
+ ; Test ASR instruction
+ LDL R5,#$04 ; R5=$0008
+ LDH R5,#$81 ; R5=$8108
+ LDL R3,#$03
+ ASR R5,R3 ; R5=$f000, Carry flag set
+ BCC _FAIL
+ BVS _FAIL ; Negative Flag should be clear
+ LDL R4,#$20 ; R4=$0020
+ LDH R4,#$f0 ; R4=$f020
+ SUB R0,R5,R4 ; Compare R5 to R4
+ BNE _FAIL
+
+ ; Test CSL insrtruction
+ LDL R5,#$10 ; R5=$0010
+ LDH R5,#$88 ; R5=$8810
+ LDL R3,#$05
+ CSL R5,R3 ; R5=$081f, Carry flag set
+ BCC _FAIL
+ LDL R4,#$00 ; R4=$0000
+ LDH R4,#$02 ; R4=$0200
+ SUB R0,R5,R4 ; Compare R5 to R4
+ BNE _FAIL
+
+ ;Test CSR instruction
+ LDL R5,#$88 ; R5=$0088
+ LDH R5,#$10 ; R5=$1088
+ LDL R3,#$04
+ CSR R5,R3 ; R5=$0108, Carry flag set
+ BCC _FAIL
+ LDL R4,#$08 ; R4=$0008
+ LDH R4,#$01 ; R4=$0108
+ SUB R0,R5,R4 ; Compare R5 to R4
+ BNE _FAIL
+
+ ;Test LSL instruction
+ LDL R2,#$ff ; R2=$00ff
+ LDH R2,#$07 ; R2=$07ff
+ LDL R1,#$06
+ LSL R2,R1 ; R2=$ffc0, Carry flag set
+ BCC _FAIL
+ LDL R4,#$c0 ; R4=$0008
+ LDH R4,#$ff ; R4=$0108
+ SUB R0,R2,R4 ; Compare R2 to R4
+ BNE _FAIL
+
+ ;Test LSR instruction
+ LDL R7,#$02 ; R7=$0002
+ LDH R7,#$c3 ; R7=$c302
+ LDL R6,#$02
+ LSR R7,R6 ; R7=$30c0, Carry flag set
+ BCC _FAIL
+ LDL R4,#$c0 ; R4=$00c0
+ LDH R4,#$30 ; R4=$30c0
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL
+
+ ;Test ROL instruction
+ LDL R7,#$62 ; R7=$0062
+ LDH R7,#$c3 ; R7=$c362
+ LDL R6,#$04
+ ROL R7,R6 ; R7=$362c
+ BVS _FAIL ; Overflow Flag should be clear
+ LDL R4,#$2c ; R4=$002c
+ LDH R4,#$36 ; R4=$362c
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL
+
+ ;Test ROR instruction
+ LDL R7,#$62 ; R7=$0062
+ LDH R7,#$c3 ; R7=$c362
+ LDL R6,#$08
+ ROL R7,R6 ; R7=$62c3
+ BVS _FAIL ; Overflow Flag should be clear
+ LDL R4,#$c3 ; R4=$00c3
+ LDH R4,#$62 ; R4=$62c3
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL
+
+ ; Test ASR instruction
+ LDL R5,#$00 ; R5=$0000
+ LDH R5,#$80 ; R5=$8000
+ ASR R5,#0 ; R5=$ffff, Carry flag set
+ BCC _FAIL
+ BVS _FAIL ; Overflow Flag should be clear
+ LDL R4,#$ff ; R4=$00ff
+ LDH R4,#$ff ; R4=$ffff
+ SUB R0,R5,R4 ; Compare R5 to R4
+ BNE _FAIL
+
+ ; Test CSL insrtruction
+ LDL R5,#$01 ; R5=$0001
+ LDH R5,#$0f ; R5=$0f01
+ CSL R5,#0 ; R5=$0000, Carry flag set
+ BCC _FAIL
+ LDL R4,#$00 ; R4=$0000
+ LDH R4,#$00 ; R4=$0000
+ SUB R0,R5,R4 ; Compare R5 to R4
+ BNE _FAIL
+
+ ;Test CSR instruction
+ LDL R5,#$ff ; R5=$00ff
+ LDH R5,#$80 ; R5=$80ff
+ CSR R5,#15 ; R5=$0001, Carry flag clear
+ BCS _FAIL
+ LDL R4,#$01 ; R4=$0001
+ LDH R4,#$00 ; R4=$0001
+ SUB R0,R5,R4 ; Compare R5 to R4
+ BNE _FAIL
+
+ ;Test LSL instruction
+ LDL R2,#$1a ; R2=$001a
+ LDH R2,#$ff ; R2=$ff1a
+ LSL R2,#12 ; R2=$a000, Carry flag set
+ BCC _FAIL
+ LDL R4,#$00 ; R4=$0000
+ LDH R4,#$a0 ; R4=$a000
+ SUB R0,R2,R4 ; Compare R2 to R4
+ BNE _FAIL
+
+ ;Test LSR instruction
+ LDL R7,#$8f ; R7=$008f
+ LDH R7,#$b2 ; R7=$b18f
+ LSR R7,#8 ; R7=$00b0, Carry flag set
+ BCC _FAIL
+ LDL R4,#$b2 ; R4=$00b0
+ LDH R4,#$00 ; R4=$00b0
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL
+
+ ;Test ROL instruction
+ LDL R7,#$62 ; R7=$0062
+ LDH R7,#$c3 ; R7=$c362
+ ROL R7,#8 ; R7=$62c3
+ BVS _FAIL ; Overflow Flag should be clear
+ LDL R4,#$c3 ; R4=$00c3
+ LDH R4,#$62 ; R4=$62c3
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL
+
+ ;Test ROR instruction
+ LDL R7,#$62 ; R7=$0062
+ LDH R7,#$c3 ; R7=$c362
+ ROL R7,#12 ; R7=$2c36
+ BVS _FAIL ; Overflow Flag should be clear
+ LDL R4,#$36 ; R4=$0036
+ LDH R4,#$2c ; R4=$2c36
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL
+
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$02
+ STB R3,(R2,#0)
+
+ NOP
+ NOP
+ SIF
+ RTS
+
+_FAIL
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$02
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; Test Logical Byte wide instructions
+;-------------------------------------------------------------------------------
+_START2
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$03 ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$02 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ ;Test ANDL instruction
+ LDL R7,#$55 ; R7=$0055
+ LDH R7,#$a5 ; R7=$a555
+ ANDL R7,#$00 ; R7=&a500
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BMI _FAIL2 ; Negative Flag should be clear
+ LDL R3,#$00 ; R3=$0000
+ LDH R3,#$a5 ; R3=$a500
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+ LDL R7,#$c5 ; R7=$00c5
+ LDH R7,#$a5 ; R7=$a5c5
+ ANDL R7,#$80 ; R7=$a580
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+ LDL R3,#$80 ; R3=$0080
+ LDH R3,#$a5 ; R3=$a580
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+
+ ;Test ANDH instruction
+ LDL R7,#$55 ; R7=$0055
+ LDH R7,#$a5 ; R7=$a555
+ ANDH R7,#$00 ; R7=&0055
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BMI _FAIL2 ; Negative Flag should be clear
+ LDL R3,#$55 ; R3=$0000
+ LDH R3,#$00 ; R3=$a500
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+ LDL R7,#$c5 ; R7=$00c5
+ LDH R7,#$a5 ; R7=$a5c5
+ ANDH R7,#$80 ; R7=$80c5
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+ LDL R3,#$c5 ; R3=$00c5
+ LDH R3,#$80 ; R3=$80c5
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+
+ ;Test BITL instruction
+ LDL R7,#$55 ; R7=$0055
+ LDH R7,#$a5 ; R7=$a555
+ BITL R7,#$00 ; R7=&a500
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BMI _FAIL2 ; Negative Flag should be clear
+ LDL R7,#$c5 ; R7=$00c5
+ LDH R7,#$a5 ; R7=$a5c5
+ BITL R7,#$80 ; R7=$a580
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+
+ ;Test BITH instruction
+ LDL R7,#$55 ; R7=$0055
+ LDH R7,#$a5 ; R7=$a555
+ BITH R7,#$00 ; R7=&0055
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BMI _FAIL2 ; Negative Flag should be clear
+ LDL R7,#$c5 ; R7=$00c5
+ LDH R7,#$a5 ; R7=$a5c5
+ BITH R7,#$80 ; R7=$80c5
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+
+ ;Test ORL instruction
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ LDL R7,#$00 ; R7=$0000
+ LDH R7,#$a5 ; R7=$a500
+ ORL R7,#$00 ; R7=&a500
+ BMI _FAIL2 ; Negative Flag should be clear
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCC _FAIL2 ; Carry Flag should be set
+ LDL R3,#$00 ; R3=$0000
+ LDH R3,#$a5 ; R3=$a500
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R7,#$9f ; R7=$009f
+ LDH R7,#$a5 ; R7=$a59f
+ ORL R7,#$60 ; R7=$a5ff
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCS _FAIL2 ; Carry Flag should be clear
+ LDL R3,#$ff ; R3=$00ff
+ LDH R3,#$a5 ; R3=$a5ff
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+
+ ;Test ORH instruction
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ LDL R7,#$88 ; R7=$0088
+ LDH R7,#$00 ; R7=$0088
+ ORH R7,#$00 ; R7=&0088
+ BMI _FAIL2 ; Negative Flag should be clear
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCC _FAIL2 ; Carry Flag should be set
+ LDL R3,#$88 ; R3=$0088
+ LDH R3,#$00 ; R3=$0088
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R7,#$36 ; R7=$0036
+ LDH R7,#$a1 ; R7=$a136
+ ORH R7,#$50 ; R7=$f136
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCS _FAIL2 ; Carry Flag should be clear
+ LDL R3,#$36 ; R3=$0036
+ LDH R3,#$f1 ; R3=$f136
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+
+ ;Test XNORL instruction
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ LDL R7,#$c3 ; R7=$00c3
+ LDH R7,#$96 ; R7=$96c3
+ XNORL R7,#$3c ; R7=$9600
+ BMI _FAIL2 ; Negative Flag should be clear
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCC _FAIL2 ; Carry Flag should be set
+ LDL R3,#$00 ; R3=$0000
+ LDH R3,#$96 ; R3=$9600
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$00 ; R6=$0000
+ LDH R6,#$a5 ; R6=$a500
+ XNORL R6,#$73 ; R6=$a58c
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCS _FAIL2 ; Carry Flag should be clear
+ LDL R3,#$8c ; R3=$008c
+ LDH R3,#$a5 ; R3=$a58c
+ SUB R0,R6,R3 ; Compare R6 to R3
+ BNE _FAIL2
+
+ ;Test XNORH instruction
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ LDL R7,#$c3 ; R7=$00c3
+ LDH R7,#$96 ; R7=$96c3
+ XNORH R7,#$69 ; R7=$00c3
+ BMI _FAIL2 ; Negative Flag should be clear
+ BNE _FAIL2 ; Zero Flag should be set
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCC _FAIL2 ; Carry Flag should be set
+ LDL R3,#$c3 ; R3=$00c3
+ LDH R3,#$00 ; R3=$00c3
+ SUB R0,R7,R3 ; Compare R7 to R3
+ BNE _FAIL2
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$66 ; R6=$0066
+ LDH R6,#$66 ; R6=$6666
+ XNORH R6,#$66 ; R6=$ff66
+ BPL _FAIL2 ; Negative Flag should be set
+ BEQ _FAIL2 ; Zero Flag should be clear
+ BVS _FAIL2 ; Overflow Flag should be clear
+ BCS _FAIL2 ; Carry Flag should be clear
+ LDL R3,#$66 ; R3=$0066
+ LDH R3,#$ff ; R3=$ff66
+ SUB R0,R6,R3 ; Compare R6 to R3
+ BNE _FAIL2
+
+
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$04
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_FAIL2
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$04
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; Test Logical Word Wide instructions
+;-------------------------------------------------------------------------------
+_START3
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$05 ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$03 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ ;Test SEX instruction
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ LDL R3,#$00 ; R3=$0000
+ LDH R3,#$ff ; R3=$ff00
+ SEX R3 ; R3=$0000
+ BMI _FAIL3 ; Negative Flag should be clear
+ BNE _FAIL3 ; Zero Flag should be set
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCC _FAIL3 ; Carry Flag should be set
+ LDL R6,#$00 ; R6=$0000
+ LDH R6,#$00 ; R6=$0000
+ SUB R0,R6,R3 ; Compare R6 to R3
+ BNE _FAIL3
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$83 ; R6=$0083
+ LDH R6,#$00 ; R6=$0083
+ SEX R6 ; R6=$ff83
+ BPL _FAIL3 ; Negative Flag should be set
+ BEQ _FAIL3 ; Zero Flag should be clear
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCS _FAIL3 ; Carry Flag should be clear
+ LDL R3,#$83 ; R3=$0083
+ LDH R3,#$ff ; R3=$ff83
+ SUB R0,R6,R3 ; Compare R6 to R3
+ BNE _FAIL3
+
+ ;Test PAR instruction
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ LDL R4,#$00 ; R4=$0000
+ LDH R4,#$00 ; R4=$0000
+ PAR R4 ; R4=$0000
+ BMI _FAIL3 ; Negative Flag should be clear
+ BNE _FAIL3 ; Zero Flag should be set
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCS _FAIL3 ; Carry Flag should be clear
+ LDL R6,#$00 ; R6=$0000
+ LDH R6,#$00 ; R6=$0000
+ SUB R0,R6,R4 ; Compare R6 to R4
+ BNE _FAIL3
+ LDL R2,#$0e
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$01 ; R6=$0001
+ LDH R6,#$03 ; R6=$0301
+ PAR R6 ; R6=$0301
+ BMI _FAIL3 ; Negative Flag should be clear
+ BEQ _FAIL3 ; Zero Flag should be clear
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCC _FAIL3 ; Carry Flag should be set
+ LDL R3,#$01 ; R3=$0001
+ LDH R3,#$03 ; R3=$0301
+ SUB R0,R6,R3 ; Compare R6 to R3
+ BNE _FAIL3
+
+ ;Test AND instruction
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ LDL R6,#$55 ; R6=$0055
+ LDH R6,#$aa ; R6=$aa55
+ LDL R5,#$aa ; R5=$00aa
+ LDH R5,#$55 ; R5=$55aa
+ AND R3,R5,R6 ; R3=$0000
+ BMI _FAIL3 ; Negative Flag should be clear
+ BNE _FAIL3 ; Zero Flag should be set
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCS _FAIL3 ; Carry Flag should be clear
+ SUB R0,R0,R3 ; Compare R0 to R3
+ BNE _FAIL3
+ LDL R7,#$55 ; R7=$00c5
+ LDH R7,#$aa ; R7=$aa55
+ LDL R2,#$07
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
+ AND R4,R6,R7 ; R4=$aa55
+ BPL _FAIL3 ; Negative Flag should be set
+ BEQ _FAIL3 ; Zero Flag should be clear
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCC _FAIL3 ; Carry Flag should be set
+ SUB R0,R4,R7 ; Compare R4 to R7
+ BNE _FAIL2
+
+ ;Test OR instruction
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ LDL R6,#$00 ; R6=$0000
+ LDL R5,#$00 ; R5=$0000
+ OR R3,R5,R6 ; R3=$0000
+ BMI _FAIL3 ; Negative Flag should be clear
+ BNE _FAIL3 ; Zero Flag should be set
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCS _FAIL3 ; Carry Flag should be clear
+ SUB R0,R0,R3 ; Compare R0 to R3
+ BNE _FAIL3
+ LDL R7,#$55 ; R7=$00c5
+ LDH R7,#$aa ; R7=$aa55
+ LDL R6,#$8a ; R6=$008a
+ LDH R6,#$10 ; R7=$108a
+ LDL R2,#$07
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
+ OR R4,R6,R7 ; R4=$badf
+ BPL _FAIL3 ; Negative Flag should be set
+ BEQ _FAIL3 ; Zero Flag should be clear
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCC _FAIL3 ; Carry Flag should be set
+ LDL R3,#$df ; R3=$00df
+ LDH R3,#$ba ; R3=$badf
+ SUB R0,R4,R3 ; Compare R6 to R3
+ BNE _FAIL3
+
+ ;Test XNOR instruction
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ LDL R1,#$55 ; R1=$0055
+ LDH R1,#$aa ; R1=$aa55
+ LDL R5,#$aa ; R5=$00aa
+ LDH R5,#$55 ; R5=$55aa
+ XNOR R3,R5,R1 ; R3=$0000
+ BMI _FAIL3 ; Negative Flag should be clear
+ BNE _FAIL3 ; Zero Flag should be set
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCS _FAIL3 ; Carry Flag should be clear
+ SUB R0,R0,R3 ; Compare R0 to R3
+ BNE _FAIL3
+ LDL R7,#$cc ; R7=$00cc
+ LDH R7,#$33 ; R7=$33cc
+ LDL R2,#$01 ; R2=$0001
+ LDH R2,#$40 ; R2=$4001
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
+ XNOR R4,R7,R2 ; R4=$8c32
+ BPL _FAIL3 ; Negative Flag should be set
+ BEQ _FAIL3 ; Zero Flag should be clear
+ BVS _FAIL3 ; Overflow Flag should be clear
+ BCC _FAIL3 ; Carry Flag should be set
+ LDL R3,#$32 ; R3=$0032
+ LDH R3,#$8c ; R3=$8c32
+ SUB R0,R4,R3 ; Compare R4 to R3
+ BNE _FAIL3
+
+
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$06
+ STB R3,(R2,#0)
+
+ NOP
+ SIF
+ RTS
+
+_FAIL3
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$06
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Bit Field instructions
+;-------------------------------------------------------------------------------
+_START4
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$07 ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$04 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ ;Test BFEXT instruction
+ LDL R2,#$0e
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
+ LDL R5,#$a6 ; Set R5=$00a6
+ LDH R5,#$c3 ; Set R5=$c3a6
+ LDL R4,#$ff ; Set R4=$00ff
+ SEX R4 ; Set R4=$ffff
+ BFEXT R4,R5,R6 ; R4=$000a
+ BMI _FAIL4 ; Negative Flag should be clear
+ BEQ _FAIL4 ; Zero Flag should be clear
+ BVS _FAIL4 ; Overflow Flag should be clear
+ BCS _FAIL4 ; Carry Flag should be clear
+ LDL R7,#$0a ; R7=$00cc
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ LDL R6,#$b8 ; Set offset to 8 and width to 11(12 bits)
+ BFEXT R4,R5,R6 ; R4=$00c3
+ LDL R7,#$c3 ; R7=$00c3
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ ;Test BFINS instruction
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
+ LDL R5,#$a6 ; Set R5=$00a6
+ LDH R5,#$c3 ; Set R5=$c3a6
+ LDL R4,#$ff ; Set R4=$00ff
+ SEX R4 ; Set R4=$ffff
+ BFINS R4,R5,R6 ; R4=$ffaf
+ BPL _FAIL4 ; Negative Flag should be set
+ BEQ _FAIL4 ; Zero Flag should be clear
+ BVS _FAIL4 ; Overflow Flag should be clear
+ BCS _FAIL4 ; Carry Flag should be clear
+ LDL R7,#$6f ; R7=$006f
+ LDH R7,#$ff ; R7=$ff6f
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ LDL R6,#$b0 ; Set offset to 0 and width to 11(12 bits)
+ BFINS R4,R5,R6 ; R4=$f3a6
+ LDL R7,#$a6 ; R7=$00a6
+ LDH R7,#$f3 ; R7=$f3a6
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ ;Test BFINSI instruction
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$3c ; Set offset to 12 and width to 3(4 bits)
+ LDL R5,#$a6 ; Set R5=$00a6
+ LDH R5,#$c3 ; Set R5=$c3a6
+ LDL R4,#$ff ; Set R4=$00ff
+ SEX R4 ; Set R4=$ffff
+ BFINSI R4,R5,R6 ; R4=$9fff
+ BPL _FAIL4 ; Negative Flag should be set
+ BEQ _FAIL4 ; Zero Flag should be clear
+ BVS _FAIL4 ; Overflow Flag should be clear
+ BCS _FAIL4 ; Carry Flag should be clear
+ LDL R7,#$ff ; R7=$00ff
+ LDH R7,#$9f ; R7=$ff6f
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ LDL R6,#$78 ; Set offset to 8 and width to 7(8 bits)
+ BFINSI R4,R5,R6 ; R4=$59ff
+ LDL R7,#$ff ; R7=$00ff
+ LDH R7,#$59 ; R7=$59ff
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ ;Test BFINSX instruction
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ LDL R6,#$38 ; Set offset to 8 and width to 3(4 bits)
+ LDL R5,#$a6 ; Set R5=$00a6
+ LDH R5,#$c3 ; Set R5=$c3a6
+ LDL R4,#$ff ; Set R4=$00ff
+ LDH R4,#$fa ; Set R4=$faff
+ BFINSX R4,R5,R6 ; R4=$f3ff
+ BPL _FAIL4 ; Negative Flag should be set
+ BEQ _FAIL4 ; Zero Flag should be clear
+ BVS _FAIL4 ; Overflow Flag should be clear
+ BCS _FAIL4 ; Carry Flag should be clear
+ LDL R7,#$ff ; R7=$00ff
+ LDH R7,#$f3 ; R7=$f3ff
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+ LDL R6,#$70 ; Set offset to 0 and width to 7(8 bits)
+ BFINSX R4,R5,R6 ; R4=$f3a6
+ LDL R7,#$a6 ; R7=$00a6
+ LDH R7,#$f3 ; R7=$f3a6
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL4
+
+
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$08
+ STB R3,(R2,#0)
+
+ NOP
+ SIF
+ RTS
+
+_FAIL4
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$08
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Branch instructions
+;-------------------------------------------------------------------------------
+_START5
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$09 ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$05 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ ;Test BCC instruction C = 0
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BCC _BCC_OK1 ; Take Branch
+ BRA _BR_ERR
+_BCC_OK1
+ LDL R2,#$01
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
+ BCC _BR_ERR ; Don't take branch
+
+
+ ;Test BCS instruction C = 1
+ LDL R2,#$01
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
+ BCS _BCS_OK1 ; Take Branch
+ BRA _BR_ERR
+_BCS_OK1
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BCS _BR_ERR ; Don't take branch
+
+
+ ;Test BEQ instruction Z = 1
+ LDL R2,#$04
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
+ BEQ _BEQ_OK1 ; Take Branch
+ BRA _BR_ERR
+_BEQ_OK1
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BEQ _BR_ERR ; Don't take branch
+
+
+ ;Test BNE instruction Z = 0
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BNE _BNE_OK1 ; Take Branch
+ BRA _BR_ERR
+_BNE_OK1
+ LDL R2,#$04
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
+ BNE _BR_ERR ; Don't take branch
+
+
+ ;Test BPL instruction N = 0
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BPL _BPL_OK1 ; Take Branch
+ BRA _BR_ERR
+_BPL_OK1
+ LDL R2,#$08
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
+ BPL _BR_ERR ; Don't take branch
+
+
+ ;Test BMI instruction N = 1
+ LDL R2,#$08
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
+ BMI _BMI_OK1 ; Take Branch
+ BRA _BR_ERR
+_BMI_OK1
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BMI _BR_ERR ; Don't take branch
+
+
+ ;Test BVC instruction V = 0
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BVC _BVC_OK1 ; Take Branch
+ BRA _BR_ERR
+_BVC_OK1
+ LDL R2,#$02
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
+ BVC _BR_ERR ; Don't take branch
+
+
+ ;Test BVS instruction V = 1
+ LDL R2,#$02
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
+ BVS _BVS_OK1 ; Take Branch
+ BRA _BR_ERR
+_BVS_OK1
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BVS _BR_ERR ; Don't take branch
+
+
+ ;Test BLS instruction C | Z = 1
+ LDL R2,#$01
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
+ BLS _BLS_OK1 ; Take Branch
+ BRA _BR_ERR
+_BLS_OK1
+ LDL R2,#$04
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
+ BLS _BLS_OK2 ; Take Branch
+ BRA _BR_ERR
+_BLS_OK2
+ LDL R2,#$00
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
+ BLS _BR_ERR ; Don't take branch
+
+
+ ;Test BGE instruction N ^ V = 0
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ BGE _BGE_OK1 ; Take Branch
+ BRA _BR_ERR
+_BGE_OK1
+ LDL R2,#$05
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
+ BGE _BGE_OK2 ; Take Branch
+ BRA _BR_ERR
+_BGE_OK2
+ LDL R2,#$08
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
+ BGE _BR_ERR ; Don't take branch
+
+
+ ;Test BHI instruction Z | C = 0
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ BHI _BHI_OK1 ; Take Branch
+ BRA _BR_ERR
+_BHI_OK1
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ BHI _BR_ERR ; Don't take branch
+
+ LDL R2,#$0e
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ BHI _BR_ERR ; Don't take branch
+
+
+ ;Test BGT instruction Z | (N ^ V) = 0
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ BGT _BGT_OK1 ; Take Branch
+ BRA _BR_ERR
+_BGT_OK1
+ LDL R2,#$01
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
+ BGT _BGT_OK2 ; Take Branch
+ BRA _BR_ERR
+_BGT_OK2
+ LDL R2,#$0e
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ BGT _BR_ERR ; Don't take branch
+
+ LDL R2,#$02
+ TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
+ BGT _BR_ERR ; Don't take branch
+
+ LDL R2,#$08
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
+ BGT _BR_ERR ; Don't take branch
+
+
+ BRA BRA_FWARD
+
+
+_BR_ERR
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$0a
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_BRA_OK
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0a
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+BRA_FWARD
+ BRA _BRA_OK ; Test backward branch caculation
+
+
+;-------------------------------------------------------------------------------
+; Test Subroutine Call and return instructions
+;-------------------------------------------------------------------------------
+_START6
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0b ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$06 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ LDL R4,#$00
+ TFR R5,PC ; Subroutine Call
+ BRA SUB_TST
+
+RET_SUB
+
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0c
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_FAIL6
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$0c
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+SUB_TST
+ LDL R4,#$88 ; If we branch to far then the wrong data will get loaded
+ LDH R4,#$99 ; and we'll make a bad compare to cause test to fail
+ LDL R7,#$88 ; R7=$0088
+ LDH R7,#$99 ; R7=$9988
+ SUB R0,R7,R4 ; Compare R7 to R4
+ BNE _FAIL6
+ JAL R5 ; Jump to return address
+
+;-------------------------------------------------------------------------------
+; Test 16 bit Addition and Substract instructions
+;-------------------------------------------------------------------------------
+_START7
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0d ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$07 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ ;Test SUB instruction
+ LDL R4,#$0f ; R4=$000f
+ LDH R4,#$01 ; R4=$010f
+ LDL R7,#$0e ; R7=$000e
+ LDH R7,#$01 ; R7=$010e
+ LDL R2,#$0f
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
+ SUB R1,R4,R7 ; R4 - R7 => R1
+ BMI _FAIL7 ; Negative Flag should be clear
+ BEQ _FAIL7 ; Zero Flag should be clear
+ BVS _FAIL7 ; Overflow Flag should be clear
+ BCS _FAIL7 ; Carry Flag should be clear
+ LDL R3,#$01 ; R3=$0001
+ SUB R0,R1,R3 ; Compare R1 to R3
+ BNE _FAIL7
+
+ LDL R7,#$0f ; R7=$000f
+ LDH R7,#$01 ; R7=$010f
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ SUB R1,R4,R7 ; R4 - R7 => R1
+ BMI _FAIL7 ; Negative Flag should be clear
+ BNE _FAIL7 ; Zero Flag should be set
+ BVS _FAIL7 ; Overflow Flag should be clear
+ BCS _FAIL7 ; Carry Flag should be clear
+
+
+ ;Test SBC instruction
+ LDL R4,#$11 ; R4=$0011
+ LDH R4,#$01 ; R4=$0111
+ LDL R7,#$0e ; R7=$000e
+ LDH R7,#$01 ; R7=$010e
+ LDL R2,#$0f
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
+ SBC R1,R4,R7 ; R4 - R7 => R1
+ BMI _FAIL7 ; Negative Flag should be clear
+ BEQ _FAIL7 ; Zero Flag should be clear
+ BVS _FAIL7 ; Overflow Flag should be clear
+ BCS _FAIL7 ; Carry Flag should be clear
+ LDL R3,#$02 ; R3=$0002
+ SUB R0,R1,R3 ; Compare R1 to R3
+ BNE _FAIL7
+
+ LDL R4,#$0f ; R4=$000f
+ LDH R4,#$01 ; R4=$010f
+ LDL R7,#$0f ; R7=$000f
+ LDH R7,#$01 ; R7=$010f
+ LDL R2,#$0a
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
+ SBC R1,R4,R7 ; R4 - R7 => R1
+ BMI _FAIL7 ; Negative Flag should be clear
+ BNE _FAIL7 ; Zero Flag should be set
+ BVS _FAIL7 ; Overflow Flag should be clear
+ BCS _FAIL7 ; Carry Flag should be clear
+
+
+ ;Test ADD instruction
+ LDL R4,#$0f ; R4=$000f
+ LDH R4,#$70 ; R4=$700f
+ LDL R7,#$01 ; R7=$0001
+ LDH R7,#$10 ; R7=$1001
+ LDL R2,#$05
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
+ ADD R1,R4,R7 ; R4 + R7 => R1
+ BPL _FAIL7 ; Negative Flag should be set
+ BEQ _FAIL7 ; Zero Flag should be clear
+ BVC _FAIL7 ; Overflow Flag should be set
+ BCS _FAIL7 ; Carry Flag should be clear
+ LDL R3,#$10 ; R3=$0010
+ LDH R3,#$80 ; R3=$8010
+ SUB R0,R1,R3 ; Compare R1 to R3
+ BNE _FAIL7
+
+ LDL R4,#$00 ; R4=$0000
+ LDH R4,#$80 ; R4=$8000
+ LDL R7,#$00 ; R7=$0000
+ LDH R7,#$80 ; R7=$8000
+ LDL R2,#$0f
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
+ ADD R1,R4,R7 ; R4 + R7 => R1
+ BMI _FAIL7 ; Negative Flag should be clear
+ BNE _FAIL7 ; Zero Flag should be set
+ BVC _FAIL7 ; Overflow Flag should be set
+ BCC _FAIL7 ; Carry Flag should be set
+ SUB R0,R1,R0 ; Compare R1 to R0(Zero)
+ BNE _FAIL7
+
+
+ ;Test ADC instruction
+ LDL R4,#$0f ; R4=$000f
+ LDH R4,#$70 ; R4=$700f
+ LDL R7,#$01 ; R7=$0001
+ LDH R7,#$10 ; R7=$1001
+ LDL R2,#$05
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
+ ADC R1,R4,R7 ; R4 + R7 => R1
+ BPL _FAIL7 ; Negative Flag should be set
+ BEQ _FAIL7 ; Zero Flag should be clear
+ BVC _FAIL7 ; Overflow Flag should be set
+ BCS _FAIL7 ; Carry Flag should be clear
+ LDL R3,#$11 ; R3=$0011
+ LDH R3,#$80 ; R3=$8011
+ SUB R0,R1,R3 ; Compare R1 to R3
+ BNE _FAIL7
+
+ LDL R4,#$00 ; R4=$0000
+ LDH R4,#$80 ; R4=$8000
+ LDL R7,#$00 ; R7=$0000
+ LDH R7,#$80 ; R7=$8000
+ LDL R2,#$0c
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
+ ADC R1,R4,R7 ; R4 + R7 => R1
+ BMI _FAIL7 ; Negative Flag should be clear
+ BNE _FAIL7 ; Zero Flag should be set
+ BVC _FAIL7 ; Overflow Flag should be set
+ BCC _FAIL7 ; Carry Flag should be set
+ SUB R0,R1,R0 ; Compare R1 to R0(Zero)
+ BNE _FAIL7
+
+
+_END_7
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0e
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_FAIL7
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$0e
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+;-------------------------------------------------------------------------------
+; Test 8 bit Addition and Substract instructions
+;-------------------------------------------------------------------------------
+_START8
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$0f ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$08 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ ;Test SUBL instruction
+ LDL R5,#$0f ; R5=$000f
+ LDL R2,#$0f
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
+ SUBL R5,#$0e ; R5 - $0e => R5
+ BMI _FAIL8 ; Negative Flag should be clear
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCS _FAIL8 ; Carry Flag should be clear
+ LDL R3,#$01 ; R3=$0001
+ SUB R0,R5,R3 ; Compare R5 to R3
+ BNE _FAIL8
+
+ LDL R7,#$0f ; R7=$000f
+ LDL R2,#$0d
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ SUBL R7,#$10 ; R7 - $10 => R7
+ BPL _FAIL8 ; Negative Flag should be set
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCC _FAIL8 ; Carry Flag should be set
+
+ ;Test SUBH instruction
+ LDL R6,#$11 ; R4=$0011
+ LDH R6,#$81 ; R4=$8111
+ LDL R2,#$0d
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=1
+ SUBH R6,#$70 ; R6 - $70 => R6
+ BMI _FAIL8 ; Negative Flag should be clear
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVC _FAIL8 ; Overflow Flag should be set
+ BCS _FAIL8 ; Carry Flag should be clear
+ LDL R3,#$11 ; R3=$0011
+ LDH R3,#$11 ; R3=$1111
+ SUB R0,R6,R3 ; Compare R6 to R3
+ BNE _FAIL8
+
+ LDL R6,#$00 ; R6=$0000
+ LDH R6,#$01 ; R6=$0100
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ SUBH R6,#$02 ; R6 - $70 => R6
+ BPL _FAIL8 ; Negative Flag should be set
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCC _FAIL8 ; Carry Flag should be set
+
+
+ ;Test CMPL instruction
+ LDL R5,#$0f ; R5=$000f
+ LDL R2,#$0b
+ TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
+ CMPL R5,#$0f ; R5 - $0f => R5
+ BMI _FAIL8 ; Negative Flag should be clear
+ BNE _FAIL8 ; Zero Flag should be set
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCS _FAIL8 ; Carry Flag should be clear
+
+ LDL R7,#$0f ; R7=$000f
+ LDL R2,#$07
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
+ CMPL R7,#$10 ; R7 - $10 => R7
+ BPL _FAIL8 ; Negative Flag should be set
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCC _FAIL8 ; Carry Flag should be set
+
+
+ ;Test CPCH instruction
+ LDL R5,#$00 ; R5=$0000
+ LDH R5,#$01 ; R5=$0001
+ LDL R2,#$0f
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
+ CPCH R5,#$00 ; R5 - $00 - carryflag => nowhere
+ BMI _FAIL8 ; Negative Flag should be clear
+ BNE _FAIL8 ; Zero Flag should be set
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCS _FAIL8 ; Carry Flag should be clear
+ LDL R2,#$06
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
+ CPCH R5,#$02 ; R5 - $00 - carryflag => nowhere
+ BPL _FAIL8 ; Negative Flag should be set
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCC _FAIL8 ; Carry Flag should be set
+
+
+ ;Test ADDH instruction
+ LDL R5,#$0f ; R5=$000f
+ LDH R5,#$70 ; R5=$700f
+ LDL R2,#$0e
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ ADDH R5,#$a0 ; R5 + $a0 => R5
+ BMI _FAIL8 ; Negative Flag should be clear
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCC _FAIL8 ; Carry Flag should be set
+ LDL R3,#$0f ; R3=$000f
+ LDH R3,#$10 ; R3=$100f
+ SUB R0,R5,R3 ; Compare R5 to R3
+ BNE _FAIL8
+
+ LDL R2,#$07
+ TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
+ ADDH R5,#$70 ; R5 + $70 => R5
+ BPL _FAIL8 ; Negative Flag should be set
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVC _FAIL8 ; Overflow Flag should be set
+ BCS _FAIL8 ; Carry Flag should be clear
+ LDL R3,#$0f ; R3=$000f
+ LDH R3,#$80 ; R3=$800f
+ SUB R0,R5,R3 ; Compare R5 to R3
+ BNE _FAIL8
+
+
+ ;Test ADDL instruction
+ LDL R4,#$ff ; R4=$00ff
+ LDH R4,#$70 ; R4=$70ff
+ LDL R2,#$0e
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
+ ADDL R4,#$01 ; R4 + $01 => R4
+ BMI _FAIL8 ; Negative Flag should be clear
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVS _FAIL8 ; Overflow Flag should be clear
+ BCC _FAIL8 ; Carry Flag should be set
+ LDL R5,#$00 ; R5=$0000
+ LDH R5,#$71 ; R5=$7100
+ SUB R0,R4,R5 ; Compare R4 to R5
+ BNE _FAIL8
+
+ LDL R4,#$8e ; R4=$008e
+ LDH R4,#$7f ; R4=$7f8e
+ LDL R2,#$0c
+ TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
+ ADDL R4,#$81 ; R4 + $81 => R4
+ BPL _FAIL8 ; Negative Flag should be set
+ BEQ _FAIL8 ; Zero Flag should be clear
+ BVC _FAIL8 ; Overflow Flag should be set
+ BCC _FAIL8 ; Carry Flag should be set
+ LDL R6,#$0f ; R6=$000f
+ LDH R6,#$80 ; R6=$800f
+ SUB R0,R4,R6 ; Compare R4 to R6
+ BNE _FAIL8
+
+
+_END_8
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$10
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_FAIL8
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$10
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Load and Store instructions
+;-------------------------------------------------------------------------------
+_START9
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$11 ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$09 ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ LDL R1,#$aa ; R1=$00aa
+ LDH R1,#$7f ; R1=$7faa
+ LDL R2,#$55 ; R2=$0055
+ LDH R2,#$6f ; R2=$6f55
+ LDL R3,#$66 ; R3=$0066
+ LDH R3,#$5f ; R3=$5f66
+ LDL R7,#$ff ; R7=$00ff
+ LDH R7,#$ff ; R7=$ffff
+
+ ;Test STB/LDB instruction
+ STB R1,(R0,#$00) ;
+ STB R2,(R0,#$01) ;
+ STB R3,(R0,#$1f) ;
+ LDL R4,#$00 ; R4=$0000
+ LDB R5,(R4,#$00) ;
+ LDB R6,(R4,#$01) ;
+ LDB R7,(R4,#$1f) ;
+ CMPL R5,#$aa ;
+ BNE _FAIL9
+ CMPL R6,#$55 ;
+ BNE _FAIL9
+ CMPL R7,#$66 ;
+ BNE _FAIL9
+ LDL R6,#$66 ; R6=$0066
+ CMP R6,R7 ; Make sure the high byte has been cleared
+ BNE _FAIL9
+
+ ;Test STW/LDW instruction
+ STW R1,(R0,#$04) ; Should be even offsets
+ STW R2,(R0,#$06) ;
+ STW R3,(R0,#$0a) ;
+ LDL R4,#$00 ; R4=$0000
+ LDL R5,#$00 ; R5=$0000
+ LDL R6,#$00 ; R6=$0000
+ LDL R7,#$00 ; R7=$0000
+ LDW R5,(R4,#$04) ;
+ LDW R6,(R4,#$06) ;
+ LDW R7,(R4,#$0a) ;
+ CMP R1,R5 ;
+ BNE _FAIL9
+ CMP R2,R6 ;
+ BNE _FAIL9
+ CMP R3,R7 ;
+ BNE _FAIL9
+
+ ;Test STB/LDB instruction
+ LDL R1,#$cc ; R1=$00cc
+ LDH R1,#$1f ; R1=$1f66
+ LDL R2,#$99 ; R2=$0099
+ LDH R2,#$2f ; R2=$2f99
+
+ LDL R4,#$20 ; R4=$0020 - Base Address
+ LDL R5,#$02 ; R5=$0002 - even offset
+ LDL R6,#$07 ; R6=$0007 - odd offset
+ STB R1,(R4,R5) ;
+ STB R2,(R4,R6) ;
+ LDB R5,(R4,R5) ;
+ LDB R6,(R4,R6) ;
+ CMPL R5,#$cc ;
+ BNE _FAIL9
+ LDL R3,#$99 ; R3=$0099
+ CMP R3,R6 ; Make sure the high byte has been cleared
+ BNE _FAIL9
+
+ ;Test STW/LDW instruction
+ LDL R1,#$cc ; R1=$00cc
+ LDH R1,#$1f ; R1=$1f66
+ LDL R2,#$99 ; R2=$0099
+ LDH R2,#$2f ; R2=$2f99
+
+ LDL R4,#$30 ; R3=$0030 - Base Address
+ LDL R5,#$02 ; R5=$0002
+ LDL R6,#$08 ; R6=$0008
+ STW R1,(R4,R5) ;
+ STW R2,(R4,R6) ;
+ LDW R5,(R4,R5) ;
+ LDW R6,(R4,R6) ;
+ CMP R5,R1 ;
+ BNE _FAIL9
+ CMP R6,R2 ;
+ BNE _FAIL9
+
+ ;Test STB/LDB instruction
+ LDL R1,#$33 ; R1=$0033
+ LDH R1,#$1f ; R1=$1f33
+ LDL R2,#$55 ; R2=$0055
+ LDH R2,#$2f ; R2=$2f55
+
+ LDL R4,#$40 ; R4=$0040 - Base Address
+ LDL R5,#$02 ; R5=$0002 - even offset
+ LDL R6,#$07 ; R6=$0007 - odd offset
+ STB R1,(R4,R5+) ;
+ STB R2,(R4,R6+) ;
+ CMPL R5,#$03 ; Test for 1 byte increment
+ BNE _FAIL9
+ CMPL R6,#$08 ; Test for 1 byte increment
+ BNE _FAIL9
+ LDB R3,(R4,-R5) ;
+ LDB R7,(R4,-R6) ;
+ CMPL R5,#$02 ; Test for 1 byte decrement
+ BNE _FAIL9
+ CMPL R6,#$07 ; Test for 1 byte decrement
+ BNE _FAIL9
+ CMPL R3,#$33 ;
+ BNE _FAIL9
+ LDL R3,#$55 ; R3=$0055
+ CMP R3,R7 ; Make sure the high byte has been cleared
+ BNE _FAIL9
+
+ ;Test STB/LDB instruction
+ LDL R1,#$66 ; R1=$0066
+ LDH R1,#$1f ; R1=$1f66
+ LDL R2,#$99 ; R2=$0099
+ LDH R2,#$2f ; R2=$2f99
+
+ LDL R4,#$50 ; R4=$0050 - Base Address
+ LDL R5,#$04 ; R5=$0004 - even offset
+ LDL R6,#$09 ; R6=$0009 - odd offset
+ STB R1,(R4,-R5) ;
+ STB R2,(R4,-R6) ;
+ CMPL R5,#$03 ; Test for 1 byte decrement
+ BNE _FAIL9
+ CMPL R6,#$08 ; Test for 1 byte decrement
+ BNE _FAIL9
+ LDB R3,(R4,R5+) ;
+ LDB R7,(R4,R6+) ;
+ CMPL R5,#$04 ; Test for 1 byte increment
+ BNE _FAIL9
+ CMPL R6,#$09 ; Test for 1 byte increment
+ BNE _FAIL9
+ CMPL R3,#$66 ;
+ BNE _FAIL9
+ LDL R3,#$99 ; R3=$0099
+ CMP R3,R7 ; Make sure the high byte has been cleared
+ BNE _FAIL9
+
+ ;Test STW/LDW instruction
+ LDL R1,#$aa ; R1=$00aa
+ LDH R1,#$1f ; R1=$1faa
+ LDL R2,#$cc ; R2=$00cc
+ LDH R2,#$2f ; R2=$2fcc
+
+ LDL R4,#$60 ; R4=$0060 - Base Address
+ LDL R5,#$02 ; R5=$0002 - even offset
+ LDL R6,#$08 ; R6=$0008
+ STW R1,(R4,R5+) ;
+ STW R2,(R4,R6+) ;
+ CMPL R5,#$04 ; Test for 2 byte increment
+ BNE _FAIL9
+ CMPL R6,#$0a ; Test for 2 byte increment
+ BNE _FAIL9
+ LDW R3,(R4,-R5) ;
+ LDW R7,(R4,-R6) ;
+ CMPL R5,#$02 ; Test for 2 byte decrement
+ BNE _FAIL9
+ CMPL R6,#$08 ; Test for 2 byte decrement
+ BNE _FAIL9
+ CMP R1,R3 ;
+ BNE _FAIL9
+ CMP R2,R7 ;
+ BNE _FAIL9
+
+_END_9
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$12
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_FAIL9
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$12
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+; Test Semaphore instructions
+;-------------------------------------------------------------------------------
+_START10
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$13 ; Checkpoint Value
+ STB R3,(R2,#0)
+ LDL R3,#$0a ; Thread Value
+ STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
+
+ LDL R1,#$5 ; R1=$0005
+
+ ;Test SSEM instruction
+ SSEM #7 ; semaphores
+ BCC _FAIL10 ; Should be set
+ SSEM R1 ; semaphores
+ BCC _FAIL10 ; Should be set
+
+ SSEM #6 ; semaphore has been set by host
+ BCS _FAIL10 ; Should be clear
+
+ CSEM #7 ; semaphore
+ CSEM R1 ; semaphore #5
+ ; Host will test that these semaphores are clear
+
+ SSEM #3 ; set this semaphore for the host to test
+
+
+_END_10
+ LDL R2,#$00 ; Sent Message to Testbench Check Point Register
+ LDH R2,#$80
+ LDL R3,#$14
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+_FAIL10
+ LDL R2,#$04 ; Sent Message to Testbench Error Register
+ LDH R2,#$80
+ LDL R3,#$14
+ STB R3,(R2,#0)
+
+ SIF
+ RTS
+
+
+;-------------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+
+ TFR R2,CCR ; R2 = CCR
+
+;empty line
+
+BACK_
+
+
+ SIF R7
+ BRK
+
+ ORG $8000 ; Special Testbench Addresses
+_BENCH DS.W 8
+
+
+
+
trunk/sw/xgate_test_code/inst_test/inst_test.s
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+*
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