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URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

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  • This comparison shows the changes necessary to convert path 
    /xgate
    from Rev 85 to Rev 86
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  •

Rev 85 → Rev 86

/trunk/bench/verilog/tst_bench_top.v
46,6 → 46,9
parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
parameter STOP_ON_ERROR = 1'b0;
parameter MAX_VECTOR = 9000;
parameter IR_BITS = 4; // Number of bits in JTAG instruction
parameter JTAG_PERIOD = 4; // JTAG Test clock half period
 
parameter L_BYTE = 2'b01;
parameter H_BYTE = 2'b10;
153,6 → 156,13
reg sync_reset;
reg por_reset_b;
reg scantestmode;
reg jtag_tck;
reg jtag_tdi;
reg jtag_tms;
wire jtag_tdo;
wire jtag_tdo_en;
 
reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
232,6 → 242,10
scantestmode = 0;
error_count = 0;
mem_wait_state_enable = 0;
jtag_tck = 0;
jtag_tdi = 0;
jtag_tms = 1;
 
// channel_req = 0;
 
`ifdef WAVES
410,7 → 424,19
.secure_mode_i( 1'b0 ),
.scantestmode( scantestmode )
);
xgate_jtag #(.IR_BITS(IR_BITS))
jtag(
.jtag_tdo( jtag_tdo ),
.jtag_tdo_en( jtag_tdo_en ),
 
.jtag_tdi( jtag_tdi ),
.jtag_clk( jtag_tck ),
.jtag_reset_n( rstn ),
.jtag_tms( jtag_tms )
);
 
 
tb_slave #(.DWIDTH(16),
.SINGLE_CYCLE(1'b1),
.MAX_CHANNEL(MAX_CHANNEL))
499,6 → 525,27
wrap_up;
end
 
// Main JTAG Test Program
initial
begin
$display("\nstatus at time: %t Testbench started", $time);
// tms, tdi
send_jtag_bit(1,0); // RUN/TEST/IDLE
send_jtag_bit(0,1); // SEL DR
send_jtag_bit(1,1); // SEL IR
send_jtag_bit(1,1); // Capture IR
send_jtag_bit(0,1); // Dead Bit?
send_jtag_bit(0,1); // LSB
send_jtag_bit(0,0); // Bit 1
send_jtag_bit(0,1); // Bit 2
send_jtag_bit(0,0); // Bit 3
send_jtag_bit(1,1); // EXIT1 IR
send_jtag_bit(1,1); // UPDATE IR
send_jtag_bit(0,1); // RUN/TEST/IDLE
send_jtag_bit(0,1); // RUN/TEST/IDLE
 
end
 
////////////////////////////////////////////////////////////////////////////////
// Test CHID Debug mode operation
task test_chid_debug;
1338,6 → 1385,22
endtask
 
////////////////////////////////////////////////////////////////////////////////
task send_jtag_bit;
input tms_val;
input tdi_val;
begin
jtag_tck = 0;
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
jtag_tck = 1;
#1;
jtag_tms = tms_val;
jtag_tdi = tdi_val;
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
jtag_tck = 0;
end
endtask
 
////////////////////////////////////////////////////////////////////////////////
function [15:0] four_2_16;
input [3:0] vector;
begin

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