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Rev 88 → Rev 89

/trunk/bench/verilog/tst_bench_top.v
3,7 → 3,7
// WISHBONE revB.2 compliant Xgate Coprocessor - Test Bench
//
// Author: Bob Hayes
// rehayes@opencores.org
// rehayes@opencores.org
//
// Downloaded from: http://www.opencores.org/projects/xgate.....
//
17,10 → 17,10
//
// Supplemental terms.
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// notice, this list of conditions and the following disclaimer.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
43,12 → 43,9
 
module tst_bench_top();
 
parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
parameter STOP_ON_ERROR = 1'b0;
parameter MAX_VECTOR = 9000;
parameter IR_BITS = 4; // Number of bits in JTAG instruction
parameter JTAG_PERIOD = 4; // JTAG Test clock half period
parameter MAX_VECTOR = 12_000;
 
parameter L_BYTE = 2'b01;
parameter H_BYTE = 2'b10;
56,12 → 53,12
 
 
// Name Address Locations
parameter XGATE_BASE = 24'h1000;
parameter XGATE_BASE = 24'h1000;
parameter XGATE_XGMCTL = XGATE_BASE + 6'h00;
parameter XGATE_XGCHID = XGATE_BASE + 6'h02;
parameter XGATE_XGISPHI = XGATE_BASE + 6'h04;
parameter XGATE_XGISPLO = XGATE_BASE + 6'h06;
parameter XGATE_XGVBR = XGATE_BASE + 6'h08;
parameter XGATE_XGVBR = XGATE_BASE + 6'h08;
parameter XGATE_XGIF_7 = XGATE_BASE + 6'h0a;
parameter XGATE_XGIF_6 = XGATE_BASE + 6'h0c;
parameter XGATE_XGIF_5 = XGATE_BASE + 6'h0e;
70,22 → 67,22
parameter XGATE_XGIF_2 = XGATE_BASE + 6'h14;
parameter XGATE_XGIF_1 = XGATE_BASE + 6'h16;
parameter XGATE_XGIF_0 = XGATE_BASE + 6'h18;
parameter XGATE_XGSWT = XGATE_BASE + 6'h1a;
parameter XGATE_XGSEM = XGATE_BASE + 6'h1c;
parameter XGATE_RES1 = XGATE_BASE + 6'h1e;
parameter XGATE_XGCCR = XGATE_BASE + 6'h20;
parameter XGATE_XGPC = XGATE_BASE + 6'h22;
parameter XGATE_RES2 = XGATE_BASE + 6'h24;
parameter XGATE_XGR1 = XGATE_BASE + 6'h26;
parameter XGATE_XGR2 = XGATE_BASE + 6'h28;
parameter XGATE_XGR3 = XGATE_BASE + 6'h2a;
parameter XGATE_XGR4 = XGATE_BASE + 6'h2c;
parameter XGATE_XGR5 = XGATE_BASE + 6'h2e;
parameter XGATE_XGR6 = XGATE_BASE + 6'h30;
parameter XGATE_XGR7 = XGATE_BASE + 6'h32;
parameter XGATE_XGSWT = XGATE_BASE + 6'h1a;
parameter XGATE_XGSEM = XGATE_BASE + 6'h1c;
parameter XGATE_RES1 = XGATE_BASE + 6'h1e;
parameter XGATE_XGCCR = XGATE_BASE + 6'h20;
parameter XGATE_XGPC = XGATE_BASE + 6'h22;
parameter XGATE_RES2 = XGATE_BASE + 6'h24;
parameter XGATE_XGR1 = XGATE_BASE + 6'h26;
parameter XGATE_XGR2 = XGATE_BASE + 6'h28;
parameter XGATE_XGR3 = XGATE_BASE + 6'h2a;
parameter XGATE_XGR4 = XGATE_BASE + 6'h2c;
parameter XGATE_XGR5 = XGATE_BASE + 6'h2e;
parameter XGATE_XGR6 = XGATE_BASE + 6'h30;
parameter XGATE_XGR7 = XGATE_BASE + 6'h32;
 
// Define bits in XGATE Control Register
parameter XGMCTL_XGEM = 16'h8000;
parameter XGMCTL_XGEM = 16'h8000;
parameter XGMCTL_XGFRZM = 16'h4000;
parameter XGMCTL_XGDBGM = 15'h2000;
parameter XGMCTL_XGSSM = 15'h1000;
93,14 → 90,14
parameter XGMCTL_XGBRKIEM = 15'h0400;
parameter XGMCTL_XGSWEIFM = 15'h0200;
parameter XGMCTL_XGIEM = 15'h0100;
parameter XGMCTL_XGE = 16'h0080;
parameter XGMCTL_XGE = 16'h0080;
parameter XGMCTL_XGFRZ = 16'h0040;
parameter XGMCTL_XGDBG = 15'h0020;
parameter XGMCTL_XGSS = 15'h0010;
parameter XGMCTL_XGSS = 15'h0010;
parameter XGMCTL_XGFACT = 15'h0008;
parameter XGMCTL_XGBRKIE = 15'h0004;
parameter XGMCTL_XGSWEIF = 15'h0002;
parameter XGMCTL_XGIE = 15'h0001;
parameter XGMCTL_XGIE = 15'h0001;
 
parameter CHECK_POINT = 16'h8000;
parameter CHANNEL_ACK = CHECK_POINT + 2;
126,26 → 123,26
parameter BREAK_CAPT_7 = CHECK_POINT + 78;
 
parameter SYS_RAM_BASE = 24'h00_0000;
parameter RAM_WAIT_STATES = 1; // Number between 0 and 15
parameter SYS_READ_DELAY = 10;
 
parameter RAM_WAIT_STATES = 1; // Number between 0 and 15
parameter SYS_READ_DELAY = 10;
parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
parameter XGATE_SS_DELAY = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
parameter XGATE_SS_DELAY = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
 
parameter IRQ_BASE = XGATE_BASE + 64;
parameter IRQ_BYPS_0 = IRQ_BASE + 0;
parameter IRQ_BYPS_1 = IRQ_BASE + 2;
parameter IRQ_BYPS_2 = IRQ_BASE + 4;
parameter IRQ_BYPS_3 = IRQ_BASE + 6;
parameter IRQ_BYPS_4 = IRQ_BASE + 8;
parameter IRQ_BYPS_5 = IRQ_BASE + 10;
parameter IRQ_BYPS_6 = IRQ_BASE + 12;
parameter IRQ_BYPS_7 = IRQ_BASE + 14;
parameter IRQ_BASE = XGATE_BASE + 64;
parameter IRQ_BYPS_0 = IRQ_BASE + 0;
parameter IRQ_BYPS_1 = IRQ_BASE + 2;
parameter IRQ_BYPS_2 = IRQ_BASE + 4;
parameter IRQ_BYPS_3 = IRQ_BASE + 6;
parameter IRQ_BYPS_4 = IRQ_BASE + 8;
parameter IRQ_BYPS_5 = IRQ_BASE + 10;
parameter IRQ_BYPS_6 = IRQ_BASE + 12;
parameter IRQ_BYPS_7 = IRQ_BASE + 14;
 
//
// wires && regs
//
reg mstr_test_clk;
reg mstr_test_clk;
reg [19:0] vector;
reg [15:0] error_count;
reg [ 7:0] test_num;
152,39 → 149,32
 
reg [15:0] q, qq;
 
reg rstn;
reg sync_reset;
reg por_reset_b;
reg scantestmode;
reg jtag_tck;
reg jtag_tdi;
reg jtag_tms;
wire jtag_tdo;
wire jtag_tdo_en;
reg rstn;
reg sync_reset;
reg por_reset_b;
reg scantestmode;
 
reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
wire [ 7:0] xgswt; // XGATE Software Trigger outputs
wire xg_sw_irq; // Xgate Software Error interrupt
wire [15:0] brkpt_cntl; //
wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
wire [ 7:0] xgswt; // XGATE Software Trigger outputs
wire xg_sw_irq; // Xgate Software Error interrupt
wire [15:0] brkpt_cntl; //
 
 
wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
wire [ 1:0] wbm_sel_o;
 
reg mem_wait_state_enable;
reg mem_wait_state_enable;
 
wire [15:0] tb_ram_out;
 
wire [15:0] tb_slave_dout; // WISHBONE data bus output from testbench slave module
wire error_pulse; // Error detected output pulse from the testbench slave module
wire tb_slave_ack; // WISHBONE ack from testbench slave module
wire ack_pulse; // Thread ack output pulse from testbench slave module
wire error_pulse; // Error detected output pulse from the testbench slave module
wire tb_slave_ack; // WISHBONE ack from testbench slave module
wire ack_pulse; // Thread ack output pulse from testbench slave module
 
wire wbm_cyc_o;
wire wbm_stb_o;
wire wbm_we_o;
198,38 → 188,38
reg [15:0] data_xgswt;
reg [15:0] data_xgsem;
 
wire sys_cyc;
wire sys_stb;
wire sys_we;
wire sys_cyc;
wire sys_stb;
wire sys_we;
wire [ 1:0] sys_sel;
wire [23:0] sys_adr;
wire [15:0] sys_dout;
wire [15:0] sys_din;
 
wire host_ack;
wire host_ack;
wire [15:0] host_dout;
wire host_cyc;
wire host_stb;
wire host_we;
wire host_cyc;
wire host_stb;
wire host_we;
wire [ 1:0] host_sel;
wire [23:0] host_adr;
wire [15:0] host_din;
 
wire xgate_ack;
wire xgate_ack;
wire [15:0] xgate_dout;
wire xgate_cyc;
wire xgate_stb;
wire xgate_we;
wire xgate_cyc;
wire xgate_stb;
wire xgate_we;
wire [ 1:0] xgate_sel;
wire [15:0] xgate_adr;
wire [15:0] xgate_din;
 
wire xgate_s_stb;
wire xgate_s_ack;
wire xgate_s_stb;
wire xgate_s_ack;
wire [15:0] xgate_s_dout;
 
wire slv2_stb;
wire ram_sel;
wire slv2_stb;
wire ram_sel;
wire [15:0] ram_dout;
 
// initial values and testbench setup
236,31 → 226,34
initial
begin
mstr_test_clk = 0;
vector = 0;
test_num = 0;
por_reset_b = 0;
scantestmode = 0;
error_count = 0;
vector = 0;
test_num = 0;
por_reset_b = 0;
scantestmode = 0;
error_count = 0;
mem_wait_state_enable = 0;
jtag_tck = 0;
jtag_tdi = 0;
jtag_tms = 1;
 
// channel_req = 0;
 
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",tst_bench_top,"AS");
$display("\nINFO: Signal dump enabled ...\n\n");
$shm_open("waves");
$shm_probe("AS", tst_bench_top, "AS");
$display("\nINFO: Signal dump enabled ...\n\n");
`endif
 
`ifdef WAVES_V
$dumpfile ("xgate_wave_dump.lxt");
$dumpvars (0, tst_bench_top);
$dumpon;
$display("\nINFO: VCD Signal dump enabled ...\n\n");
$dumpfile ("xgate_wave_dump.lxt");
$dumpvars (0, tst_bench_top);
$dumpon;
$display("\nINFO: VCD Signal dump enabled ...\n\n");
`endif
 
//-------------------------------------------------------
// Enable Debussy dumping of simulation
`ifdef FSDB
$fsdbDumpfile("verilog.fsdb");
$fsdbDumpvars(0, tst_bench_top);
`endif
 
end
 
// generate clock
271,11 → 264,11
begin
vector <= vector + 1;
if (vector > MAX_VECTOR)
begin
error_count <= error_count + 1;
$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
wrap_up;
end
begin
error_count <= error_count + 1;
$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
wrap_up;
end
end
 
// Add up errors that come from WISHBONE read compares
289,7 → 282,7
#1;
error_count = error_count + 1;
if (STOP_ON_ERROR == 1'b1)
wrap_up;
wrap_up;
end
 
wire [ 6:0] current_active_channel = xgate.risc.xgchid;
332,14 → 325,14
);
 
bus_arbitration #(.dwidth(16),
.awidth(24),
.ram_base(0),
.ram_size(17'h10000),
.slv1_base(XGATE_BASE),
.slv1_size(128),
.slv2_base(CHECK_POINT),
.slv2_size(32),
.ram_wait_states(RAM_WAIT_STATES)
.awidth(24),
.ram_base(0),
.ram_size(17'h10000),
.slv1_base(XGATE_BASE),
.slv1_size(128),
.slv2_base(CHECK_POINT),
.slv2_size(32),
.ram_wait_states(RAM_WAIT_STATES)
)
arb(
// System bus I/O
389,81 → 382,69
// hookup XGATE core - Parameters take all default values
xgate_top #(.SINGLE_CYCLE(1'b0),
.WB_RD_DEFAULT(1'b0),
.MAX_CHANNEL(MAX_CHANNEL)) // Max XGATE Interrupt Channel Number
xgate(
// Wishbone slave interface
.wbs_clk_i( mstr_test_clk ),
.wbs_rst_i( 1'b0 ), // sync_reset
.arst_i( rstn ), // async resetn
.wbs_adr_i( sys_adr[6:1] ),
.wbs_dat_i( sys_dout ),
.wbs_dat_o( xgate_s_dout ),
.wbs_we_i( sys_we ),
.wbs_stb_i( xgate_s_stb ),
.wbs_cyc_i( sys_cyc ),
.wbs_sel_i( sys_sel ),
.wbs_ack_o( xgate_s_ack ),
.wbs_err_o( wbs_err_o ),
.MAX_CHANNEL(MAX_CHANNEL)) // Max XGATE Interrupt Channel Number
xgate(
// Wishbone slave interface
.wbs_clk_i( mstr_test_clk ),
.wbs_rst_i( 1'b0 ), // sync_reset
.arst_i( rstn ), // async resetn
.wbs_adr_i( sys_adr[6:1] ),
.wbs_dat_i( sys_dout ),
.wbs_dat_o( xgate_s_dout ),
.wbs_we_i( sys_we ),
.wbs_stb_i( xgate_s_stb ),
.wbs_cyc_i( sys_cyc ),
.wbs_sel_i( sys_sel ),
.wbs_ack_o( xgate_s_ack ),
.wbs_err_o( wbs_err_o ),
 
// Wishbone master Signals
.wbm_dat_o( wbm_dat_o ),
.wbm_we_o( wbm_we_o ),
.wbm_stb_o( wbm_stb_o ),
.wbm_cyc_o( wbm_cyc_o ),
.wbm_sel_o( wbm_sel_o ),
.wbm_adr_o( wbm_adr_o ),
.wbm_dat_i( sys_din ),
.wbm_ack_i( xgate_ack ),
// Wishbone master Signals
.wbm_dat_o( wbm_dat_o ),
.wbm_we_o( wbm_we_o ),
.wbm_stb_o( wbm_stb_o ),
.wbm_cyc_o( wbm_cyc_o ),
.wbm_sel_o( wbm_sel_o ),
.wbm_adr_o( wbm_adr_o ),
.wbm_dat_i( sys_din ),
.wbm_ack_i( xgate_ack ),
 
.xgif( xgif ), // XGATE Interrupt Flag output
.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
.xgswt( xgswt ),
.risc_clk( mstr_test_clk ),
.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:1]} ),
.debug_mode_i( 1'b0 ),
.secure_mode_i( 1'b0 ),
.scantestmode( scantestmode )
.xgif( xgif ), // XGATE Interrupt Flag output
.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
.xgswt( xgswt ),
.risc_clk( mstr_test_clk ),
.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:1]} ),
.debug_mode_i( 1'b0 ),
.secure_mode_i( 1'b0 ),
.scantestmode( scantestmode )
);
xgate_jtag #(.IR_BITS(IR_BITS))
jtag(
.jtag_tdo( jtag_tdo ),
.jtag_tdo_en( jtag_tdo_en ),
 
.jtag_tdi( jtag_tdi ),
.jtag_clk( jtag_tck ),
.jtag_reset_n( rstn ),
.jtag_tms( jtag_tms )
);
 
 
tb_slave #(.DWIDTH(16),
.SINGLE_CYCLE(1'b1),
.MAX_CHANNEL(MAX_CHANNEL))
tb_slave_regs(
// wishbone interface
.wb_clk_i( mstr_test_clk ),
.wb_rst_i( 1'b0 ),
.arst_i( rstn ),
.wb_adr_i( sys_adr[4:1] ),
.wb_dat_i( sys_dout ),
.wb_dat_o( tb_slave_dout),
.wb_we_i( sys_we ),
.wb_stb_i( slv2_stb ),
.wb_cyc_i( sys_cyc ),
.wb_sel_i( sys_sel ),
.wb_ack_o( tb_slave_ack ),
.SINGLE_CYCLE(1'b1),
.MAX_CHANNEL(MAX_CHANNEL))
tb_slave_regs(
// wishbone interface
.wb_clk_i( mstr_test_clk ),
.wb_rst_i( 1'b0 ),
.arst_i( rstn ),
.wb_adr_i( sys_adr[4:1] ),
.wb_dat_i( sys_dout ),
.wb_dat_o( tb_slave_dout),
.wb_we_i( sys_we ),
.wb_stb_i( slv2_stb ),
.wb_cyc_i( sys_cyc ),
.wb_sel_i( sys_sel ),
.wb_ack_o( tb_slave_ack ),
 
.ack_pulse( ack_pulse ),
.ack_pulse( ack_pulse ),
.brkpt_cntl( brkpt_cntl ),
.error_pulse( error_pulse ),
.brk_pt( ),
.x_address( wbm_adr_o ),
.xgif( xgif ),
.vector( vector )
.error_pulse( error_pulse ),
.brk_pt( ),
.x_address( wbm_adr_o ),
.xgif( xgif ),
.vector( vector )
);
 
tb_debug #(.DWIDTH(16), // Data bus width
tb_debug #(.DWIDTH(16), // Data bus width
.BREAK_CAPT_0(BREAK_CAPT_0),
.BREAK_CAPT_1(BREAK_CAPT_1),
.BREAK_CAPT_2(BREAK_CAPT_2),
473,9 → 454,9
.BREAK_CAPT_6(BREAK_CAPT_6),
.BREAK_CAPT_7(BREAK_CAPT_7))
debugger(
.arst_i( rstn ),
.risc_clk( mstr_test_clk ),
.brkpt_cntl( brkpt_cntl )
.arst_i( rstn ),
.risc_clk( mstr_test_clk ),
.brkpt_cntl( brkpt_cntl )
);
 
 
489,22 → 470,24
$display("\nstatus at time: %t Testbench started", $time);
 
// reset system
rstn = 1'b1; // negate reset
channel_req = 1; //
rstn = 1'b1; // negate reset
channel_req = 1; //
repeat(1) @(posedge mstr_test_clk);
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
#2; // move the async reset away from the clock edge
rstn = 1'b0; // assert async reset
#5; // Keep the async reset pulse with less than a clock cycle
rstn = 1'b1; // negate async reset
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
#2; // move the async reset away from the clock edge
rstn = 1'b0; // assert async reset
#5; // Keep the async reset pulse with less than a clock cycle
rstn = 1'b1; // negate async reset
por_reset_b = 1'b1;
channel_req = 0; //
channel_req = 0; //
repeat(1) @(posedge mstr_test_clk);
sync_reset = 1'b0;
channel_req = 0; //
channel_req = 0; //
 
$display("\nstatus at time: %t done reset", $time);
 
test_skipjack;
 
test_inst_set;
 
test_debug_mode;
514,38 → 497,15
test_chid_debug;
 
reg_test_16;
 
reg_irq;
 
// host_ram;
 
// test_skipjack;
 
// End testing
wrap_up;
end
 
// Main JTAG Test Program
initial
begin
$display("\nstatus at time: %t Testbench started", $time);
// tms, tdi
send_jtag_bit(1,0); // RUN/TEST/IDLE
send_jtag_bit(0,1); // SEL DR
send_jtag_bit(1,1); // SEL IR
send_jtag_bit(1,1); // Capture IR
send_jtag_bit(0,1); // Dead Bit?
send_jtag_bit(0,1); // LSB
send_jtag_bit(0,0); // Bit 1
send_jtag_bit(0,1); // Bit 2
send_jtag_bit(0,0); // Bit 3
send_jtag_bit(1,1); // EXIT1 IR
send_jtag_bit(1,1); // UPDATE IR
send_jtag_bit(0,1); // RUN/TEST/IDLE
send_jtag_bit(0,1); // RUN/TEST/IDLE
 
end
 
////////////////////////////////////////////////////////////////////////////////
// Test CHID Debug mode operation
task test_chid_debug;
558,7 → 518,7
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
 
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
$display("BRK Software Error Interrupt enabled at vector=%d", vector);
 
activate_thread_sw(3);
565,59 → 525,59
 
wait_debug_set; // Debug Status bit is set by BRK instruction
 
host.wb_cmp(0, XGATE_XGPC, 16'h20c6, WORD); // See Program code (BRK).
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
host.wb_cmp(0, XGATE_XGPC, 16'h20c6, WORD); // See Program code (BRK).
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
$display("Debug entry detected at vector=%d", vector);
 
channel_req[5] = 1'b1; //
repeat(7) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
 
host.wb_write(0, XGATE_XGCHID, 16'h000f, H_BYTE); // Check byte select lines
host.wb_write(0, XGATE_XGCHID, 16'h000f, H_BYTE); // Check byte select lines
repeat(4) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Verify CHID is unchanged
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Verify CHID is unchanged
 
host.wb_write(0, XGATE_XGCHID, 16'h000f, L_BYTE); // Change CHID
host.wb_cmp(0, XGATE_XGCHID, 16'h000f, WORD); // Check for Correct CHID
host.wb_write(0, XGATE_XGCHID, 16'h000f, L_BYTE); // Change CHID
host.wb_cmp(0, XGATE_XGCHID, 16'h000f, WORD); // Check for Correct CHID
 
host.wb_write(0, XGATE_XGCHID, 16'h0000, WORD); // Change CHID to 00, RISC should go to IDLE state
host.wb_write(0, XGATE_XGCHID, 16'h0000, WORD); // Change CHID to 00, RISC should go to IDLE state
 
repeat(1) @(posedge mstr_test_clk);
 
host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD); // Change CHID
host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD); // Change CHID
 
repeat(8) @(posedge mstr_test_clk);
$display("Channel ID changed at vector=%d", vector);
 
 
data_xgmctl = XGMCTL_XGDBGM;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
 
wait_debug_set; // Debug Status bit is set by BRK instruction
host.wb_cmp(0, XGATE_XGCHID, 16'h0004, WORD); // Check for Correct CHID
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
wait_debug_set; // Debug Status bit is set by BRK instruction
host.wb_cmp(0, XGATE_XGCHID, 16'h0004, WORD); // Check for Correct CHID
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
 
wait_debug_set; // Debug Status bit is set by BRK instruction
host.wb_cmp(0, XGATE_XGCHID, 16'h0005, WORD); // Check for Correct CHID
host.wb_cmp(0, XGATE_XGCHID, 16'h0005, WORD); // Check for Correct CHID
activate_channel(6);
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
 
wait_debug_set; // Debug Status bit is set by BRK instruction
host.wb_cmp(0, XGATE_XGCHID, 16'h0006, WORD); // Check for Correct CHID
host.wb_cmp(0, XGATE_XGPC, 16'h211c, WORD); // See Program code (BRK)
wait_debug_set; // Debug Status bit is set by BRK instruction
host.wb_cmp(0, XGATE_XGCHID, 16'h0006, WORD); // Check for Correct CHID
host.wb_cmp(0, XGATE_XGPC, 16'h211c, WORD); // See Program code (BRK)
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h211e, WORD); // See Program code (BRA)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
host.wb_cmp(0, XGATE_XGPC, 16'h211e, WORD); // See Program code (BRA)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h2122, WORD); // See Program code ()
host.wb_cmp(0, XGATE_XGPC, 16'h2122, WORD); // See Program code ()
 
repeat(20) @(posedge mstr_test_clk);
 
data_xgmctl = XGMCTL_XGDBGM;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
 
repeat(50) @(posedge mstr_test_clk);
 
655,7 → 615,7
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
 
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
 
activate_thread_sw(2);
 
663,7 → 623,7
repeat(12 + RAM_WAIT_STATES*12) @(posedge mstr_test_clk);
 
data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Set Debug Mode Control Bit
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Set Debug Mode Control Bit
repeat(5) @(posedge mstr_test_clk);
$display("DEBUG bit set at vector=%d", vector);
 
671,37 → 631,37
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
qq = q;
 
// The Xgate test program is in an infinate loop incrementing R3
// The Xgate test program is in an infinite loop incrementing R3
while (qq == q) // Look for change in R3 register
begin
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_read(1, XGATE_XGR3, q, WORD);
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_read(1, XGATE_XGR3, q, WORD);
end
if (q != (qq+1))
begin
$display("Error! - Unexpected value of R3 at vector=%d", vector);
error_count = error_count + 1;
$display("Error! - Unexpected value of R3 at vector=%d", vector);
error_count = error_count + 1;
end
 
 
host.wb_write(1, XGATE_XGPC, 16'h2094, WORD); // Write to PC to force exit from infinite loop
host.wb_write(1, XGATE_XGPC, 16'h2094, WORD); // Write to PC to force exit from infinite loop
repeat(10) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h2094, WORD); // Verify Proram Counter was changed
host.wb_cmp(0, XGATE_XGPC, 16'h2094, WORD); // Verify Proram Counter was changed
$display("Program Counter changed at vector=%d", vector);
 
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGR4, 16'h0002, WORD); // See Program code.(R4 <= R4 + 1)
host.wb_cmp(0, XGATE_XGR4, 16'h0002, WORD); // See Program code.(R4 <= R4 + 1)
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGR4, 16'h0003, WORD); // See Program code.(R4 <= R4 + 1)
host.wb_cmp(0, XGATE_XGR4, 16'h0003, WORD); // See Program code.(R4 <= R4 + 1)
 
data_xgmctl = XGMCTL_XGDBGM;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
// Should be back in Run Mode
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
// Should be back in Run Mode
 
// data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
// host.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Software Interrupt and BRK Interrupt Enable Bit
722,73 → 682,73
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
 
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
 
activate_thread_sw(1);
 
wait_debug_set; // Debug Status bit is set by BRK instruction
 
host.wb_cmp(0, XGATE_XGPC, 16'h203a, WORD); // See Program code (BRK).
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
host.wb_cmp(0, XGATE_XGPC, 16'h203a, WORD); // See Program code (BRK).
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
 
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h203c, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGPC, 16'h203c, WORD); // PC + 2.
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load NOP instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute ADDL instruction
host.wb_cmp(0, XGATE_XGR3, 16'h0002, WORD); // See Program code.(R3 <= R3 + 1)
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // See Program code.
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // PC + 2.
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load NOP instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute ADDL instruction
host.wb_cmp(0, XGATE_XGR3, 16'h0002, WORD); // See Program code.(R3 <= R3 + 1)
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // See Program code.
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // PC + 2.
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // Still no change.
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // Still no change.
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load BRA instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute NOP instruction
host.wb_cmp(0, XGATE_XGPC, 16'h2040, WORD); // See Program code.
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load BRA instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute NOP instruction
host.wb_cmp(0, XGATE_XGPC, 16'h2040, WORD); // See Program code.
 
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute BRA instruction
host.wb_cmp(0, XGATE_XGPC, 16'h2064, WORD); // PC = Branch destination.
// Load ADDL instruction
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute BRA instruction
host.wb_cmp(0, XGATE_XGPC, 16'h2064, WORD); // PC = Branch destination.
// Load ADDL instruction
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load LDW R7 instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute ADDL instruction
host.wb_cmp(0, XGATE_XGPC, 16'h2066, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load LDW R7 instruction)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute ADDL instruction
host.wb_cmp(0, XGATE_XGPC, 16'h2066, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (LDW R7)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (LDW R7)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h2068, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGR7, 16'h00c3, WORD); // See Program code
host.wb_cmp(0, XGATE_XGPC, 16'h2068, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGR7, 16'h00c3, WORD); // See Program code
 
repeat(1) @(posedge mstr_test_clk);
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (BRA)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (BRA)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h2048, WORD); // See Program code.
host.wb_cmp(0, XGATE_XGPC, 16'h2048, WORD); // See Program code.
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (STW R3)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (STW R3)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h204a, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
host.wb_cmp(0, XGATE_XGPC, 16'h204a, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
 
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (R3 <= R3 + 1)
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (R3 <= R3 + 1)
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
host.wb_cmp(0, XGATE_XGPC, 16'h204c, WORD); // PC + 2.
host.wb_cmp(0, XGATE_XGPC, 16'h204c, WORD); // PC + 2.
 
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
data_xgmctl = XGMCTL_XGDBGM;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
// Should be back in Run Mode
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
// Should be back in Run Mode
wait_irq_set(1);
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
 
data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Software Interrupt and BRK Interrupt Enable Bit
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Software Interrupt and BRK Interrupt Enable Bit
repeat(15) @(posedge mstr_test_clk);
 
end
802,7 → 762,7
test_num = test_num + 1;
$display("\nTEST #%d Starts at vector=%d, test_inst_set", test_num, vector);
repeat(1) @(posedge mstr_test_clk);
 
// Enable interrupts to RISC
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
 
843,43 → 803,45
host.wb_write(1, XGATE_XGIF_0, 16'h0200, WORD);
 
host.wb_write(1, XGATE_XGSEM, 16'h5050, WORD);
host.wb_cmp(0, XGATE_XGSEM, 16'h0050, WORD); //
host.wb_cmp(0, XGATE_XGSEM, 16'h0050, WORD); //
activate_thread_sw(10);
wait_irq_set(10);
host.wb_write(1, XGATE_XGIF_0, 16'h0400, WORD);
 
host.wb_write(1, XGATE_XGSEM, 16'hff00, WORD); // clear the old settings
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); //
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); //
host.wb_write(1, XGATE_XGSEM, 16'ha0a0, WORD); // Verify that bits were unlocked by RISC
host.wb_cmp(0, XGATE_XGSEM, 16'h00a0, WORD); // Verify bits were set
host.wb_cmp(0, XGATE_XGSEM, 16'h00a0, WORD); // Verify bits were set
host.wb_write(1, XGATE_XGSEM, 16'hff08, WORD); // Try to set the bit that was left locked by the RISC
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // Verify no bits were set
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // Verify no bits were set
 
repeat(20) @(posedge mstr_test_clk);
 
p_ram.dump_ram(0);
 
read_ram_cmp(16'h0000,16'haa55);
read_ram_cmp(16'h0004,16'h7faa);
read_ram_cmp(16'h0006,16'h6f55);
read_ram_cmp(16'h000a,16'h5f66);
read_ram_cmp(16'h0032,16'h1fcc);
read_ram_cmp(16'h0038,16'h2f99);
read_ram_cmp(16'h0062,16'h1faa);
read_ram_cmp(16'h0068,16'h2fcc);
read_ram_cmp(16'h0022,16'hccxx);
read_ram_cmp(16'h0026,16'hxx99);
read_ram_cmp(16'h0052,16'hxx66);
read_ram_cmp(16'h0058,16'h99xx);
read_ram_cmp(16'h0000, 16'haa55);
read_ram_cmp(16'h0004, 16'h7faa);
read_ram_cmp(16'h0006, 16'h6f55);
read_ram_cmp(16'h000a, 16'h5f66);
read_ram_cmp(16'h0032, 16'h1fcc);
read_ram_cmp(16'h0038, 16'h2f99);
read_ram_cmp(16'h0062, 16'h1faa);
read_ram_cmp(16'h0068, 16'h2fcc);
read_ram_cmp(16'h0022, 16'hccxx);
read_ram_cmp(16'h0026, 16'hxx99);
read_ram_cmp(16'h0052, 16'hxx66);
read_ram_cmp(16'h0058, 16'h99xx);
read_ram_cmp(16'h0080, 16'h9966);
read_ram_cmp(16'h0086, 16'h7533);
 
data_xgmctl = 16'hff00;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
 
end
endtask
 
////////////////////////////////////////////////////////////////////////////////
// Test SKIPJACK Application Program
// Test instruction set
task test_skipjack;
begin
$readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
886,7 → 848,7
test_num = test_num + 1;
$display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
repeat(1) @(posedge mstr_test_clk);
 
host.wb_write(0, DEBUG_CNTRL, 16'hFFFF, WORD);
 
// Enable interrupts to RISC
904,7 → 866,7
// p_ram.dump_ram(16'h9000);
 
data_xgmctl = 16'hff00;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
 
end
endtask
918,45 → 880,32
 
system_reset;
 
host.wb_cmp(0, XGATE_XGMCTL, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGCHID, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGISPHI, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGISPLO, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGVBR, 16'hfe00, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_7, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_6, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_5, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_4, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_3, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_2, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_1, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGPC, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR1, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR2, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR3, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR4, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR5, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR6, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR7, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGMCTL, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGCHID, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGISPHI, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGISPLO, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGVBR, 16'hfe00, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_7, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_6, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_5, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_4, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_3, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_2, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_1, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGPC, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR1, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR2, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR3, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR4, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR5, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR6, 16'h0000, WORD); // verify reset
host.wb_cmp(0, XGATE_XGR7, 16'h0000, WORD); // verify reset
 
/*
parameter XGMCTL_XGDBGM = 15'h2000;
parameter XGMCTL_XGSSM = 15'h1000;
parameter XGMCTL_XGBRKIEM = 15'h0400;
parameter XGMCTL_XGSWEIFM = 15'h0200;
parameter XGMCTL_XGIEM = 15'h0100;
 
parameter XGMCTL_XGDBG = 15'h0020;
parameter XGMCTL_XGSS = 15'h0010;
parameter XGMCTL_XGBRKIE = 15'h0004;
parameter XGMCTL_XGSWEIF = 15'h0002;
parameter XGMCTL_XGIE = 15'h0001;
*/
// Test bits in the Xgate Control Register (XGMCTL)
// Test bits in the Xgate Control Register (XGMCTL)
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
1119,14 → 1068,14
 
system_reset;
 
host.wb_cmp(0, IRQ_BYPS_0, 16'hFFFE, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_1, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_2, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_3, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_4, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_5, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_6, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_7, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_0, 16'hFFFE, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_1, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_2, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_3, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_4, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_5, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_6, 16'hFFFF, WORD); // verify reset
host.wb_cmp(0, IRQ_BYPS_7, 16'hFFFF, WORD); // verify reset
 
 
// Test the Xgate IRQ Bypass Registers (IRQ_BYPS)
1157,17 → 1106,17
channel_req[3:1] = 3'b111; //
 
q = 0;
// The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
// The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
while (q == 0) // Look for change in test bench semapore register
begin
host.wb_read(1, TB_SEMPHORE, q, WORD);
host.wb_read(1, TB_SEMPHORE, q, WORD);
end
 
if (q != 1)
begin
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
end
 
channel_req[1] = 1'b0; //
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
host.wb_write(0, TB_SEMPHORE, 16'h0000, WORD);
1177,51 → 1126,51
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD); // Clear Interrupt Flag from Xgate
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
 
q = 0;
// The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
// The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
while (q == 0) // Look for change in test bench semapore register
begin
host.wb_read(1, TB_SEMPHORE, q, WORD);
host.wb_read(1, TB_SEMPHORE, q, WORD);
end
 
if (q != 2)
begin
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
end
 
channel_req[2] = 1'b0; //
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
host.wb_write(0, TB_SEMPHORE, 16'h0000, WORD);
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
// host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD); // Verify Xgate output interrupt flag set
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD); // Clear Interrupt Flag from Xgate
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
 
q = 0;
// The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
// The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
while (q == 0) // Look for change in test bench semapore register
begin
host.wb_read(1, TB_SEMPHORE, q, WORD);
host.wb_read(1, TB_SEMPHORE, q, WORD);
end
 
if (q != 3)
begin
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
end
 
channel_req[3] = 1'b0; //
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
host.wb_write(0, TB_SEMPHORE, 16'h0000, WORD);
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
// host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD); // Verify Xgate output interrupt flag set
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD); // Clear Interrupt Flag from Xgate
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
 
end
endtask
 
1268,20 → 1217,20
////////////////////////////////////////////////////////////////////////////////
task system_reset; // reset system
begin
repeat(1) @(posedge mstr_test_clk);
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
#2; // move the async reset away from the clock edge
rstn = 1'b0; // assert async reset
#5; // Keep the async reset pulse with less than a clock cycle
rstn = 1'b1; // negate async reset
repeat(1) @(posedge mstr_test_clk);
sync_reset = 1'b0;
repeat(1) @(posedge mstr_test_clk);
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
#2; // move the async reset away from the clock edge
rstn = 1'b0; // assert async reset
#5; // Keep the async reset pulse with less than a clock cycle
rstn = 1'b1; // negate async reset
repeat(1) @(posedge mstr_test_clk);
sync_reset = 1'b0;
 
$display("\nstatus: %t System Reset Task Done", $time);
test_num = test_num + 1;
$display("\nstatus: %t System Reset Task Done", $time);
test_num = test_num + 1;
 
repeat(2) @(posedge mstr_test_clk);
end
repeat(2) @(posedge mstr_test_clk);
end
endtask
 
 
1315,21 → 1264,21
begin
$display("Clearing Channel interrupt flag #%d", chan_val);
if (0 < chan_val < 16)
host.wb_write(1, XGATE_XGIF_0, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_0, 16'hffff, WORD);
if (15 < chan_val < 32)
host.wb_write(1, XGATE_XGIF_1, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_1, 16'hffff, WORD);
if (31 < chan_val < 48)
host.wb_write(1, XGATE_XGIF_2, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_2, 16'hffff, WORD);
if (47 < chan_val < 64)
host.wb_write(1, XGATE_XGIF_3, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_3, 16'hffff, WORD);
if (63 < chan_val < 80)
host.wb_write(1, XGATE_XGIF_4, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_4, 16'hffff, WORD);
if (79 < chan_val < 96)
host.wb_write(1, XGATE_XGIF_5, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_5, 16'hffff, WORD);
if (95 < chan_val < 112)
host.wb_write(1, XGATE_XGIF_6, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_6, 16'hffff, WORD);
if (111 < chan_val < 128)
host.wb_write(1, XGATE_XGIF_7, 16'hffff, WORD);
host.wb_write(1, XGATE_XGIF_7, 16'hffff, WORD);
 
channel_req[chan_val] = 1'b0; //
repeat(1) @(posedge mstr_test_clk);
1355,7 → 1304,7
task read_ram_cmp;
input [15:0] address;
input [15:0] value;
reg [15:0] q;
reg [15:0] q;
begin
 
// BIGENDIAN
1362,10 → 1311,10
q = {p_ram.ram_8[address], p_ram.ram_8[address+1]};
// "X" compares don't work, "X" in value or q always match
if (value != q)
begin
error_count = error_count + 1;
$display("RAM Data compare error at address %h. Received %h, expected %h at time %t", address, q, value, $time);
end
begin
error_count = error_count + 1;
$display("RAM Data compare error at address %h. Received %h, expected %h at time %t", address, q, value, $time);
end
end
endtask
 
1385,22 → 1334,6
endtask
 
////////////////////////////////////////////////////////////////////////////////
task send_jtag_bit;
input tms_val;
input tdi_val;
begin
jtag_tck = 0;
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
jtag_tck = 1;
#1;
jtag_tms = tms_val;
jtag_tdi = tdi_val;
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
jtag_tck = 0;
end
endtask
 
////////////////////////////////////////////////////////////////////////////////
function [15:0] four_2_16;
input [3:0] vector;
begin
1430,20 → 1363,20
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module bus_arbitration #(parameter dwidth = 16,
parameter awidth = 24,
parameter ram_base = 0,
parameter ram_size = 16'hffff,
parameter slv1_base = 0,
parameter slv1_size = 1,
parameter slv2_base = 0,
parameter slv2_size = 1,
module bus_arbitration #(parameter dwidth = 16,
parameter awidth = 24,
parameter ram_base = 0,
parameter ram_size = 16'hffff,
parameter slv1_base = 0,
parameter slv1_size = 1,
parameter slv2_base = 0,
parameter slv2_size = 1,
parameter ram_wait_states = 0) // Number between 0 and 15
(
// System bus I/O
output reg sys_cyc,
output reg sys_stb,
output reg sys_we,
output reg sys_cyc,
output reg sys_stb,
output reg sys_we,
output reg [dwidth/8 -1:0] sys_sel,
output reg [awidth -1:0] sys_adr,
output reg [dwidth -1:0] sys_dout,
1450,73 → 1383,73
output [dwidth -1:0] sys_din,
 
// Host bus I/O
output host_ack,
output host_ack,
output [dwidth -1:0] host_dout,
input host_cyc,
input host_stb,
input host_we,
input [dwidth/8 -1:0] host_sel,
input [awidth -1:0] host_adr,
input [dwidth -1:0] host_din,
input host_cyc,
input host_stb,
input host_we,
input [dwidth/8 -1:0] host_sel,
input [awidth -1:0] host_adr,
input [dwidth -1:0] host_din,
 
// Alternate Bus Master #1 Bus I/O
output alt1_ack,
output alt1_ack,
output [dwidth -1:0] alt1_dout,
input alt1_cyc,
input alt1_stb,
input alt1_we,
input [dwidth/8 -1:0] alt1_sel,
input [awidth -1:0] alt1_adr,
input [dwidth -1:0] alt1_din,
input alt1_cyc,
input alt1_stb,
input alt1_we,
input [dwidth/8 -1:0] alt1_sel,
input [awidth -1:0] alt1_adr,
input [dwidth -1:0] alt1_din,
 
// System RAM memory signals
output ram_sel,
input [dwidth -1:0] ram_dout,
output ram_sel,
input [dwidth -1:0] ram_dout,
 
// Slave #1 Bus I/O
output slv1_stb,
input slv1_ack,
input [dwidth -1:0] slv1_din,
output slv1_stb,
input slv1_ack,
input [dwidth -1:0] slv1_din,
 
// Slave #2 Bus I/O
output slv2_stb,
input slv2_ack,
input [dwidth -1:0] slv2_din,
output slv2_stb,
input slv2_ack,
input [dwidth -1:0] slv2_din,
 
// Miscellaneous
input host_clk,
input risc_clk,
input rst, // No Connect
input err, // No Connect
input rty // No Connect
input host_clk,
input risc_clk,
input rst, // No Connect
input err, // No Connect
input rty // No Connect
);
 
// States for bus arbitration
parameter [1:0] BUS_IDLE = 2'b00,
HOST_OWNS = 2'b10,
RISC_OWNS = 2'b11;
parameter [1:0] BUS_IDLE = 2'b00,
HOST_OWNS = 2'b10,
RISC_OWNS = 2'b11;
 
parameter max_bus_hold = 5; // Max number of cycles any bus master can hold the system bus
parameter max_bus_hold = 5; // Max number of cycles any bus master can hold the system bus
//////////////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire ram_ack; //
wire any_ack; //
reg host_wait; // Host bus in wait state, Hold the bus till the transaction complets
wire ram_ack; //
wire any_ack; //
reg host_wait; // Host bus in wait state, Hold the bus till the transaction complets
reg [3:0] host_cycle_cnt; // Used to count the cycle the host and break the lock if the risc needs access
 
wire risc_lock; // RISC has the slave bus
reg risc_wait; // RISC bus in wait state, Hold the bus till the transaction complets
wire risc_lock; // RISC has the slave bus
reg risc_wait; // RISC bus in wait state, Hold the bus till the transaction complets
reg [3:0] risc_cycle_cnt; // Used to count the cycle the risc and break the lock if the host needs access
 
reg [1:0] owner_state;
reg [1:0] owner_ns;
 
wire host_timeout;
wire risc_timeout;
wire host_timeout;
wire risc_timeout;
 
wire ram_ack_dly; // Delayed bus ack to simulate bus wait states
wire ram_ack_dly; // Delayed bus ack to simulate bus wait states
reg [3:0] ack_dly_cnt; // Counter to delay bus ack to master modules
 
 
1531,26 → 1464,26
always @*
case (owner_state)
BUS_IDLE :
begin
if (host_cyc)
owner_ns = HOST_OWNS;
else if (alt1_cyc)
owner_ns = RISC_OWNS;
end
begin
if (host_cyc)
owner_ns = HOST_OWNS;
else if (alt1_cyc)
owner_ns = RISC_OWNS;
end
HOST_OWNS :
begin
if (!host_cyc && !alt1_cyc)
owner_ns = BUS_IDLE;
else if (alt1_cyc && (!host_cyc || host_timeout))
owner_ns = RISC_OWNS;
end
begin
if (!host_cyc && !alt1_cyc)
owner_ns = BUS_IDLE;
else if (alt1_cyc && (!host_cyc || host_timeout))
owner_ns = RISC_OWNS;
end
RISC_OWNS :
begin
if (!host_cyc && !alt1_cyc)
owner_ns = BUS_IDLE;
else if (host_cyc && (!alt1_cyc || risc_timeout))
owner_ns = HOST_OWNS;
end
begin
if (!host_cyc && !alt1_cyc)
owner_ns = BUS_IDLE;
else if (host_cyc && (!alt1_cyc || risc_timeout))
owner_ns = HOST_OWNS;
end
default : owner_ns = BUS_IDLE;
endcase
 
1564,7 → 1497,7
host_cycle_cnt <= 0;
else if ((owner_state != HOST_OWNS) || !alt1_cyc)
host_cycle_cnt <= 0;
else if (&host_cycle_cnt && !host_timeout) // Don't allow rollover
else if (&host_cycle_cnt && !host_timeout) // Don't allow rollover
host_cycle_cnt <= host_cycle_cnt;
else if ((owner_state == HOST_OWNS) && alt1_cyc)
host_cycle_cnt <= host_cycle_cnt + 1'b1;
1575,7 → 1508,7
risc_cycle_cnt <= 0;
else if ((owner_state != RISC_OWNS) || !host_cyc)
risc_cycle_cnt <= 0;
else if (&risc_cycle_cnt && !risc_timeout) // Don't allow rollover
else if (&risc_cycle_cnt && !risc_timeout) // Don't allow rollover
risc_cycle_cnt <= risc_cycle_cnt;
else if ((owner_state == RISC_OWNS) && host_cyc)
risc_cycle_cnt <= risc_cycle_cnt + 1'b1;
1592,8 → 1525,8
 
// Address decoding for Testbench access to RAM
assign ram_sel = sys_cyc && sys_stb && !(slv1_stb || slv2_stb) &&
(sys_adr >= ram_base) &&
(sys_adr < (ram_base + ram_size));
(sys_adr >= ram_base) &&
(sys_adr < (ram_base + ram_size));
 
// Throw in some wait states from the memory
always @(posedge host_clk)
1608,48 → 1541,48
 
// Create the System Read Data Bus from the Slave output data buses
assign sys_din = ({dwidth{1'b1}} & slv1_din) |
({dwidth{slv2_stb}} & slv2_din) |
({dwidth{ram_sel}} & ram_dout);
({dwidth{slv2_stb}} & slv2_din) |
({dwidth{ram_sel}} & ram_dout);
 
// Mux for System Bus access
always @*
case (owner_state)
BUS_IDLE :
begin
sys_cyc = 0;
sys_stb = 0;
sys_we = 0;
sys_sel = 0;
sys_adr = 0;
sys_dout = 0;
end
begin
sys_cyc = 0;
sys_stb = 0;
sys_we = 0;
sys_sel = 0;
sys_adr = 0;
sys_dout = 0;
end
HOST_OWNS :
begin
sys_cyc = host_cyc;
sys_stb = host_stb;
sys_we = host_we;
sys_sel = host_sel;
sys_adr = host_adr;
sys_dout = host_din;
end
begin
sys_cyc = host_cyc;
sys_stb = host_stb;
sys_we = host_we;
sys_sel = host_sel;
sys_adr = host_adr;
sys_dout = host_din;
end
RISC_OWNS :
begin
sys_cyc = alt1_cyc;
sys_stb = alt1_stb;
sys_we = alt1_we;
sys_sel = alt1_sel;
sys_adr = alt1_adr;
sys_dout = alt1_din;
end
begin
sys_cyc = alt1_cyc;
sys_stb = alt1_stb;
sys_we = alt1_we;
sys_sel = alt1_sel;
sys_adr = alt1_adr;
sys_dout = alt1_din;
end
default :
begin
sys_cyc = 0;
sys_stb = 0;
sys_we = 0;
sys_sel = 0;
sys_adr = 0;
sys_dout = 0;
end
begin
sys_cyc = 0;
sys_stb = 0;
sys_we = 0;
sys_sel = 0;
sys_adr = 0;
sys_dout = 0;
end
endcase
 
endmodule // bus_arbitration
1658,38 → 1591,38
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module tb_slave #(parameter SINGLE_CYCLE = 1'b0, // No bus wait state added
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter DWIDTH = 16) // Data bus width
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter DWIDTH = 16) // Data bus width
(
// Wishbone Signals
output [DWIDTH-1:0] wb_dat_o, // databus output
output wb_ack_o, // bus cycle acknowledge output
input wb_clk_i, // master clock input
input wb_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [3:0] wb_adr_i, // lower address bits
input [DWIDTH-1:0] wb_dat_i, // databus input
input wb_we_i, // write enable input
input wb_stb_i, // stobe/core select signal
input wb_cyc_i, // valid bus cycle input
input [1:0] wb_sel_i, // Select byte in word bus transaction
output [DWIDTH-1:0] wb_dat_o, // databus output
output wb_ack_o, // bus cycle acknowledge output
input wb_clk_i, // master clock input
input wb_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [ 3:0] wb_adr_i, // lower address bits
input [DWIDTH-1:0] wb_dat_i, // databus input
input wb_we_i, // write enable input
input wb_stb_i, // stobe/core select signal
input wb_cyc_i, // valid bus cycle input
input [ 1:0] wb_sel_i, // Select byte in word bus transaction
// Slave unique IO Signals
output reg error_pulse, // Error detected output pulse
output reg ack_pulse, // Thread ack output pulse
output reg error_pulse, // Error detected output pulse
output reg ack_pulse, // Thread ack output pulse
output reg [DWIDTH-1:0] brkpt_cntl, // Break Point Control reg
 
output brk_pt, // Break point
input [15:0] x_address, // XGATE WISHBONE Master bus address
input [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
input [19:0] vector
output brk_pt, // Break point
input [15:0] x_address, // XGATE WISHBONE Master bus address
input [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
input [19:0] vector
);
 
wire async_rst_b; // Asyncronous reset
wire sync_reset; // Syncronous reset
wire async_rst_b; // Asyncronous reset
wire sync_reset; // Syncronous reset
 
// Wishbone Bus interface
// registers
reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux
reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data
 
1706,9 → 1639,9
event channel_err_wrt;
 
// Wires
wire module_sel; // This module is selected for bus transaction
wire wb_wacc; // WISHBONE Write Strobe
wire wb_racc; // WISHBONE Read Access (Clock gating signal)
wire module_sel; // This module is selected for bus transaction
wire wb_wacc; // WISHBONE Write Strobe
wire wb_racc; // WISHBONE Read Access (Clock gating signal)
 
//
// module body
1728,15 → 1661,15
// Accesses in back to back clock cycles are not possable.
always @(posedge wb_clk_i or negedge arst_i)
if (!arst_i)
bus_wait_state <= 1'b0;
bus_wait_state <= 1'b0;
else if (wb_rst_i)
bus_wait_state <= 1'b0;
bus_wait_state <= 1'b0;
else
bus_wait_state <= module_sel && !bus_wait_state;
bus_wait_state <= module_sel && !bus_wait_state;
 
// assign data read bus -- DAT_O
always @(posedge wb_clk_i)
if ( wb_racc ) // Clock gate for power saving
if ( wb_racc ) // Clock gate for power saving
rd_data_reg <= rd_data_mux;
 
// WISHBONE Read Data Mux
1763,60 → 1696,60
always @(posedge wb_clk_i or negedge arst_i)
begin
if (!arst_i)
begin
check_point_reg <= 0;
channel_ack_reg <= 0;
channel_err_reg <= 0;
ack_pulse <= 0;
error_pulse <= 0;
brkpt_cntl <= 0;
brkpt_addr_reg <= 0;
tb_semaphr_reg <= 0;
end
begin
check_point_reg <= 0;
channel_ack_reg <= 0;
channel_err_reg <= 0;
ack_pulse <= 0;
error_pulse <= 0;
brkpt_cntl <= 0;
brkpt_addr_reg <= 0;
tb_semaphr_reg <= 0;
end
else if (wb_wacc)
case (wb_adr_i) // synopsys parallel_case
3'b000 :
begin
check_point_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : check_point_reg[ 7:0];
check_point_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : check_point_reg[15:8];
-> check_point_wrt;
end
3'b001 :
begin
channel_ack_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_ack_reg[ 7:0];
channel_ack_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_ack_reg[15:8];
ack_pulse <= 1;
-> channel_ack_wrt;
end
3'b010 :
begin
channel_err_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_err_reg[ 7:0];
channel_err_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_err_reg[15:8];
error_pulse <= 1'b1;
-> channel_err_wrt;
end
3'b011 :
begin
brkpt_cntl[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl[ 7:0];
brkpt_cntl[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl[15:8];
end
3'b100 :
begin
brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
end
3'b101 :
begin
tb_semaphr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : tb_semaphr_reg[ 7:0];
tb_semaphr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : tb_semaphr_reg[15:8];
end
default: ;
endcase
case (wb_adr_i) // synopsys parallel_case
3'b000 :
begin
check_point_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : check_point_reg[ 7:0];
check_point_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : check_point_reg[15:8];
-> check_point_wrt;
end
3'b001 :
begin
channel_ack_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_ack_reg[ 7:0];
channel_ack_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_ack_reg[15:8];
ack_pulse <= 1;
-> channel_ack_wrt;
end
3'b010 :
begin
channel_err_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_err_reg[ 7:0];
channel_err_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_err_reg[15:8];
error_pulse <= 1'b1;
-> channel_err_wrt;
end
3'b011 :
begin
brkpt_cntl[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl[ 7:0];
brkpt_cntl[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl[15:8];
end
3'b100 :
begin
brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
end
3'b101 :
begin
tb_semaphr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : tb_semaphr_reg[ 7:0];
tb_semaphr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : tb_semaphr_reg[15:8];
end
default: ;
endcase
else
begin
ack_pulse <= 0;
error_pulse <= 1'b0;
end
begin
ack_pulse <= 0;
error_pulse <= 1'b0;
end
end
 
always @check_point_wrt
1828,7 → 1761,7
always @channel_err_wrt
begin
#1;
$display("\n ------ !!!!! Software Checkpoint Error #%d -- at vector=%d\n -------", channel_err_reg, vector);
$display("\n ------ !!!!! Software Checkpoint Error #%d -- at vector=%d\n -------", channel_err_reg, vector);
end
 
 
1837,7 → 1770,7
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module tb_debug #(parameter DWIDTH = 16, // Data bus width
module tb_debug #(parameter DWIDTH = 16, // Data bus width
parameter BREAK_CAPT_0 = 0,
parameter BREAK_CAPT_1 = 0,
parameter BREAK_CAPT_2 = 0,
1846,12 → 1779,12
parameter BREAK_CAPT_5 = 0,
parameter BREAK_CAPT_6 = 0,
parameter BREAK_CAPT_7 = 0
)
)
(
// Wishbone Signals
input arst_i, // asynchronous reset
input arst_i, // asynchronous reset
input risc_clk,
input [DWIDTH-1:0] brkpt_cntl // databus input
input [DWIDTH-1:0] brkpt_cntl // databus input
);
 
wire [15:0] next_pc = xgate.risc.program_counter;
1862,7 → 1795,7
wire [15:0] x5 = xgate.risc.xgr5;
wire [15:0] x6 = xgate.risc.xgr6;
wire [15:0] x7 = xgate.risc.xgr7;
 
reg [15:0] cap_x1;
reg [15:0] cap_x2;
reg [15:0] cap_x3;
1870,7 → 1803,7
reg [15:0] cap_x5;
reg [15:0] cap_x6;
reg [15:0] cap_x7;
 
reg [15:0] break_addr_0;
reg [15:0] break_addr_1;
reg [15:0] break_addr_2;
1879,11 → 1812,11
reg [15:0] break_addr_5;
reg [15:0] break_addr_6;
reg [15:0] break_addr_7;
 
reg detect_addr;
 
wire trigger, trigger0, trigger1, trigger3, trigger4, trigger5, trigger6, trigger7;
 
initial
begin
break_addr_0 = 0;
1894,7 → 1827,7
break_addr_5 = 0;
break_addr_6 = 0;
break_addr_7 = 0;
repeat(4) @(posedge risc_clk); // Note: !! This should come after code load
repeat(4) @(posedge risc_clk);
break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
1904,7 → 1837,7
break_addr_6 = {p_ram.ram_8[BREAK_CAPT_6], p_ram.ram_8[BREAK_CAPT_6+1]};
break_addr_7 = {p_ram.ram_8[BREAK_CAPT_7], p_ram.ram_8[BREAK_CAPT_7+1]};
end
 
assign trigger0 = (next_pc === break_addr_0) && brkpt_cntl[ 8];
assign trigger1 = (next_pc === break_addr_1) && brkpt_cntl[ 9];
assign trigger2 = (next_pc === break_addr_2) && brkpt_cntl[10];
1913,32 → 1846,32
assign trigger5 = (next_pc === break_addr_5) && brkpt_cntl[13];
assign trigger6 = (next_pc === break_addr_6) && brkpt_cntl[14];
assign trigger7 = (next_pc === break_addr_7) && brkpt_cntl[15];
 
assign trigger = brkpt_cntl[0] &
(trigger0 | trigger1 | trigger2 | trigger3 | trigger4 | trigger5 | trigger6 | trigger7);
 
always @(posedge risc_clk or negedge arst_i)
begin
if (!arst_i)
begin
cap_x1 <= 0;
cap_x2 <= 0;
cap_x3 <= 0;
cap_x4 <= 0;
cap_x5 <= 0;
cap_x6 <= 0;
cap_x7 <= 0;
end
begin
cap_x1 <= 0;
cap_x2 <= 0;
cap_x3 <= 0;
cap_x4 <= 0;
cap_x5 <= 0;
cap_x6 <= 0;
cap_x7 <= 0;
end
else if (trigger)
begin
cap_x1 <= x1;
cap_x2 <= x2;
cap_x3 <= x3;
cap_x4 <= x4;
cap_x5 <= x5;
cap_x6 <= x6;
cap_x7 <= x7;
end
begin
cap_x1 <= x1;
cap_x2 <= x2;
cap_x3 <= x3;
cap_x4 <= x4;
cap_x5 <= x5;
cap_x6 <= x6;
cap_x7 <= x7;
end
end
 
 
/trunk/bench/verilog/inst_test.v
1,11 → 1,11
 
@2000 29 8E
@2000 2A 0A
@2012 56 FF
@201E F2 04 FA 80 F3 FF 53 40 03 00 02 00 F2 00 FA 80 F3 01 53 40 53 42 F5 01 FD 4F 0C B0 2E 8C F6 0E 18 D0 24 89 0C 10 20 87 FD 00 0C B0 22 84 2E 83 18 10 24 81 F5 04 FD 81 F3 03 0D 71 20 7C 2E 7B
@205E F4 20 FC F0 18 B0 24 77 F5 10 FD 88 F3 05 0D 72 20 72 F4 00 FC 02 18 B0 24 6E F5 88 FD 10 F3 04 0D 73 20 69 F4 08 FC 01 18 B0 24 65 F2 FF FA 07 F1 06 0A 34 20 60 F4 C0 FC FF 18 50 24 5C F7 02
@209E FF C3 F6 02 0F D5 20 57 F4 C0 FC 30 18 F0 24 53 F7 62 FF C3 F6 04 0F D6 2E 4E F4 2C FC 36 18 F0 24 4A F7 62 FF C3 F6 08 0F D6 2E 45 F4 C3 FC 62 18 F0 24 41 F5 00 FD 80 0D 09 20 3D 2E 3C F4 FF
@209E FF C3 F6 02 0F D5 20 57 F4 C0 FC 30 18 F0 24 53 F7 62 FF C3 F6 04 0F D6 2E 4E F4 2C FC 36 18 F0 24 4A F7 62 FF C3 F6 08 0F D7 2E 45 F4 C3 FC 62 18 F0 24 41 F5 00 FD 80 0D 09 20 3D 2E 3C F4 FF
@20DE FC FF 18 B0 24 38 F5 01 FD 0F 0D 0A 20 34 F4 00 FC 00 18 B0 24 30 F5 FF FD 80 0D FB 22 2C F4 01 FC 00 18 B0 24 28 F2 1A FA FF 0A CC 20 24 F4 00 FC A0 18 50 24 20 F7 8F FF B2 0F 8D 20 1C F4 B2
@211E FC 00 18 F0 24 18 F7 62 FF C3 0F 8E 2E 14 F4 C3 FC 62 18 F0 24 10 F7 62 FF C3 0F CE 2E 0C F4 36 FC 2C 18 F0 24 08 F2 00 FA 80 F3 02 53 40 01 00 01 00 03 00 02 00 F2 04 FA 80 F3 02 53 40 03 00
@211E FC 00 18 F0 24 18 F7 62 FF C3 0F 8E 2E 14 F4 C3 FC 62 18 F0 24 10 F7 62 FF C3 0F CF 2E 0C F4 2C FC 36 18 F0 24 08 F2 00 FA 80 F3 02 53 40 01 00 01 00 03 00 02 00 F2 04 FA 80 F3 02 53 40 03 00
@215E 02 00 F2 00 FA 80 F3 03 53 40 F3 02 53 42 F7 55 FF A5 87 00 24 AA 2E A9 2A A8 F3 00 FB A5 18 EC 24 A4 F7 C5 FF A5 87 80 28 A0 26 9F 2E 9E F3 80 FB A5 18 EC 24 9A F7 55 FF A5 8F 00 24 96 2E 95
@219E 2A 94 F3 55 FB 00 18 EC 24 90 F7 C5 FF A5 8F 80 28 8C 26 8B 2E 8A F3 C5 FB 80 18 EC 24 86 F7 55 FF A5 97 00 24 82 2E 81 2A 80 F7 C5 FF A5 97 80 28 7C 26 7B 2E 7A F7 55 FF A5 9F 00 24 76 2E 75
@21DE 2A 74 F7 C5 FF A5 9F 80 28 70 26 6F 2E 6E F2 0B 02 F9 F7 00 FF A5 A7 00 2A 68 24 67 2E 66 20 65 F3 00 FB A5 18 EC 24 61 F2 06 02 F9 F7 9F FF A5 A7 60 28 5B 26 5A 2E 59 22 58 F3 FF FB A5 18 EC
12,34 → 12,36
@221E 24 54 F2 0B 02 F9 F7 88 FF 00 AF 00 2A 4E 24 4D 2E 4C 20 4B F3 88 FB 00 18 EC 24 47 F2 06 02 F9 F7 36 FF A1 AF 50 28 41 26 40 2E 3F 22 3E F3 36 FB F1 18 EC 24 3A F2 0B 02 F9 F7 C3 FF 96 B7 3C
@225E 2A 34 24 33 2E 32 20 31 F3 00 FB 96 18 EC 24 2D F2 06 02 F9 F6 00 FE A5 B6 73 28 27 26 26 2E 25 22 24 F3 8C FB A5 18 CC 24 20 F2 0B 02 F9 F7 C3 FF 96 BF 69 2A 1A 24 19 2E 18 20 17 F3 C3 FB 00
@229E 18 EC 24 13 F2 06 02 F9 F6 66 FE 66 BE 66 28 0D 26 0C 2E 0B 22 0A F3 66 FB FF 18 CC 24 06 F2 00 FA 80 F3 04 53 40 03 00 02 00 F2 04 FA 80 F3 04 53 40 03 00 02 00 F2 00 FA 80 F3 05 53 40 F3 03
@22DE 53 42 F2 0B 02 F9 F3 00 FB FF 03 F4 2A 82 24 81 2E 80 20 7F F6 00 FE 00 18 CC 24 7B F2 06 02 F9 F6 83 FE 00 06 F4 28 75 26 74 2E 73 22 72 F3 83 FB FF 18 CC 24 6E F2 0A 02 F9 F4 00 FC 00 04 F5
@231E 2A 68 24 67 2E 66 22 65 F6 00 FE 00 18 D0 24 61 F2 0E 02 F9 F6 01 FE 03 06 F5 2A 5B 26 5A 2E 59 20 58 F3 01 FB 03 18 CC 24 54 F2 0A 02 F9 F6 55 FE AA F5 AA FD 55 13 B8 2A 4C 24 4B 2E 4A 22 49
@235E 18 0C 24 47 F7 55 FF AA F2 07 02 F9 14 DC 28 41 26 40 2E 3F 20 3E 18 9C 25 A8 F2 0A 02 F9 F6 00 F5 00 13 BA 2A 36 24 35 2E 34 22 33 18 0C 24 31 F7 55 FF AA F6 8A FE 10 F2 07 02 F9 14 DE 28 29
@239E 26 28 2E 27 20 26 F3 DF FB BA 18 8C 24 22 F2 0A 02 F9 F1 55 F9 AA F5 AA FD 55 13 A7 2A 1A 24 19 2E 18 22 17 18 0C 24 15 F7 CC FF 33 F2 01 FA 40 02 F9 14 EB 28 0E 26 0D 2E 0C 20 0B F3 32 FB 8C
@23DE 18 8C 24 07 F2 00 FA 80 F3 06 53 40 01 00 03 00 02 00 F2 04 FA 80 F3 06 53 40 03 00 02 00 F2 00 FA 80 F3 07 53 40 F3 04 53 42 F2 0E 02 F9 F6 34 F5 A6 FD C3 F4 FF 04 F4 64 BB 2A 54 26 53 2E 52
@241E 22 51 F7 0A 18 F0 24 4E F6 B8 64 BB F7 C3 18 F0 24 49 F2 06 02 F9 F6 34 F5 A6 FD C3 F4 FF 04 F4 6C BB 28 40 26 3F 2E 3E 22 3D F7 6F FF FF 18 F0 24 39 F6 B0 6C BB F7 A6 FF F3 18 F0 24 33 F2 06
@245E 02 F9 F6 3C F5 A6 FD C3 F4 FF 04 F4 74 BB 28 2A 26 29 2E 28 22 27 F7 FF FF 9F 18 F0 24 23 F6 78 74 BB F7 FF FF 59 18 F0 24 1D F2 06 02 F9 F6 38 F5 A6 FD C3 F4 FF FC FA 7C BB 28 14 26 13 2E 12
@249E 22 11 F7 FF FF F3 18 F0 24 0D F6 70 7C BB F7 A6 FF F3 18 F0 24 07 F2 00 FA 80 F3 08 53 40 01 00 03 00 02 00 F2 04 FA 80 F3 08 53 40 03 00 02 00 F2 00 FA 80 F3 09 53 40 F3 05 53 42 F2 00 02 F9
@24DE 20 01 3C 66 F2 01 02 F9 20 63 F2 01 02 F9 22 01 3C 5F F2 00 02 F9 22 5C F2 04 02 F9 26 01 3C 58 F2 00 02 F9 26 55 F2 00 02 F9 24 01 3C 51 F2 04 02 F9 24 4E F2 00 02 F9 28 01 3C 4A F2 08 02 F9
@251E 28 47 F2 08 02 F9 2A 01 3C 43 F2 00 02 F9 2A 40 F2 00 02 F9 2C 01 3C 3C F2 02 02 F9 2C 39 F2 02 02 F9 2E 01 3C 35 F2 00 02 F9 2E 32 F2 01 02 F9 32 01 3C 2E F2 04 02 F9 32 01 3C 2A F2 00 02 F9
@255E 32 27 F2 0A 02 F9 34 01 3C 23 F2 05 02 F9 34 01 3C 1F F2 08 02 F9 34 1C F2 0A 02 F9 30 01 3C 18 F2 0B 02 F9 30 15 F2 0E 02 F9 30 12 F2 0A 02 F9 38 01 3C 0E F2 01 02 F9 38 01 3C 0A F2 0E 02 F9
@259E 38 07 F2 02 02 F9 38 04 F2 08 02 F9 38 01 3C 0C F2 04 FA 80 F3 0A 53 40 03 00 02 00 F2 00 FA 80 F3 0A 53 40 03 00 02 00 3F F9 F2 00 FA 80 F3 0B 53 40 F3 06 53 42 F4 00 05 FA 3C 0C F2 00 FA 80
@25DE F3 0C 53 40 03 00 02 00 F2 04 FA 80 F3 0C 53 40 03 00 02 00 F4 88 FC 99 F7 88 FF 99 18 F0 25 F4 05 F6 F2 00 FA 80 F3 0D 53 40 F3 07 53 42 F4 0F FC 01 F7 0E FF 01 F2 0F 02 F9 19 9C 2A 66 26 65
@261E 2E 64 22 63 F3 01 18 2C 24 60 F7 0F FF 01 F2 0B 02 F9 19 9C 2A 5A 24 59 2E 58 22 57 F4 11 FC 01 F7 0E FF 01 F2 0F 02 F9 19 9D 2A 4F 26 4E 2E 4D 22 4C F3 02 18 2C 24 49 F4 0F FC 01 F7 0F FF 01
@265E F2 0A 02 F9 19 9D 2A 41 26 40 2E 3F 22 3E F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9E 28 36 26 35 2C 34 22 33 F3 10 FB 80 18 2C 24 2F F4 00 FC 80 F7 00 FF 80 F2 0F 02 F9 19 9E 2A 27 24 26 2C 25
@269E 20 24 18 20 24 22 F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9F 28 1A 26 19 2C 18 22 17 F3 11 FB 80 18 2C 24 13 F4 00 FC 80 F7 00 FF 80 F2 0C 02 F9 19 9F 2A 0B 24 0A 2C 09 20 08 18 20 24 06 F2 00
@26DE FA 80 F3 0E 53 40 03 00 02 00 F2 04 FA 80 F3 0E 53 40 03 00 02 00 F2 00 FA 80 F3 0F 53 40 F3 08 53 42 F5 0F F2 0F 02 F9 C5 0E 2A 7F 26 7E 2E 7D 22 7C F3 01 18 AC 24 79 F7 0F F2 0D 02 F9 C7 10
@271E 28 74 26 73 2E 72 20 71 D7 FF DF FF 24 6E F6 11 FE 81 F2 0D 02 F9 CE 70 2A 68 26 67 2C 66 22 65 F3 11 FB 11 18 CC 24 61 F6 00 FE 01 F2 06 02 F9 CE 02 28 5B 26 5A 2E 59 20 58 F5 0F F2 0B 02 F9
@275E D5 0F 2A 53 24 52 2E 51 22 50 F7 0F F2 07 02 F9 D7 10 28 4B 26 4A 2E 49 20 48 F5 00 FD 01 F2 0F 02 F9 DD 00 2A 42 24 41 2E 40 22 3F F2 06 02 F9 DD 02 28 3B 26 3A 2E 39 20 38 F5 0F FD 70 F2 0E
@279E 02 F9 ED A0 2A 32 26 31 2E 30 20 2F F3 0F FB 10 18 AC 24 2B F2 07 02 F9 ED 70 28 27 26 26 2C 25 22 24 F3 0F FB 80 18 AC 24 20 F4 FF FC 70 F2 0E 02 F9 E4 01 2A 1A 26 19 2E 18 20 17 F5 00 FD 71
@27DE 18 94 24 13 F4 8E FC 7F F2 0C 02 F9 E4 81 28 0D 26 0C 2C 0B 20 0A F6 0F FE 80 18 98 24 06 F2 00 FA 80 F3 10 53 40 03 00 02 00 F2 00 FA 80 F3 10 53 44 03 00 02 00 F2 00 FA 80 F3 11 53 40 F3 09
@281E 53 42 F1 AA F9 7F F2 55 FA 6F F3 66 FB 5F F7 FF FF FF 51 00 52 01 53 1F F4 00 45 80 46 81 47 9F D5 AA 24 83 D6 55 24 81 D7 66 24 7F F6 66 18 DC 24 7C 59 04 5A 06 5B 0A F4 00 F5 00 F6 00 F7 00
@285E 4D 84 4E 86 4F 8A 18 34 24 70 18 58 24 6E 18 7C 24 6C F1 CC F9 1F F2 99 FA 2F F4 20 F5 02 F6 07 71 94 72 98 65 94 66 98 D5 CC 24 5F F3 99 18 78 24 5C F1 CC F9 1F F2 99 FA 2F F4 30 F5 02 F6 08
@289E 79 94 7A 98 6D 94 6E 98 18 A4 24 4F 18 C8 24 4D F1 33 F9 1F F2 55 FA 2F F4 40 F5 02 F6 07 71 95 72 99 D5 03 24 42 D6 08 24 40 63 96 67 9A D5 02 24 3C D6 07 24 3A D3 33 24 38 F3 55 18 7C 24 35
@28DE F1 66 F9 1F F2 99 FA 2F F4 50 F5 04 F6 09 71 96 72 9A D5 03 24 2A D6 08 24 28 63 95 67 99 D5 04 24 24 D6 09 24 22 D3 66 24 20 F3 99 18 7C 24 1D F1 AA F9 1F F2 CC FA 2F F4 60 F5 02 F6 08 79 95
@291E 7A 99 D5 04 24 12 D6 0A 24 10 6B 96 6F 9A D5 02 24 0C D6 08 24 0A 18 2C 24 08 18 5C 24 06 F2 00 FA 80 F3 12 53 40 03 00 02 00 F2 04 FA 80 F3 12 53 40 03 00 02 00 F2 00 FA 80 F3 13 53 40 F3 0A
@295E 53 42 F1 05 07 F2 20 0D 01 F3 20 0B 06 F2 22 09 07 F0 01 F1 03 F2 F2 00 FA 80 F3 14 53 40 03 00 02 00 F2 04 FA 80 F3 14 53 40 03 00 02 00 02 F8 07 F7 00 00
@FE04 20 2A 00 7B 21 60 00 7B 22 D4 00 7B 23 FC 00 7B 24 CE 00 7B 25 C8 00 7B 26 00 00 7B 26 F4 00 7B 28 14 00 7B 29 54 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B
@22DE 53 42 F2 0B 02 F9 F3 00 FB FF 03 F4 2A 8A 24 89 2E 88 20 87 F6 00 FE 00 18 CC 24 83 F2 06 02 F9 F6 83 FE 00 06 F4 28 7D 26 7C 2E 7B 22 7A F3 83 FB FF 18 CC 24 76 F2 0A 02 F9 F4 00 FC 00 04 F5
@231E 2A 70 24 6F 2E 6E 22 6D F6 00 FE 00 18 D0 24 69 F2 0E 02 F9 F6 01 FE 03 06 F5 2A 63 26 62 2E 61 20 60 F3 01 FB 03 18 CC 24 5C F2 0A 02 F9 F6 55 FE AA F5 AA FD 55 13 B8 2A 54 24 53 2E 52 22 51
@235E 18 0C 24 4F F7 55 FF AA F2 07 02 F9 14 DC 28 49 26 48 2E 47 20 46 18 9C 25 A8 F2 0A 02 F9 F6 00 F5 00 13 BA 2A 3E 24 3D 2E 3C 22 3B 18 0C 24 39 F7 55 FF AA F6 8A FE 10 F2 07 02 F9 14 DE 28 31
@239E 26 30 2E 2F 20 2E F3 DF FB BA 18 8C 24 2A F2 0A 02 F9 F1 55 F9 AA F5 AA FD 55 13 A7 2A 22 24 21 2E 20 22 1F 18 0C 24 1D F7 CC FF 33 F2 01 FA 40 02 F9 14 EB 28 16 26 15 2E 14 20 13 F3 32 FB 8C
@23DE 18 8C 24 0F 11 02 11 07 01 F9 05 F8 F6 0F FE 00 18 B8 24 07 F2 00 FA 80 F3 06 53 40 01 00 03 00 02 00 F2 04 FA 80 F3 06 53 40 03 00 02 00 F2 00 FA 80 F3 07 53 40 F3 04 53 42 F2 0E 02 F9 F6 34
@241E F5 A6 FD C3 F4 FF 04 F4 64 BB 2A 54 26 53 2E 52 22 51 F7 0A 18 F0 24 4E F6 B8 64 BB F7 C3 18 F0 24 49 F2 06 02 F9 F6 34 F5 A6 FD C3 F4 FF 04 F4 6C BB 28 40 26 3F 2E 3E 22 3D F7 6F FF FF 18 F0
@245E 24 39 F6 B0 6C BB F7 A6 FF F3 18 F0 24 33 F2 06 02 F9 F6 3C F5 A6 FD C3 F4 FF 04 F4 74 BB 28 2A 26 29 2E 28 22 27 F7 FF FF 9F 18 F0 24 23 F6 78 74 BB F7 FF FF 59 18 F0 24 1D F2 06 02 F9 F6 38
@249E F5 A6 FD C3 F4 FF FC FA 7C BB 28 14 26 13 2E 12 22 11 F7 FF FF F3 18 F0 24 0D F6 70 7C BB F7 A6 FF F3 18 F0 24 07 F2 00 FA 80 F3 08 53 40 01 00 03 00 02 00 F2 04 FA 80 F3 08 53 40 03 00 02 00
@24DE F2 00 FA 80 F3 09 53 40 F3 05 53 42 F2 00 02 F9 20 01 3C 86 F2 01 02 F9 20 83 F2 01 02 F9 22 01 3C 7F F2 00 02 F9 22 7C F2 04 02 F9 26 01 3C 78 F2 00 02 F9 26 75 F2 00 02 F9 24 01 3C 71 F2 04
@251E 02 F9 24 6E F2 00 02 F9 28 01 3C 6A F2 08 02 F9 28 67 F2 08 02 F9 2A 01 3C 63 F2 00 02 F9 2A 60 F2 00 02 F9 2C 01 3C 5C F2 02 02 F9 2C 59 F2 02 02 F9 2E 01 3C 55 F2 00 02 F9 2E 52 F2 01 02 F9
@255E 32 01 3C 4E F2 04 02 F9 32 01 3C 4A F2 00 02 F9 32 47 F2 0A 02 F9 34 01 3C 43 F2 05 02 F9 34 01 3C 3F F2 08 02 F9 34 3C F2 08 02 F9 36 01 3C 38 F2 02 02 F9 36 01 3C 34 F2 0A 02 F9 36 31 F2 00
@259E 02 F9 36 2E F2 0A 02 F9 30 01 3C 2A F2 0B 02 F9 30 27 F2 0E 02 F9 30 24 F2 0A 02 F9 38 01 3C 20 F2 01 02 F9 38 01 3C 1C F2 0E 02 F9 38 19 F2 02 02 F9 38 16 F2 08 02 F9 38 13 F2 04 02 F9 3A 01
@25DE 3C 0F F2 02 02 F9 3A 01 3C 0B F2 08 02 F9 3A 01 3C 07 F2 0A 02 F9 3A 04 F2 00 02 F9 3A 01 3C 0C F2 04 FA 80 F3 0A 53 40 03 00 02 00 F2 00 FA 80 F3 0A 53 40 03 00 02 00 3F F9 F2 00 FA 80 F3 0B
@261E 53 40 F3 06 53 42 F4 00 05 FA 3C 0C F2 00 FA 80 F3 0C 53 40 03 00 02 00 F2 04 FA 80 F3 0C 53 40 03 00 02 00 F4 88 FC 99 F7 88 FF 99 18 F0 25 F4 05 F6 F2 00 FA 80 F3 0D 53 40 F3 07 53 42 F4 0F
@265E FC 01 F7 0E FF 01 F2 0F 02 F9 19 9C 2A 66 26 65 2E 64 22 63 F3 01 18 2C 24 60 F7 0F FF 01 F2 0B 02 F9 19 9C 2A 5A 24 59 2E 58 22 57 F4 11 FC 01 F7 0E FF 01 F2 0F 02 F9 19 9D 2A 4F 26 4E 2E 4D
@269E 22 4C F3 02 18 2C 24 49 F4 0F FC 01 F7 0F FF 01 F2 0A 02 F9 19 9D 2A 41 26 40 2E 3F 22 3E F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9E 28 36 26 35 2C 34 22 33 F3 10 FB 80 18 2C 24 2F F4 00 FC 80
@26DE F7 00 FF 80 F2 0F 02 F9 19 9E 2A 27 24 26 2C 25 20 24 18 20 24 22 F4 0F FC 70 F7 01 FF 10 F2 05 02 F9 19 9F 28 1A 26 19 2C 18 22 17 F3 11 FB 80 18 2C 24 13 F4 00 FC 80 F7 00 FF 80 F2 0C 02 F9
@271E 19 9F 2A 0B 24 0A 2C 09 20 08 18 20 24 06 F2 00 FA 80 F3 0E 53 40 03 00 02 00 F2 04 FA 80 F3 0E 53 40 03 00 02 00 F2 00 FA 80 F3 0F 53 40 F3 08 53 42 F5 0F F2 0F 02 F9 C5 0E 2A 7F 26 7E 2E 7D
@275E 22 7C F3 01 18 AC 24 79 F7 0F F2 0D 02 F9 C7 10 28 74 26 73 2E 72 20 71 D7 FF DF FF 24 6E F6 11 FE 81 F2 0D 02 F9 CE 70 2A 68 26 67 2C 66 22 65 F3 11 FB 11 18 CC 24 61 F6 00 FE 01 F2 06 02 F9
@279E CE 02 28 5B 26 5A 2E 59 20 58 F5 0F F2 0B 02 F9 D5 0F 2A 53 24 52 2E 51 22 50 F7 0F F2 07 02 F9 D7 10 28 4B 26 4A 2E 49 20 48 F5 00 FD 01 F2 0F 02 F9 DD 00 2A 42 24 41 2E 40 22 3F F2 06 02 F9
@27DE DD 02 28 3B 26 3A 2E 39 20 38 F5 0F FD 70 F2 0E 02 F9 ED A0 2A 32 26 31 2E 30 20 2F F3 0F FB 10 18 AC 24 2B F2 07 02 F9 ED 70 28 27 26 26 2C 25 22 24 F3 0F FB 80 18 AC 24 20 F4 FF FC 70 F2 0E
@281E 02 F9 E4 01 2A 1A 26 19 2E 18 20 17 F5 00 FD 71 18 94 24 13 F4 8E FC 7F F2 0C 02 F9 E4 81 28 0D 26 0C 2C 0B 20 0A F6 0F FE 80 18 98 24 06 F2 00 FA 80 F3 10 53 40 03 00 02 00 F2 00 FA 80 F3 10
@285E 53 44 03 00 02 00 F2 00 FA 80 F3 11 53 40 F3 09 53 42 F1 AA F9 7F F2 55 FA 6F F3 66 FB 5F F7 FF FF FF 51 00 52 01 53 1F F4 00 45 80 46 81 47 9F D5 AA 24 9A D6 55 24 98 D7 66 24 96 F6 66 18 DC
@289E 24 93 59 04 5A 06 5B 0A F4 00 F5 00 F6 00 F7 00 4D 84 4E 86 4F 8A 18 34 24 87 18 58 24 85 18 7C 24 83 F1 CC F9 1F F2 99 FA 2F F4 20 F5 02 F6 07 71 94 72 98 65 94 66 98 D5 CC 24 76 F3 99 18 78
@28DE 24 73 F1 CC F9 1F F2 99 FA 2F F4 30 F5 02 F6 08 79 94 7A 98 6D 94 6E 98 18 A4 24 66 18 C8 24 64 F1 33 F9 1F F2 55 FA 2F F4 40 F5 02 F6 07 71 95 72 99 D5 03 24 59 D6 08 24 57 63 96 67 9A D5 02
@291E 24 53 D6 07 24 51 D3 33 24 4F F3 55 18 7C 24 4C F1 66 F9 1F F2 99 FA 2F F4 50 F5 04 F6 09 71 96 72 9A D5 03 24 41 D6 08 24 3F 63 95 67 99 D5 04 24 3B D6 09 24 39 D3 66 24 37 F3 99 18 7C 24 34
@295E F1 AA F9 1F F2 CC FA 2F F4 60 F5 02 F6 08 79 95 7A 99 D5 04 24 29 D6 0A 24 27 6B 96 6F 9A D5 02 24 23 D6 08 24 21 18 2C 24 1F 18 5C 24 1D F1 66 F9 99 F2 33 FA 75 F4 80 F5 02 F6 08 79 96 7A 9A
@299E D5 00 24 12 D6 06 24 10 6B 95 6F 99 D5 02 24 0C D6 08 24 0A 18 2C 24 08 18 5C 24 06 F2 00 FA 80 F3 12 53 40 03 00 02 00 F2 04 FA 80 F3 12 53 40 03 00 02 00 F2 00 FA 80 F3 13 53 40 F3 0A 53 42
@29DE F1 05 07 F2 20 0D 01 F3 20 0B 06 F2 22 09 07 F0 01 F1 03 F2 F2 00 FA 80 F3 14 53 40 03 00 02 00 F2 04 FA 80 F3 14 53 40 03 00 02 00 07 F7 00 00
@FE04 20 2A 00 7B 21 60 00 7B 22 D4 00 7B 24 0C 00 7B 24 DE 00 7B 26 18 00 7B 26 50 00 7B 27 44 00 7B 28 64 00 7B 29 D2 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B
@FE44 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B
@FE84 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B 20 1E 00 7B
@FEC4 20 1E 00 7B 20 1E 00 7B
/trunk/bench/verilog/wb_master_model.v
35,18 → 35,7
//// ////
///////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id$
//
// $Date$
// $Revision$
// $Author$
// $Locker$
// $State$
//
// Change History:
//
`include "timescale.v"
 
module wb_master_model #(parameter dwidth = 32,
71,7 → 60,7
// Local Wires
//
 
reg [dwidth -1:0] q;
reg [dwidth-1:0] q;
 
event test_command_start;
event test_command_mid;
85,16 → 74,16
//
 
initial
begin
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
end
begin
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
end
 
 
////////////////////////////////////////////////////////////////////
103,44 → 92,44
//
 
task wb_write;
input delay;
integer delay;
input delay;
integer delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d;
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d;
input [dwidth/8 -1:0] s;
 
begin
-> test_command_start;
// wait initial delay
repeat(delay) @(posedge clk);
begin
-> test_command_start;
// wait initial delay
repeat(delay) @(posedge clk);
 
// assert wishbone signal
#1;
adr = a;
dout = d;
cyc = 1'b1;
stb = 1'b1;
we = 1'b1;
sel = s;
@(posedge clk);
-> test_command_mid;
// assert wishbone signal
#1;
adr = a;
dout = d;
cyc = 1'b1;
stb = 1'b1;
we = 1'b1;
sel = s;
@(posedge clk);
-> test_command_mid;
 
// wait for acknowledge from slave
while(~ack) @(posedge clk);
-> test_command_mid;
// wait for acknowledge from slave
while(~ack) @(posedge clk);
-> test_command_mid;
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
-> test_command_end;
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
-> test_command_end;
end
 
end
endtask
 
////////////////////////////////////////////////////////////////////
149,42 → 138,41
//
 
task wb_read;
input delay;
integer delay;
input delay;
integer delay;
 
input [awidth -1:0] a;
output [dwidth -1:0] d;
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
output [dwidth -1:0] d;
input [dwidth/8 -1:0] s;
 
begin
begin
// wait initial delay
repeat(delay) @(posedge clk);
 
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signals
#1;
adr = a;
dout = {dwidth{1'bx}};
cyc = 1'b1;
stb = 1'b1;
we = 1'b0;
sel = s;
@(posedge clk);
 
// assert wishbone signals
#1;
adr = a;
dout = {dwidth{1'bx}};
cyc = 1'b1;
stb = 1'b1;
we = 1'b0;
sel = s;
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
 
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
d = din; // Grab the data on the posedge of clock
#1; // Delay the clearing (hold time of the control signals
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
end
 
// negate wishbone signals
d = din; // Grab the data on the posedge of clock
#1; // Delay the clearing (hold time of the control signals
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
////////////////////////////////////////////////////////////////////
193,22 → 181,23
//
 
task wb_cmp;
input delay;
integer delay;
input delay;
integer delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
input [dwidth/8 -1:0] s;
 
begin
wb_read (delay, a, q, s);
begin
wb_read (delay, a, q, s);
 
if (d_exp !== q)
begin
-> cmp_error_detect;
$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
end
end
if (d_exp !== q)
begin
-> cmp_error_detect;
$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
end
end
 
endtask
 
endmodule
/trunk/rtl/verilog/xgate_wbs_bus.v
39,9 → 39,9
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_wbs_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter DWIDTH = 16,
parameter WB_RD_DEFAULT = 0, // WISHBONE Read Bus default state
parameter SINGLE_CYCLE = 1'b0)
parameter DWIDTH = 16,
parameter WB_RD_DEFAULT = 0, // WISHBONE Read Bus default state
parameter SINGLE_CYCLE = 1'b0)
(
// Wishbone Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output - Pseudo Register
98,11 → 98,11
 
// registers
reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
reg [5:0] addr_latch; // Capture WISHBONE Address
reg [5:0] addr_latch; // Capture WISHBONE Address
 
reg write_reserv1; // Dummy Reg decode for Reserved address
reg write_reserv2; // Dummy Reg decode for Reserved address
 
reg [DWIDTH-1:0] read_mux_irq; // Psudo register for WISHBONE IRQ read data bus mux
 
// Wires
110,9 → 110,9
wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal)
wire wbs_racc; // WISHBONE Read Access (Clock gating signal)
wire [5:0] address; // Select either direct or latched address
reg [DWIDTH-1:0] read_mux_risc; // Pseudo regester for WISHBONE RISC read data bus mux
 
reg [DWIDTH-1:0] read_mux_risc; // Pseudo regester for WISHBONE RISC read data bus mux
 
//
// module body
//
128,7 → 128,7
assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state;
assign address = SINGLE_CYCLE ? wbs_adr_i : addr_latch;
 
assign wbs_dat_o = read_mux_risc | read_mux_irq;
 
// generate acknowledge output signal, By using register all accesses takes two cycles.
146,41 → 146,41
always @(posedge wbs_clk_i)
if ( module_sel ) // Clock gate for power saving
addr_latch <= wbs_adr_i;
 
// WISHBONE Read Data Mux for RISC status and control registers
always @*
case ({wbs_racc, address}) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
7'b100_0000: read_mux_risc = read_risc_regs[ 15: 0];
7'b100_0001: read_mux_risc = read_risc_regs[ 31: 16];
7'b100_0010: read_mux_risc = read_risc_regs[ 47: 32];
7'b100_0011: read_mux_risc = read_risc_regs[ 63: 48];
7'b100_0100: read_mux_risc = read_risc_regs[ 79: 64];
7'b100_0101: read_mux_risc = read_risc_regs[ 95: 80];
7'b100_0110: read_mux_risc = read_risc_regs[111: 96];
7'b100_0111: read_mux_risc = read_risc_regs[127:112];
7'b100_1000: read_mux_risc = read_risc_regs[143:128];
7'b100_1001: read_mux_risc = read_risc_regs[159:144];
7'b100_1010: read_mux_risc = read_risc_regs[175:160];
7'b100_1011: read_mux_risc = read_risc_regs[191:176];
7'b100_1100: read_mux_risc = read_risc_regs[207:192];
7'b100_1101: read_mux_risc = read_risc_regs[223:208];
7'b100_1110: read_mux_risc = read_risc_regs[239:224];
7'b100_1111: read_mux_risc = read_risc_regs[255:240];
7'b101_0000: read_mux_risc = read_risc_regs[271:256];
7'b101_0001: read_mux_risc = read_risc_regs[287:272];
7'b101_0010: read_mux_risc = read_risc_regs[303:288];
7'b101_0011: read_mux_risc = read_risc_regs[319:304];
7'b101_0100: read_mux_risc = read_risc_regs[335:320];
7'b101_0101: read_mux_risc = read_risc_regs[351:336];
7'b101_0110: read_mux_risc = read_risc_regs[367:352];
7'b101_0111: read_mux_risc = read_risc_regs[383:368];
7'b101_1000: read_mux_risc = read_risc_regs[399:384];
7'b101_1001: read_mux_risc = read_risc_regs[415:400];
default: read_mux_risc = {DWIDTH{WB_RD_DEFAULT}};
// 16 bit Bus, 16 bit Granularity
7'b100_0000: read_mux_risc = read_risc_regs[ 15: 0];
7'b100_0001: read_mux_risc = read_risc_regs[ 31: 16];
7'b100_0010: read_mux_risc = read_risc_regs[ 47: 32];
7'b100_0011: read_mux_risc = read_risc_regs[ 63: 48];
7'b100_0100: read_mux_risc = read_risc_regs[ 79: 64];
7'b100_0101: read_mux_risc = read_risc_regs[ 95: 80];
7'b100_0110: read_mux_risc = read_risc_regs[111: 96];
7'b100_0111: read_mux_risc = read_risc_regs[127:112];
7'b100_1000: read_mux_risc = read_risc_regs[143:128];
7'b100_1001: read_mux_risc = read_risc_regs[159:144];
7'b100_1010: read_mux_risc = read_risc_regs[175:160];
7'b100_1011: read_mux_risc = read_risc_regs[191:176];
7'b100_1100: read_mux_risc = read_risc_regs[207:192];
7'b100_1101: read_mux_risc = read_risc_regs[223:208];
7'b100_1110: read_mux_risc = read_risc_regs[239:224];
7'b100_1111: read_mux_risc = read_risc_regs[255:240];
7'b101_0000: read_mux_risc = read_risc_regs[271:256];
7'b101_0001: read_mux_risc = read_risc_regs[287:272];
7'b101_0010: read_mux_risc = read_risc_regs[303:288];
7'b101_0011: read_mux_risc = read_risc_regs[319:304];
7'b101_0100: read_mux_risc = read_risc_regs[335:320];
7'b101_0101: read_mux_risc = read_risc_regs[351:336];
7'b101_0110: read_mux_risc = read_risc_regs[367:352];
7'b101_0111: read_mux_risc = read_risc_regs[383:368];
7'b101_1000: read_mux_risc = read_risc_regs[399:384];
7'b101_1001: read_mux_risc = read_risc_regs[415:400];
default: read_mux_risc = {DWIDTH{WB_RD_DEFAULT}};
endcase
 
// generate wishbone write register strobes for Xgate RISC
// generate wishbone write register strobes for Xgate RISC
always @*
begin
write_reserv1 = 1'b0;
210,51 → 210,51
write_xgr2 = 2'b00;
write_xgr1 = 2'b00;
if (wbs_wacc)
case (address) // synopsys parallel_case
case (address) // synopsys parallel_case
// 16 bit Bus, 8 bit Granularity
6'b00_0000 : write_xgmctl = &wbs_sel_i;
6'b00_0001 : write_xgchid = wbs_sel_i[0];
6'b00_0010 : write_xgisp74 = 1'b1;
6'b00_0011 : write_xgisp30 = 1'b1;
6'b00_0100 : write_xgvbr = wbs_sel_i;
6'b00_0101 : write_xgif_7 = wbs_sel_i;
6'b00_0110 : write_xgif_6 = wbs_sel_i;
6'b00_0111 : write_xgif_5 = wbs_sel_i;
6'b00_1000 : write_xgif_4 = wbs_sel_i;
6'b00_1001 : write_xgif_3 = wbs_sel_i;
6'b00_1010 : write_xgif_2 = wbs_sel_i;
6'b00_1011 : write_xgif_1 = wbs_sel_i;
6'b00_1100 : write_xgif_0 = wbs_sel_i;
6'b00_1101 : write_xgswt = &wbs_sel_i;
6'b00_1110 : write_xgsem = &wbs_sel_i;
6'b00_1111 : write_reserv1 = 1'b1;
6'b01_0000 : write_xgccr = wbs_sel_i[0];
6'b01_0001 : write_xgpc = wbs_sel_i;
6'b01_0010 : write_reserv2 = 1'b1;
6'b01_0011 : write_xgr1 = wbs_sel_i;
6'b01_0100 : write_xgr2 = wbs_sel_i;
6'b01_0101 : write_xgr3 = wbs_sel_i;
6'b01_0110 : write_xgr4 = wbs_sel_i;
6'b01_0111 : write_xgr5 = wbs_sel_i;
6'b01_1000 : write_xgr6 = wbs_sel_i;
6'b01_1001 : write_xgr7 = wbs_sel_i;
default: ;
endcase
6'b00_0000 : write_xgmctl = &wbs_sel_i;
6'b00_0001 : write_xgchid = wbs_sel_i[0];
6'b00_0010 : write_xgisp74 = 1'b1;
6'b00_0011 : write_xgisp30 = 1'b1;
6'b00_0100 : write_xgvbr = wbs_sel_i;
6'b00_0101 : write_xgif_7 = wbs_sel_i;
6'b00_0110 : write_xgif_6 = wbs_sel_i;
6'b00_0111 : write_xgif_5 = wbs_sel_i;
6'b00_1000 : write_xgif_4 = wbs_sel_i;
6'b00_1001 : write_xgif_3 = wbs_sel_i;
6'b00_1010 : write_xgif_2 = wbs_sel_i;
6'b00_1011 : write_xgif_1 = wbs_sel_i;
6'b00_1100 : write_xgif_0 = wbs_sel_i;
6'b00_1101 : write_xgswt = &wbs_sel_i;
6'b00_1110 : write_xgsem = &wbs_sel_i;
6'b00_1111 : write_reserv1 = 1'b1;
6'b01_0000 : write_xgccr = wbs_sel_i[0];
6'b01_0001 : write_xgpc = wbs_sel_i;
6'b01_0010 : write_reserv2 = 1'b1;
6'b01_0011 : write_xgr1 = wbs_sel_i;
6'b01_0100 : write_xgr2 = wbs_sel_i;
6'b01_0101 : write_xgr3 = wbs_sel_i;
6'b01_0110 : write_xgr4 = wbs_sel_i;
6'b01_0111 : write_xgr5 = wbs_sel_i;
6'b01_1000 : write_xgr6 = wbs_sel_i;
6'b01_1001 : write_xgr7 = wbs_sel_i;
default: ;
endcase
end
 
// WISHBONE Read Data Mux for IRQ control registers
always @*
case ({wbs_racc, address}) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
7'b110_0000: read_mux_irq = {irq_bypass[ 15: 1], 1'b0};
7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
7'b110_0110: read_mux_irq = irq_bypass[111: 96];
7'b110_0111: read_mux_irq = irq_bypass[127:112];
default: read_mux_irq = {DWIDTH{WB_RD_DEFAULT}};
// 16 bit Bus, 16 bit Granularity
7'b110_0000: read_mux_irq = {irq_bypass[ 15: 1], 1'b0};
7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
7'b110_0110: read_mux_irq = irq_bypass[111: 96];
7'b110_0111: read_mux_irq = irq_bypass[127:112];
default: read_mux_irq = {DWIDTH{WB_RD_DEFAULT}};
endcase
 
// generate wishbone write register strobes for interrupt control
269,18 → 269,18
write_irw_en_1 = 2'b00;
write_irw_en_0 = 2'b00;
if (wbs_wacc)
case (address) // synopsys parallel_case
case (address) // synopsys parallel_case
// 16 bit Bus, 8 bit Granularity
6'b10_0000 : write_irw_en_0 = wbs_sel_i;
6'b10_0001 : write_irw_en_1 = wbs_sel_i;
6'b10_0010 : write_irw_en_2 = wbs_sel_i;
6'b10_0011 : write_irw_en_3 = wbs_sel_i;
6'b10_0100 : write_irw_en_4 = wbs_sel_i;
6'b10_0101 : write_irw_en_5 = wbs_sel_i;
6'b10_0110 : write_irw_en_6 = wbs_sel_i;
6'b10_0111 : write_irw_en_7 = wbs_sel_i;
default: ;
endcase
6'b10_0000 : write_irw_en_0 = wbs_sel_i;
6'b10_0001 : write_irw_en_1 = wbs_sel_i;
6'b10_0010 : write_irw_en_2 = wbs_sel_i;
6'b10_0011 : write_irw_en_3 = wbs_sel_i;
6'b10_0100 : write_irw_en_4 = wbs_sel_i;
6'b10_0101 : write_irw_en_5 = wbs_sel_i;
6'b10_0110 : write_irw_en_6 = wbs_sel_i;
6'b10_0111 : write_irw_en_7 = wbs_sel_i;
default: ;
endcase
end
 
endmodule // xgate_wbs_bus
/trunk/rtl/verilog/xgate_wbm_bus.v
39,7 → 39,7
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_wbm_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter DWIDTH = 16,
parameter DWIDTH = 16,
parameter SINGLE_CYCLE = 1'b0)
(
// Wishbone Signals
63,7 → 63,7
input single_step, // Pulse to trigger a single instruction execution in debug mode
output ss_mem_ack, // WISHBONE Bus has granted single step memory access
input [15:0] xgate_address, // Address to system memory
input mem_access, //
input mem_access, //
input write_mem_strb_l, // Strobe for writing low data byte
input write_mem_strb_h, // Strobe for writing high data bye
input [DWIDTH-1:0] write_mem_data // Data to system memory
77,7 → 77,7
//
// Module body
//
 
// Latch Single Step Request and ask for memory access
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
84,22 → 84,22
ss_mem_req <= 1'b0;
else
ss_mem_req <= (single_step || ss_mem_req) && !wbm_ack_i && xge;
 
assign ss_mem_ack = ss_mem_req && wbm_ack_i;
 
 
assign wbm_dat_o = write_mem_data;
assign read_mem_data = wbm_dat_i;
assign wbm_adr_o = xgate_address;
 
assign mem_req_ack = wbm_ack_i;
 
assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
 
assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
 
assign wbm_cyc_o = xge && (mem_access || ss_mem_req);
 
assign wbm_stb_o = xge && (mem_access || ss_mem_req);
 
endmodule // xgate_wbm_bus
/trunk/rtl/verilog/xgate_regs.v
230,47 → 230,47
begin
k = 1; // WISHBONE Bus bit counter [15:0]
for (j = 1; j <= 127; j = j + 1)
begin
if (j <= MAX_CHANNEL)
begin
if ((j >= 0) && (j < 8))
irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 8) && (j < 16))
irq_bypass_d[j] = write_irw_en_0[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 16) && (j < 24))
irq_bypass_d[j] = write_irw_en_1[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 24) && (j < 32))
irq_bypass_d[j] = write_irw_en_1[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 32) && (j < 40))
irq_bypass_d[j] = write_irw_en_2[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 40) && (j < 48))
irq_bypass_d[j] = write_irw_en_2[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 48) && (j < 56))
irq_bypass_d[j] = write_irw_en_3[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 56) && (j < 64))
irq_bypass_d[j] = write_irw_en_3[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 64) && (j < 72))
irq_bypass_d[j] = write_irw_en_4[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 72) && (j < 80))
irq_bypass_d[j] = write_irw_en_4[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 80) && (j < 88))
irq_bypass_d[j] = write_irw_en_5[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 88) && (j < 96))
irq_bypass_d[j] = write_irw_en_5[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 96) && (j < 104))
irq_bypass_d[j] = write_irw_en_6[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 104) && (j < 112))
irq_bypass_d[j] = write_irw_en_6[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 112) && (j < 120))
irq_bypass_d[j] = write_irw_en_7[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 120) && (j < 128))
irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j];
end
else
irq_bypass_d[j] = 1'b0;
k = k + 1;
if (k > 15)
k = 0;
begin
if (j <= MAX_CHANNEL)
begin
if ((j >= 0) && (j < 8))
irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 8) && (j < 16))
irq_bypass_d[j] = write_irw_en_0[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 16) && (j < 24))
irq_bypass_d[j] = write_irw_en_1[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 24) && (j < 32))
irq_bypass_d[j] = write_irw_en_1[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 32) && (j < 40))
irq_bypass_d[j] = write_irw_en_2[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 40) && (j < 48))
irq_bypass_d[j] = write_irw_en_2[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 48) && (j < 56))
irq_bypass_d[j] = write_irw_en_3[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 56) && (j < 64))
irq_bypass_d[j] = write_irw_en_3[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 64) && (j < 72))
irq_bypass_d[j] = write_irw_en_4[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 72) && (j < 80))
irq_bypass_d[j] = write_irw_en_4[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 80) && (j < 88))
irq_bypass_d[j] = write_irw_en_5[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 88) && (j < 96))
irq_bypass_d[j] = write_irw_en_5[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 96) && (j < 104))
irq_bypass_d[j] = write_irw_en_6[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 104) && (j < 112))
irq_bypass_d[j] = write_irw_en_6[1] ? write_bus[k] : irq_bypass[j];
if ((j >= 112) && (j < 120))
irq_bypass_d[j] = write_irw_en_7[0] ? write_bus[k] : irq_bypass[j];
if ((j >= 120) && (j < 128))
irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j];
end
else
irq_bypass_d[j] = 1'b0;
k = k + 1;
if (k > 15)
k = 0;
end
end
 
283,7 → 283,7
irq_bypass <= irq_bypass_d;
 
// Alias the register name to the output pin name so only the used bit are carried out
assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
 
endmodule // xgate_regs
 
/trunk/rtl/verilog/xgate_risc.v
49,7 → 49,7
output reg [15:0] xgr7,
output [15:0] xgate_address,
output [15:0] write_mem_data, // Data for Memory write
output mem_access, //
output mem_access, //
output write_mem_strb_l, // Strobe for writing low data byte
output write_mem_strb_h, // Strobe for writing high data bye
output reg zero_flag,
205,7 → 205,7
reg debug_edge; // Reg for edge detection
 
reg cmd_dbg;
 
reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
reg [ 1:0] chid_sm; //
wire chid_goto_idle; //
215,13 → 215,13
CHID_TEST = 2'b10,
CHID_WAIT = 2'b11;
 
 
assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};
assign bra_offset = {{5{op_code[9]}}, op_code[9:0], 1'b0};
assign pc_sum = program_counter + pc_incr_mux;
 
assign xgate_address = data_access ? data_address : program_counter;
 
//assign mem_access = data_access || load_next_inst || start_thread;
assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
(cpu_state == BREAK_2) || start_thread;
326,9 → 326,9
else
begin
cmd_dbg <= !((cpu_state == LD_INST) || (cpu_state == DEBUG)) &&
(cmd_dbg || (xgdbg_set && mem_req_ack && (next_cpu_state == CONT)));
(cmd_dbg || (xgdbg_set && mem_req_ack && (next_cpu_state == CONT)));
end
 
// Latch the debug state, set by eather xgdb or BRK instructions
always @(posedge risc_clk or negedge async_rst_b)
if ( !async_rst_b )
342,7 → 342,7
brk_set_dbg || op_code_error || debug_active);
debug_edge <= debug_active;
end
 
assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
 
// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
390,7 → 390,7
CHID_IDLE:
if ( write_xgchid && debug_active )
chid_sm_ns = CHID_TEST;
else
else
chid_sm_ns = CHID_IDLE;
CHID_TEST:
if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
404,7 → 404,7
chid_sm_ns = CHID_WAIT;
default : chid_sm_ns = CHID_IDLE;
endcase
 
assign chid_goto_idle = (chid_sm == CHID_WAIT);
 
// CPU Read Data Buffer Register
459,21 → 459,21
j = j + 1;
end
if (clear_xgif_0)
xgif_d[15: 1] = ~clear_xgif_data & xgif_status[15: 1];
xgif_d[15: 1] = ~clear_xgif_data & xgif_status[15: 1];
if (clear_xgif_1)
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
if (clear_xgif_2)
xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
if (clear_xgif_3)
xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48];
xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48];
if (clear_xgif_4)
xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64];
xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64];
if (clear_xgif_5)
xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80];
xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80];
if (clear_xgif_6)
xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96];
xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96];
if (clear_xgif_7)
xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
end
 
// Interrupt Flag Registers
498,53 → 498,53
end
else
begin
xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
{(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
{(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
(write_xgr1[0] ? perif_data[ 7:0]: xgr1[ 7:0])} :
{((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
((wrt_sel_xgr1 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr1[ 7:0])};
xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
{(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
{(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
(write_xgr2[0] ? perif_data[ 7:0]: xgr2[ 7:0])} :
{((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
((wrt_sel_xgr2 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr2[ 7:0])};
xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
{(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
{(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
(write_xgr3[0] ? perif_data[ 7:0]: xgr3[ 7:0])} :
{((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
((wrt_sel_xgr3 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr3[ 7:0])};
xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
{(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
{(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
(write_xgr4[0] ? perif_data[ 7:0]: xgr4[ 7:0])} :
{((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
((wrt_sel_xgr4 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr4[ 7:0])};
xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
{(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
{(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
(write_xgr5[0] ? perif_data[ 7:0]: xgr5[ 7:0])} :
{((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
((wrt_sel_xgr5 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr5[ 7:0])};
xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
{(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
{(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
(write_xgr6[0] ? perif_data[ 7:0]: xgr6[ 7:0])} :
{((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
((wrt_sel_xgr6 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr6[ 7:0])};
xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
{(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
{(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
(write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
end
 
 
 
 
 
 
 
 
 
// V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
// P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
// r - 8-bit data read: lasts for at least one RISC core cycle
// R - 16-bit data read: lasts for at least one RISC core cycle
// w - 8-bit data write: lasts for at least one RISC core cycle
// W - 16-bit data write: lasts for at least one RISC core cycle
// A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
// f - Free cycle: no read or write, lasts for one RISC core cycles
// Special Cases
 
// PP/P - Branch: PP if branch taken, P if not taken
 
always @*
begin
579,9 → 579,9
 
set_irq_flag = 7'b0;
 
set_semaph = 1'b0;
clear_semaph = 1'b0;
semaph_risc = 3'b0;
set_semaph = 1'b0;
clear_semaph = 1'b0;
semaph_risc = 3'b0;
 
casez ({cpu_state, op_code})
 
595,12 → 595,12
 
{CHG_CHID, 16'b????????????????} :
begin
if (!xge)
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
else if (ss_mem_ack || !debug_active)
next_cpu_state = BOOT_1;
else
next_cpu_state = CHG_CHID;
else
next_cpu_state = CHG_CHID;
 
pc_incr_mux = 16'h0000;
next_pc = pc_sum;
644,14 → 644,14
 
{BREAK, 16'b????????????????} :
begin
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = BREAK_2;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = BREAK;
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = BREAK_2;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = BREAK;
load_next_inst = 1'b0;
pc_incr_mux = 16'h0000;
next_pc = pc_sum;
672,16 → 672,16
 
{DEBUG, 16'b????????????????} :
begin
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = CONT;
else if (cmd_change_pc)
next_cpu_state = LD_INST;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = DEBUG;
if (!xge)
next_cpu_state = IDLE;
else if (ss_mem_ack || !debug_active)
next_cpu_state = CONT;
else if (cmd_change_pc)
next_cpu_state = LD_INST;
else if (chid_goto_idle)
next_cpu_state = CHG_CHID;
else
next_cpu_state = DEBUG;
 
load_next_inst = cmd_change_pc;
pc_incr_mux = 16'h0000;
784,7 → 784,7
set_semaph = 1'b1;
semaph_risc = op_code[10:8];
 
next_carry = semaph_stat;
next_carry = semaph_stat;
end
 
// Instruction = SSEM RS, Op Code = 0 0 0 0 0 RS 1 1 1 1 0 0 1 1
798,7 → 798,7
set_semaph = 1'b1;
semaph_risc = rd_data[2:0];
 
next_carry = semaph_stat;
next_carry = semaph_stat;
end
 
// -----------------------------------------------------------------------
850,9 → 850,7
// contained in RS[6:0] is set. The content of RS[15:7] is ignored
// Cycles - P
{CONT, 16'b00000???11110111} :
begin
set_irq_flag = rd_data[6:0];
end
set_irq_flag = rd_data[6:0];
 
// -----------------------------------------------------------------------
// Instruction Group -- Special Move instructions
1309,15 → 1307,13
// If C = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010000?????????} :
begin
if (!carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum; // There is a race condition when the default declaration is used
end
end
if (!carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum; // There is a race condition when the default declaration is used
end
 
// Instruction = BCS REL9, Op Code = 0 0 1 0 0 0 1 REL9
// Branch if Carry Set
1324,15 → 1320,13
// If C = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010001?????????} :
begin
if (carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (carry_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BNE REL9, Op Code = 0 0 1 0 0 1 0 REL9
// Branch if Not Equal
1339,15 → 1333,13
// If Z = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010010?????????} :
begin
if (!zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BEQ REL9, Op Code = 0 0 1 0 0 1 1 REL9
// Branch if Equal
1354,15 → 1346,13
// If Z = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010011?????????} :
begin
if (zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BPL REL9, Op Code = 0 0 1 0 1 0 0 REL9
// Branch if Plus
1369,15 → 1359,13
// If N = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010100?????????} :
begin
if (!negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BMI REL9, Op Code = 0 0 1 0 1 0 1 REL9
// Branch if Minus
1384,15 → 1372,13
// If N = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010101?????????} :
begin
if (negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (negative_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BVC REL9, Op Code = 0 0 1 0 1 1 0 REL9
// Branch if Overflow Cleared
1399,15 → 1385,13
// If V = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010110?????????} :
begin
if (!overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BVS REL9, Op Code = 0 0 1 0 1 1 1 REL9
// Branch if Overflow Set
1414,15 → 1398,13
// If V = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0010111?????????} :
begin
if (overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BHI REL9, Op Code = 0 0 1 1 0 0 0 REL9
// Branch if Higher
1429,15 → 1411,13
// If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011000?????????} :
begin
if (!(carry_flag || zero_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!(carry_flag || zero_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BLS REL9, Op Code = 0 0 1 1 0 0 1 REL9
// Branch if Lower or Same
1444,15 → 1424,13
// If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011001?????????} :
begin
if (carry_flag || zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (carry_flag || zero_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BGE REL9, Op Code = 0 0 1 1 0 1 0 REL9
// Branch if Greater than or Equal to Zero
1459,15 → 1437,13
// If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011010?????????} :
begin
if (!(negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!(negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BLT REL9, Op Code = 0 0 1 1 0 1 1 REL9
// Branch if Lower than Zero
1474,15 → 1450,13
// If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011011?????????} :
begin
if (negative_flag ^ overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (negative_flag ^ overflow_flag)
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BGT REL9, Op Code = 0 0 1 1 1 0 0 REL9
// Branch if Greater than Zero
1489,15 → 1463,13
// If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011100?????????} :
begin
if (!(zero_flag || (negative_flag ^ overflow_flag)))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (!(zero_flag || (negative_flag ^ overflow_flag)))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BLE REL9, Op Code = 0 0 1 1 1 0 1 REL9
// Branch if Less or Equal to Zero
1504,15 → 1476,13
// If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
// Cycles - PP/P
{CONT, 16'b0011101?????????} :
begin
if (zero_flag || (negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
end
if (zero_flag || (negative_flag ^ overflow_flag))
begin
next_cpu_state = S_STALL;
load_next_inst = 1'b0;
pc_incr_mux = jump_offset;
next_pc = pc_sum;
end
 
// Instruction = BRA REL10, Op Code = 0 0 1 1 1 1 REL10
// Branch Always, signed offset
2126,9 → 2096,9
end
default :
begin
// synopsys translate_off
// synopsys translate_off
$display("\nOP Code Error\n");
// synopsys translate_on
// synopsys translate_on
next_cpu_state = DEBUG;
pc_incr_mux = 16'h0000;
next_pc = pc_sum;
2136,7 → 2106,7
op_code_error = 1'b1;
end
endcase
 
end // always
 
xgate_barrel_shift barrel_shift(
2170,20 → 2140,20
generate
for (sem_gen_count = 0; sem_gen_count < 8; sem_gen_count = sem_gen_count + 1)
begin:semaphore_
semaphore_bit bit(
// outputs
.host_status( host_semap[sem_gen_count] ),
.risc_status( risc_semap[sem_gen_count] ),
// inputs
.risc_clk( risc_clk ),
.async_rst_b( async_rst_b ),
.risc_bit_sel( semap_risc_bit[sem_gen_count] ),
.csem( clear_semaph ),
.ssem( set_semaph ),
.host_wrt( write_xgsem ),
.host_bit_mask( perif_data[sem_gen_count+8] ),
.host_bit( perif_data[sem_gen_count] )
);
semaphore_bit sbit(
// outputs
.host_status( host_semap[sem_gen_count] ),
.risc_status( risc_semap[sem_gen_count] ),
// inputs
.risc_clk( risc_clk ),
.async_rst_b( async_rst_b ),
.risc_bit_sel( semap_risc_bit[sem_gen_count] ),
.csem( clear_semaph ),
.ssem( set_semaph ),
.host_wrt( write_xgsem ),
.host_bit_mask( perif_data[sem_gen_count+8] ),
.host_bit( perif_data[sem_gen_count] )
);
end
endgenerate
 
/trunk/rtl/verilog/xgate_top.v
39,9 → 39,10
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter SINGLE_CYCLE = 1'b0, //
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
parameter DWIDTH = 16, // define the wishbone bus data size
parameter SINGLE_CYCLE = 1'b0, //
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
(
// Wishbone Slave Signals
output [DWIDTH-1:0] wbs_dat_o, // databus output
76,7 → 77,6
input scantestmode // Chip in in scan test mode
);
 
parameter DWIDTH = 16; // Data bus width
 
wire zero_flag;
wire negative_flag;
147,7 → 147,7
 
wire [15:1] xgvbr; // XGATE vector Base Address Register
wire brk_irq_ena; // Enable BRK instruction to generate interrupt
 
wire [15:0] xgate_address; //
wire [15:0] write_mem_data; //
wire [15:0] read_mem_data; //
154,20 → 154,20
wire mem_access; //
wire mem_req_ack; //
 
wire debug_active; // RISC state machine in Debug mode
wire debug_active; // RISC state machine in Debug mode
wire debug_ack; // Clear debug register
wire single_step; // Pulse to trigger a single instruction execution in debug mode
wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
 
wire [ 7:0] host_semap; // Semaphore status for host
wire write_mem_strb_l; // Strobe for writing low data byte
wire write_mem_strb_h; // Strobe for writing high data bye
 
// ---------------------------------------------------------------------------
// Wishbone Slave Bus interface
xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
.SINGLE_CYCLE(SINGLE_CYCLE),
.WB_RD_DEFAULT(WB_RD_DEFAULT))
.WB_RD_DEFAULT(WB_RD_DEFAULT))
wishbone_s(
.wbs_dat_o( wbs_dat_o ),
.wbs_ack_o( wbs_ack_o ),
181,7 → 181,7
.wbs_stb_i( wbs_stb_i ),
.wbs_cyc_i( wbs_cyc_i ),
.wbs_sel_i( wbs_sel_i ),
 
// outputs
.sync_reset( sync_reset ),
.write_xgmctl( write_xgmctl ),
214,37 → 214,37
.write_irw_en_2( write_irw_en_2 ),
.write_irw_en_1( write_irw_en_1 ),
.write_irw_en_0( write_irw_en_0 ),
// inputs
// inputs
.async_rst_b( async_rst_b ),
.read_risc_regs( // in -- read register bits
{ xgr7, // XGR7
xgr6, // XGR6
xgr5, // XGR5
xgr4, // XGR4
xgr3, // XGR3
xgr2, // XGR2
xgr1, // XGR1
16'b0, // Reserved (XGR0)
xgate_address, // XGPC
{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
16'b0, // Reserved
{8'h00, host_semap}, // XGSEM
{8'h00, xgswt}, // XGSWT
{xgif_status[ 15: 1], 1'b0}, // XGIF_0
xgif_status[ 31: 16], // XGIF_1
xgif_status[ 47: 32], // XGIF_2
xgif_status[ 63: 48], // XGIF_3
xgif_status[ 79: 64], // XGIF_4
xgif_status[ 95: 80], // XGIF_5
xgif_status[111: 96], // XGIF_6
xgif_status[127:112], // XGIF_7
{xgvbr[15:1], 1'b0}, // XGVBR
16'b0, // Reserved
16'b0, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
}
),
{ xgr7, // XGR7
xgr6, // XGR6
xgr5, // XGR5
xgr4, // XGR4
xgr3, // XGR3
xgr2, // XGR2
xgr1, // XGR1
16'b0, // Reserved (XGR0)
xgate_address, // XGPC
{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
16'b0, // Reserved
{8'h00, host_semap}, // XGSEM
{8'h00, xgswt}, // XGSWT
{xgif_status[ 15: 1], 1'b0}, // XGIF_0
xgif_status[ 31: 16], // XGIF_1
xgif_status[ 47: 32], // XGIF_2
xgif_status[ 63: 48], // XGIF_3
xgif_status[ 79: 64], // XGIF_4
xgif_status[ 95: 80], // XGIF_5
xgif_status[111: 96], // XGIF_6
xgif_status[127:112], // XGIF_7
{xgvbr[15:1], 1'b0}, // XGVBR
16'b0, // Reserved
16'b0, // Reserved
{8'b0, 1'b0, xgchid}, // XGCHID
{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
}
),
.irq_bypass( irq_bypass )
 
);
331,7 → 331,7
.xg_sw_irq( xg_sw_irq ),
.mem_access( mem_access ),
.single_step( single_step ),
 
// inputs
.risc_clk( risc_clk ),
.perif_data( wbs_dat_i ),
371,7 → 371,7
.clear_xgif_data( clear_xgif_data )
);
 
xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
irq_encode(
// outputs
.xgif( xgif ),
/trunk/sim/verilog/run/run_iverilog
18,6 → 18,7
$xgate/rtl/verilog/xgate_regs.v \
$xgate/rtl/verilog/xgate_risc.v \
$xgate/rtl/verilog/xgate_irq_encode.v \
$xgate/rtl/verilog/xgate_jtag.v \
\
$bench/verilog/wb_master_model.v \
$bench/verilog/ram.v \
/trunk/sw/xgate_test_code/irq_test/irq_test.s
3,183 → 3,183
; Bob Hayes - May 11 2010
 
 
CPU XGATE
CPU XGATE
 
ORG $fe00
DS.W 2 ; reserve two words at channel 0
; channel 1
DC.W _IRQ1 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 2
DC.W _IRQ2 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 3
DC.W _IRQ3 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 4
DC.W _IRQ4 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 5
DC.W _IRQ5 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 6
DC.W _IRQ6 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 7
DC.W _IRQ7 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 8
DC.W _IRQ8 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 9
DC.W _IRQ9 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 10
DC.W _IRQ10 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 11
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 12
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 13
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 14
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 15
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 16
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 17
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 18
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 19
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 20
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 21
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 22
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 23
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 24
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 25
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 26
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 27
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 28
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 29
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 30
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 31
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 32
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 33
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 34
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 35
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 36
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 37
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 38
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 39
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 40
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 41
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 42
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 43
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 44
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 45
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 46
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 47
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 48
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 49
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 50
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
ORG $fe00
DS.W 2 ; reserve two words at channel 0
; channel 1
DC.W _IRQ1 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 2
DC.W _IRQ2 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 3
DC.W _IRQ3 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 4
DC.W _IRQ4 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 5
DC.W _IRQ5 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 6
DC.W _IRQ6 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 7
DC.W _IRQ7 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 8
DC.W _IRQ8 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 9
DC.W _IRQ9 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 10
DC.W _IRQ10 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 11
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 12
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 13
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 14
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 15
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 16
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 17
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 18
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 19
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 20
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 21
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 22
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 23
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 24
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 25
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 26
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 27
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 28
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 29
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 30
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 31
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 32
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 33
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 34
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 35
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 36
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 37
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 38
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 39
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 40
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 41
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 42
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 43
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 44
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 45
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 46
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 47
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 48
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 49
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 50
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
 
ORG $2000 ; with comment
ORG $2000 ; with comment
 
V_PTR EQU 123
V_PTR EQU 123
 
DC.W END_CODE_
DS.W 8
DC.B $56
DS.B 11
DC.W END_CODE_
DS.W 8
DC.B $56
DS.B 11
 
ALIGN 1
ALIGN 1
 
;-------------------------------------------------------------------------------
; Place where undefined interrupts go
;-------------------------------------------------------------------------------
_ERROR
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$ff
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$ff
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
186,24 → 186,24
; Test IRQ
;-------------------------------------------------------------------------------
_IRQ1
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address
LDL R3,#1 ; Checkpoint Value
STB R3,(R2,#0) ; Send Checkpoint value
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address
LDL R3,#1 ; Checkpoint Value
STB R3,(R2,#0) ; Send Checkpoint value
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_1
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_1
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_1
 
_END_1
LDL R3,#101
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#101
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
210,24 → 210,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ2
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address
LDL R3,#2 ; Checkpoint Value
STB R3,(R2,#0) ; Send Checkpoint value
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address
LDL R3,#2 ; Checkpoint Value
STB R3,(R2,#0) ; Send Checkpoint value
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_2
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_2
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_2
 
_END_2
LDL R3,#102
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#102
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
234,24 → 234,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ3
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address
LDL R3,#3 ; Checkpoint Value
STB R3,(R2,#0) ; Send Checkpoint value
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address
LDL R3,#3 ; Checkpoint Value
STB R3,(R2,#0) ; Send Checkpoint value
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_3
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_3
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_3
 
_END_3
LDL R3,#103
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#103
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
258,24 → 258,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ4
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#4 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#4 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_4
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_4
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_4
 
_END_4
LDL R3,#8
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#8
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
282,24 → 282,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ5
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$05 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$05 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_5
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_5
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_5
 
_END_5
LDL R3,#10
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#10
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
306,24 → 306,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ6
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#6 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#6 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_6
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_6
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_6
 
_END_6
LDL R3,#$12
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#$12
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
330,24 → 330,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ7
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#7 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#7 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_7
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_7
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_7
 
_END_7
LDL R3,#14
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#14
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
354,24 → 354,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ8
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#8 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#8 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_8
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_8
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_8
 
_END_8
LDL R3,#16
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#16
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
378,24 → 378,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ9
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#9 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#9 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_9
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_9
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_9
 
_END_9
LDL R3,#18
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#18
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
402,24 → 402,24
; Test Interrupt
;-------------------------------------------------------------------------------
_IRQ10
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#10 ; Checkpoint Value
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#10 ; Checkpoint Value
STB R3,(R2,#0)
 
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
;Test Interrupt
STW R3,(R2,#$0a) ; Should be even offsets
_TB_POLL_10
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_10
LDW R4,(R2,#$0a) ;
CMP R3,R4 ;
BEQ _TB_POLL_10
 
_END_10
LDL R3,#$20
STB R3,(R2,#0) ; Send Checkpoint value
LDL R3,#$20
STB R3,(R2,#0) ; Send Checkpoint value
 
SIF
RTS
SIF
RTS
 
 
;-------------------------------------------------------------------------------
426,8 → 426,8
;-------------------------------------------------------------------------------
END_CODE_
 
ORG $8000 ; Special Testbench Addresses
_BENCH DS.W 16
ORG $8000 ; Special Testbench Addresses
_BENCH DS.W 16
 
 
 
/trunk/sw/xgate_test_code/inst_test/inst_test.s
5,183 → 5,183
; Code function testing.
 
 
CPU XGATE
ORG $fe00
DS.W 2 ; reserve two words at channel 0
; channel 1
DC.W _START ; point to start address
DC.W V_PTR ; point to initial variables
; channel 2
DC.W _START2 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 3
DC.W _START3 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 4
DC.W _START4 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 5
DC.W _START5 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 6
DC.W _START6 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 7
DC.W _START7 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 8
DC.W _START8 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 9
DC.W _START9 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 10
DC.W _START10 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 11
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 12
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 13
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 14
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 15
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 16
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 17
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 18
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 19
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 20
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 21
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 22
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 23
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 24
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 25
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 26
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 27
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 28
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 29
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 30
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 31
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 32
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 33
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 34
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 35
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 36
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 37
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 38
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 39
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 40
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 41
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 42
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 43
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 44
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 45
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 46
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 47
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 48
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 49
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 50
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
CPU XGATE
 
ORG $2000 ; with comment
ORG $fe00
DS.W 2 ; reserve two words at channel 0
; channel 1
DC.W _START ; point to start address
DC.W V_PTR ; point to initial variables
; channel 2
DC.W _START2 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 3
DC.W _START3 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 4
DC.W _START4 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 5
DC.W _START5 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 6
DC.W _START6 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 7
DC.W _START7 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 8
DC.W _START8 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 9
DC.W _START9 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 10
DC.W _START10 ; point to start address
DC.W V_PTR ; point to initial variables
; channel 11
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 12
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 13
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 14
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 15
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 16
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 17
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 18
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 19
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 20
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 21
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 22
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 23
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 24
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 25
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 26
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 27
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 28
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 29
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 30
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 31
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 32
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 33
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 34
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 35
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 36
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 37
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 38
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 39
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 40
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 41
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 42
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 43
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 44
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 45
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 46
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 47
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 48
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 49
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
; channel 50
DC.W _ERROR ; point to start address
DC.W V_PTR ; point to initial variables
 
V_PTR EQU 123
ORG $2000 ; with comment
 
DC.W BACK_
DS.W 8
DC.B $56
DS.B 11
V_PTR EQU 123
 
ALIGN 1
DC.W BACK_
DS.W 8
DC.B $56
DS.B 11
 
ALIGN 1
 
;-------------------------------------------------------------------------------
; Place where undefined interrupts go
;-------------------------------------------------------------------------------
_ERROR
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$ff
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$ff
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
188,579 → 188,590
; Test Shift instructions
;-------------------------------------------------------------------------------
_START
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$01
STB R3,(R2,#0)
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$01
STB R3,(R2,#0)
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
 
; Test Bit Field Find First One
LDL R5,#$01 ; R5=$0001
LDH R5,#$4f ; R5=$4f01
BFFO R4,R5
BVS _FAIL ; Negative Flag should be clear
LDL R6,#$0e ; First one should have been in bit position 14
SUB R0,R6,R4
BNE _FAIL
BFFO R4,R0 ; Zero Value should set Carry Bit
BCC _FAIL
LDH R5,#$00 ; R5=$0001
BFFO R4,R5
BCS _FAIL ; Carry should be clear
BVS _FAIL ; Overflow Flag should be clear
SUB R0,R0,R4 ; R4 Should be zero
BNE _FAIL
; Test Bit Field Find First One
LDL R5,#$01 ; R5=$0001
LDH R5,#$4f ; R5=$4f01
BFFO R4,R5
BVS _FAIL ; Negative Flag should be clear
LDL R6,#$0e ; First one should have been in bit position 14
SUB R0,R6,R4
BNE _FAIL
BFFO R4,R0 ; Zero Value should set Carry Bit
BCC _FAIL
LDH R5,#$00 ; R5=$0001
BFFO R4,R5
BCS _FAIL ; Carry should be clear
BVS _FAIL ; Overflow Flag should be clear
SUB R0,R0,R4 ; R4 Should be zero
BNE _FAIL
 
; Test ASR instruction
LDL R5,#$04 ; R5=$0008
LDH R5,#$81 ; R5=$8108
LDL R3,#$03
ASR R5,R3 ; R5=$f000, Carry flag set
BCC _FAIL
BVS _FAIL ; Negative Flag should be clear
LDL R4,#$20 ; R4=$0020
LDH R4,#$f0 ; R4=$f020
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
; Test CSL insrtruction
LDL R5,#$10 ; R5=$0010
LDH R5,#$88 ; R5=$8810
LDL R3,#$05
CSL R5,R3 ; R5=$081f, Carry flag set
BCC _FAIL
LDL R4,#$00 ; R4=$0000
LDH R4,#$02 ; R4=$0200
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
;Test CSR instruction
LDL R5,#$88 ; R5=$0088
LDH R5,#$10 ; R5=$1088
LDL R3,#$04
CSR R5,R3 ; R5=$0108, Carry flag set
BCC _FAIL
LDL R4,#$08 ; R4=$0008
LDH R4,#$01 ; R4=$0108
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
;Test LSL instruction
LDL R2,#$ff ; R2=$00ff
LDH R2,#$07 ; R2=$07ff
LDL R1,#$06
LSL R2,R1 ; R2=$ffc0, Carry flag set
BCC _FAIL
LDL R4,#$c0 ; R4=$0008
LDH R4,#$ff ; R4=$0108
SUB R0,R2,R4 ; Compare R2 to R4
BNE _FAIL
;Test LSR instruction
LDL R7,#$02 ; R7=$0002
LDH R7,#$c3 ; R7=$c302
LDL R6,#$02
LSR R7,R6 ; R7=$30c0, Carry flag set
BCC _FAIL
LDL R4,#$c0 ; R4=$00c0
LDH R4,#$30 ; R4=$30c0
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
;Test ROL instruction
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
LDL R6,#$04
ROL R7,R6 ; R7=$362c
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$2c ; R4=$002c
LDH R4,#$36 ; R4=$362c
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
;Test ROR instruction
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
LDL R6,#$08
ROL R7,R6 ; R7=$62c3
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$c3 ; R4=$00c3
LDH R4,#$62 ; R4=$62c3
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
; Test ASR instruction
LDL R5,#$00 ; R5=$0000
LDH R5,#$80 ; R5=$8000
ASR R5,#0 ; R5=$ffff, Carry flag set
BCC _FAIL
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$ff ; R4=$00ff
LDH R4,#$ff ; R4=$ffff
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
; Test CSL insrtruction
LDL R5,#$01 ; R5=$0001
LDH R5,#$0f ; R5=$0f01
CSL R5,#0 ; R5=$0000, Carry flag set
BCC _FAIL
LDL R4,#$00 ; R4=$0000
LDH R4,#$00 ; R4=$0000
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
;Test CSR instruction
LDL R5,#$ff ; R5=$00ff
LDH R5,#$80 ; R5=$80ff
CSR R5,#15 ; R5=$0001, Carry flag clear
BCS _FAIL
LDL R4,#$01 ; R4=$0001
LDH R4,#$00 ; R4=$0001
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
;Test LSL instruction
LDL R2,#$1a ; R2=$001a
LDH R2,#$ff ; R2=$ff1a
LSL R2,#12 ; R2=$a000, Carry flag set
BCC _FAIL
LDL R4,#$00 ; R4=$0000
LDH R4,#$a0 ; R4=$a000
SUB R0,R2,R4 ; Compare R2 to R4
BNE _FAIL
;Test LSR instruction
LDL R7,#$8f ; R7=$008f
LDH R7,#$b2 ; R7=$b18f
LSR R7,#8 ; R7=$00b0, Carry flag set
BCC _FAIL
LDL R4,#$b2 ; R4=$00b0
LDH R4,#$00 ; R4=$00b0
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
;Test ROL instruction
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
ROL R7,#8 ; R7=$62c3
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$c3 ; R4=$00c3
LDH R4,#$62 ; R4=$62c3
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
;Test ROR instruction
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
ROL R7,#12 ; R7=$2c36
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$36 ; R4=$0036
LDH R4,#$2c ; R4=$2c36
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$02
STB R3,(R2,#0)
; Test ASR instruction **************************************************
LDL R5,#$04 ; R5=$0008
LDH R5,#$81 ; R5=$8108
LDL R3,#$03
ASR R5,R3 ; R5=$f000, Carry flag set
BCC _FAIL
BVS _FAIL ; Negative Flag should be clear
LDL R4,#$20 ; R4=$0020
LDH R4,#$f0 ; R4=$f020
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
 
NOP
NOP
SIF
RTS
; Test CSL instruction **************************************************
LDL R5,#$10 ; R5=$0010
LDH R5,#$88 ; R5=$8810
LDL R3,#$05
CSL R5,R3 ; R5=$081f, Carry flag set
BCC _FAIL
LDL R4,#$00 ; R4=$0000
LDH R4,#$02 ; R4=$0200
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
 
;Test CSR instruction ***************************************************
LDL R5,#$88 ; R5=$0088
LDH R5,#$10 ; R5=$1088
LDL R3,#$04
CSR R5,R3 ; R5=$0108, Carry flag set
BCC _FAIL
LDL R4,#$08 ; R4=$0008
LDH R4,#$01 ; R4=$0108
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
 
;Test LSL instruction ***************************************************
LDL R2,#$ff ; R2=$00ff
LDH R2,#$07 ; R2=$07ff
LDL R1,#$06
LSL R2,R1 ; R2=$ffc0, Carry flag set
BCC _FAIL
LDL R4,#$c0 ; R4=$0008
LDH R4,#$ff ; R4=$0108
SUB R0,R2,R4 ; Compare R2 to R4
BNE _FAIL
 
;Test LSR instruction ***************************************************
LDL R7,#$02 ; R7=$0002
LDH R7,#$c3 ; R7=$c302
LDL R6,#$02
LSR R7,R6 ; R7=$30c0, Carry flag set
BCC _FAIL
LDL R4,#$c0 ; R4=$00c0
LDH R4,#$30 ; R4=$30c0
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
 
;Test ROL instruction ***************************************************
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
LDL R6,#$04
ROL R7,R6 ; R7=$362c
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$2c ; R4=$002c
LDH R4,#$36 ; R4=$362c
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
 
;Test ROR instruction ***************************************************
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
LDL R6,#$08
ROR R7,R6 ; R7=$62c3
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$c3 ; R4=$00c3
LDH R4,#$62 ; R4=$62c3
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
 
; Test ASR instruction **************************************************
LDL R5,#$00 ; R5=$0000
LDH R5,#$80 ; R5=$8000
ASR R5,#0 ; R5=$ffff, Carry flag set
BCC _FAIL
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$ff ; R4=$00ff
LDH R4,#$ff ; R4=$ffff
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
 
; Test CSL insrtruction
LDL R5,#$01 ; R5=$0001
LDH R5,#$0f ; R5=$0f01
CSL R5,#0 ; R5=$0000, Carry flag set
BCC _FAIL
LDL R4,#$00 ; R4=$0000
LDH R4,#$00 ; R4=$0000
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
 
;Test CSR instruction ***************************************************
LDL R5,#$ff ; R5=$00ff
LDH R5,#$80 ; R5=$80ff
CSR R5,#15 ; R5=$0001, Carry flag clear
BCS _FAIL
LDL R4,#$01 ; R4=$0001
LDH R4,#$00 ; R4=$0001
SUB R0,R5,R4 ; Compare R5 to R4
BNE _FAIL
 
;Test LSL instruction ***************************************************
LDL R2,#$1a ; R2=$001a
LDH R2,#$ff ; R2=$ff1a
LSL R2,#12 ; R2=$a000, Carry flag set
BCC _FAIL
LDL R4,#$00 ; R4=$0000
LDH R4,#$a0 ; R4=$a000
SUB R0,R2,R4 ; Compare R2 to R4
BNE _FAIL
 
;Test LSR instruction ***************************************************
LDL R7,#$8f ; R7=$008f
LDH R7,#$b2 ; R7=$b18f
LSR R7,#8 ; R7=$00b0, Carry flag set
BCC _FAIL
LDL R4,#$b2 ; R4=$00b0
LDH R4,#$00 ; R4=$00b0
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
 
;Test ROL instruction ***************************************************
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
ROL R7,#8 ; R7=$62c3
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$c3 ; R4=$00c3
LDH R4,#$62 ; R4=$62c3
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
 
;Test ROR instruction ***************************************************
LDL R7,#$62 ; R7=$0062
LDH R7,#$c3 ; R7=$c362
ROR R7,#12 ; R7=$362c
BVS _FAIL ; Overflow Flag should be clear
LDL R4,#$2c ; R4=$002c
LDH R4,#$36 ; R4=$362c
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL
 
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$02
STB R3,(R2,#0)
 
NOP
NOP
SIF
RTS
 
_FAIL
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$02
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$02
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
;-------------------------------------------------------------------------------
; Test Logical Byte wide instructions
;-------------------------------------------------------------------------------
_START2
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$03 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$02 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$03 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$02 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
;Test ANDL instruction
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
ANDL R7,#$00 ; R7=&a500
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R3,#$00 ; R3=$0000
LDH R3,#$a5 ; R3=$a500
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
ANDL R7,#$80 ; R7=$a580
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
LDL R3,#$80 ; R3=$0080
LDH R3,#$a5 ; R3=$a580
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
;Test ANDL instruction **************************************************
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
ANDL R7,#$00 ; R7=&a500
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R3,#$00 ; R3=$0000
LDH R3,#$a5 ; R3=$a500
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
ANDL R7,#$80 ; R7=$a580
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
LDL R3,#$80 ; R3=$0080
LDH R3,#$a5 ; R3=$a580
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
 
;Test ANDH instruction
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
ANDH R7,#$00 ; R7=&0055
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R3,#$55 ; R3=$0000
LDH R3,#$00 ; R3=$a500
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
ANDH R7,#$80 ; R7=$80c5
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
LDL R3,#$c5 ; R3=$00c5
LDH R3,#$80 ; R3=$80c5
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
;Test ANDH instruction **************************************************
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
ANDH R7,#$00 ; R7=&0055
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R3,#$55 ; R3=$0000
LDH R3,#$00 ; R3=$a500
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
ANDH R7,#$80 ; R7=$80c5
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
LDL R3,#$c5 ; R3=$00c5
LDH R3,#$80 ; R3=$80c5
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
 
;Test BITL instruction
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
BITL R7,#$00 ; R7=&a500
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
BITL R7,#$80 ; R7=$a580
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
;Test BITH instruction
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
BITH R7,#$00 ; R7=&0055
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
BITH R7,#$80 ; R7=$80c5
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
;Test BITL instruction **************************************************
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
BITL R7,#$00 ; R7=&a500
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
BITL R7,#$80 ; R7=$a580
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
 
;Test ORL instruction
;Test BITH instruction **************************************************
LDL R7,#$55 ; R7=$0055
LDH R7,#$a5 ; R7=$a555
BITH R7,#$00 ; R7=&0055
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BMI _FAIL2 ; Negative Flag should be clear
LDL R7,#$c5 ; R7=$00c5
LDH R7,#$a5 ; R7=$a5c5
BITH R7,#$80 ; R7=$80c5
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
 
;Test ORL instruction ***************************************************
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$00 ; R7=$0000
LDH R7,#$a5 ; R7=$a500
ORL R7,#$00 ; R7=&a500
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$00 ; R3=$0000
LDH R3,#$a5 ; R3=$a500
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$00 ; R7=$0000
LDH R7,#$a5 ; R7=$a500
ORL R7,#$00 ; R7=&a500
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$00 ; R3=$0000
LDH R3,#$a5 ; R3=$a500
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R7,#$9f ; R7=$009f
LDH R7,#$a5 ; R7=$a59f
ORL R7,#$60 ; R7=$a5ff
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$ff ; R3=$00ff
LDH R3,#$a5 ; R3=$a5ff
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R7,#$9f ; R7=$009f
LDH R7,#$a5 ; R7=$a59f
ORL R7,#$60 ; R7=$a5ff
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$ff ; R3=$00ff
LDH R3,#$a5 ; R3=$a5ff
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
 
;Test ORH instruction
;Test ORH instruction ***************************************************
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$88 ; R7=$0088
LDH R7,#$00 ; R7=$0088
ORH R7,#$00 ; R7=&0088
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$88 ; R3=$0088
LDH R3,#$00 ; R3=$0088
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$88 ; R7=$0088
LDH R7,#$00 ; R7=$0088
ORH R7,#$00 ; R7=&0088
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$88 ; R3=$0088
LDH R3,#$00 ; R3=$0088
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R7,#$36 ; R7=$0036
LDH R7,#$a1 ; R7=$a136
ORH R7,#$50 ; R7=$f136
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$36 ; R3=$0036
LDH R3,#$f1 ; R3=$f136
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R7,#$36 ; R7=$0036
LDH R7,#$a1 ; R7=$a136
ORH R7,#$50 ; R7=$f136
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$36 ; R3=$0036
LDH R3,#$f1 ; R3=$f136
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
 
;Test XNORL instruction
;Test XNORL instruction *************************************************
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$c3 ; R7=$00c3
LDH R7,#$96 ; R7=$96c3
XNORL R7,#$3c ; R7=$9600
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$00 ; R3=$0000
LDH R3,#$96 ; R3=$9600
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$c3 ; R7=$00c3
LDH R7,#$96 ; R7=$96c3
XNORL R7,#$3c ; R7=$9600
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$00 ; R3=$0000
LDH R3,#$96 ; R3=$9600
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$00 ; R6=$0000
LDH R6,#$a5 ; R6=$a500
XNORL R6,#$73 ; R6=$a58c
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$8c ; R3=$008c
LDH R3,#$a5 ; R3=$a58c
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$00 ; R6=$0000
LDH R6,#$a5 ; R6=$a500
XNORL R6,#$73 ; R6=$a58c
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$8c ; R3=$008c
LDH R3,#$a5 ; R3=$a58c
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL2
 
;Test XNORH instruction
;Test XNORH instruction *************************************************
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$c3 ; R7=$00c3
LDH R7,#$96 ; R7=$96c3
XNORH R7,#$69 ; R7=$00c3
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$c3 ; R3=$00c3
LDH R3,#$00 ; R3=$00c3
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R7,#$c3 ; R7=$00c3
LDH R7,#$96 ; R7=$96c3
XNORH R7,#$69 ; R7=$00c3
BMI _FAIL2 ; Negative Flag should be clear
BNE _FAIL2 ; Zero Flag should be set
BVS _FAIL2 ; Overflow Flag should be clear
BCC _FAIL2 ; Carry Flag should be set
LDL R3,#$c3 ; R3=$00c3
LDH R3,#$00 ; R3=$00c3
SUB R0,R7,R3 ; Compare R7 to R3
BNE _FAIL2
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$66 ; R6=$0066
LDH R6,#$66 ; R6=$6666
XNORH R6,#$66 ; R6=$ff66
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$66 ; R3=$0066
LDH R3,#$ff ; R3=$ff66
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL2
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$66 ; R6=$0066
LDH R6,#$66 ; R6=$6666
XNORH R6,#$66 ; R6=$ff66
BPL _FAIL2 ; Negative Flag should be set
BEQ _FAIL2 ; Zero Flag should be clear
BVS _FAIL2 ; Overflow Flag should be clear
BCS _FAIL2 ; Carry Flag should be clear
LDL R3,#$66 ; R3=$0066
LDH R3,#$ff ; R3=$ff66
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL2
 
 
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$04
STB R3,(R2,#0)
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$04
STB R3,(R2,#0)
 
SIF
RTS
SIF
RTS
 
_FAIL2
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$04
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$04
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
;-------------------------------------------------------------------------------
; Test Logical Word Wide instructions
;-------------------------------------------------------------------------------
_START3
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$05 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$03 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$05 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$03 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
;Test SEX instruction
;Test SEX instruction ***************************************************
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
LDL R3,#$00 ; R3=$0000
LDH R3,#$ff ; R3=$ff00
SEX R3 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R6,#$00 ; R6=$0000
LDH R6,#$00 ; R6=$0000
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL3
LDH R3,#$ff ; R3=$ff00
SEX R3 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R6,#$00 ; R6=$0000
LDH R6,#$00 ; R6=$0000
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL3
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$83 ; R6=$0083
LDH R6,#$00 ; R6=$0083
SEX R6 ; R6=$ff83
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
LDL R3,#$83 ; R3=$0083
LDH R3,#$ff ; R3=$ff83
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL3
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$83 ; R6=$0083
LDH R6,#$00 ; R6=$0083
SEX R6 ; R6=$ff83
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
LDL R3,#$83 ; R3=$0083
LDH R3,#$ff ; R3=$ff83
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL3
 
;Test PAR instruction
;Test PAR instruction ***************************************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R4,#$00 ; R4=$0000
LDH R4,#$00 ; R4=$0000
PAR R4 ; R4=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
LDL R6,#$00 ; R6=$0000
LDH R6,#$00 ; R6=$0000
SUB R0,R6,R4 ; Compare R6 to R4
BNE _FAIL3
LDH R4,#$00 ; R4=$0000
PAR R4 ; R4=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
LDL R6,#$00 ; R6=$0000
LDH R6,#$00 ; R6=$0000
SUB R0,R6,R4 ; Compare R6 to R4
BNE _FAIL3
LDL R2,#$0e
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
LDL R6,#$01 ; R6=$0001
LDH R6,#$03 ; R6=$0301
PAR R6 ; R6=$0301
BMI _FAIL3 ; Negative Flag should be clear
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R3,#$01 ; R3=$0001
LDH R3,#$03 ; R3=$0301
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL3
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
LDL R6,#$01 ; R6=$0001
LDH R6,#$03 ; R6=$0301
PAR R6 ; R6=$0301
BMI _FAIL3 ; Negative Flag should be clear
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R3,#$01 ; R3=$0001
LDH R3,#$03 ; R3=$0301
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL3
 
;Test AND instruction
;Test AND instruction ***************************************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R6,#$55 ; R6=$0055
LDH R6,#$aa ; R6=$aa55
LDL R5,#$aa ; R5=$00aa
LDH R5,#$55 ; R5=$55aa
AND R3,R5,R6 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
SUB R0,R0,R3 ; Compare R0 to R3
BNE _FAIL3
LDL R7,#$55 ; R7=$00c5
LDH R7,#$aa ; R7=$aa55
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R6,#$55 ; R6=$0055
LDH R6,#$aa ; R6=$aa55
LDL R5,#$aa ; R5=$00aa
LDH R5,#$55 ; R5=$55aa
AND R3,R5,R6 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
SUB R0,R0,R3 ; Compare R0 to R3
BNE _FAIL3
LDL R7,#$55 ; R7=$00c5
LDH R7,#$aa ; R7=$aa55
LDL R2,#$07
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
AND R4,R6,R7 ; R4=$aa55
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
SUB R0,R4,R7 ; Compare R4 to R7
BNE _FAIL2
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
AND R4,R6,R7 ; R4=$aa55
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
SUB R0,R4,R7 ; Compare R4 to R7
BNE _FAIL2
 
;Test OR instruction
;Test OR instruction ****************************************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R6,#$00 ; R6=$0000
LDL R5,#$00 ; R5=$0000
OR R3,R5,R6 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
SUB R0,R0,R3 ; Compare R0 to R3
BNE _FAIL3
LDL R7,#$55 ; R7=$00c5
LDH R7,#$aa ; R7=$aa55
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R6,#$00 ; R6=$0000
LDL R5,#$00 ; R5=$0000
OR R3,R5,R6 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
SUB R0,R0,R3 ; Compare R0 to R3
BNE _FAIL3
LDL R7,#$55 ; R7=$00c5
LDH R7,#$aa ; R7=$aa55
LDL R6,#$8a ; R6=$008a
LDH R6,#$10 ; R7=$108a
LDH R6,#$10 ; R7=$108a
LDL R2,#$07
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
OR R4,R6,R7 ; R4=$badf
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R3,#$df ; R3=$00df
LDH R3,#$ba ; R3=$badf
SUB R0,R4,R3 ; Compare R6 to R3
BNE _FAIL3
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
OR R4,R6,R7 ; R4=$badf
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R3,#$df ; R3=$00df
LDH R3,#$ba ; R3=$badf
SUB R0,R4,R3 ; Compare R6 to R3
BNE _FAIL3
 
;Test XNOR instruction
;Test XNOR instruction **************************************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R1,#$55 ; R1=$0055
LDH R1,#$aa ; R1=$aa55
LDL R5,#$aa ; R5=$00aa
LDH R5,#$55 ; R5=$55aa
XNOR R3,R5,R1 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
SUB R0,R0,R3 ; Compare R0 to R3
BNE _FAIL3
LDL R7,#$cc ; R7=$00cc
LDH R7,#$33 ; R7=$33cc
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
LDL R1,#$55 ; R1=$0055
LDH R1,#$aa ; R1=$aa55
LDL R5,#$aa ; R5=$00aa
LDH R5,#$55 ; R5=$55aa
XNOR R3,R5,R1 ; R3=$0000
BMI _FAIL3 ; Negative Flag should be clear
BNE _FAIL3 ; Zero Flag should be set
BVS _FAIL3 ; Overflow Flag should be clear
BCS _FAIL3 ; Carry Flag should be clear
SUB R0,R0,R3 ; Compare R0 to R3
BNE _FAIL3
LDL R7,#$cc ; R7=$00cc
LDH R7,#$33 ; R7=$33cc
LDL R2,#$01 ; R2=$0001
LDH R2,#$40 ; R2=$4001
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
XNOR R4,R7,R2 ; R4=$8c32
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R3,#$32 ; R3=$0032
LDH R3,#$8c ; R3=$8c32
SUB R0,R4,R3 ; Compare R4 to R3
BNE _FAIL3
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$06
STB R3,(R2,#0)
LDH R2,#$40 ; R2=$4001
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
XNOR R4,R7,R2 ; R4=$8c32
BPL _FAIL3 ; Negative Flag should be set
BEQ _FAIL3 ; Zero Flag should be clear
BVS _FAIL3 ; Overflow Flag should be clear
BCC _FAIL3 ; Carry Flag should be set
LDL R3,#$32 ; R3=$0032
LDH R3,#$8c ; R3=$8c32
SUB R0,R4,R3 ; Compare R4 to R3
BNE _FAIL3
 
NOP
SIF
RTS
 
;Test TFR instruction ***************************************************
MOV R1,R0
COM R1
TFR CCR,R1 ; Negative=1, Zero=1, Overflow=1, Carry=1
TFR R5,CCR ; R5=$000f
LDL R6,#$0f ; R6=$xx0f
LDH R6,#$00 ; R5=$000f
CMP R5,R6
BNE _FAIL3
 
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$06
STB R3,(R2,#0)
 
NOP
SIF
RTS
 
_FAIL3
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$06
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$06
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
767,129 → 778,129
; Test Bit Field instructions
;-------------------------------------------------------------------------------
_START4
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$07 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$04 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$07 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$04 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
;Test BFEXT instruction
;Test BFEXT instruction *************************************************
LDL R2,#$0e
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
SEX R4 ; Set R4=$ffff
BFEXT R4,R5,R6 ; R4=$000a
BMI _FAIL4 ; Negative Flag should be clear
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$0a ; R7=$00cc
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
SEX R4 ; Set R4=$ffff
BFEXT R4,R5,R6 ; R4=$000a
BMI _FAIL4 ; Negative Flag should be clear
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$0a ; R7=$00cc
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
LDL R6,#$b8 ; Set offset to 8 and width to 11(12 bits)
BFEXT R4,R5,R6 ; R4=$00c3
LDL R7,#$c3 ; R7=$00c3
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
LDL R6,#$b8 ; Set offset to 8 and width to 11(12 bits)
BFEXT R4,R5,R6 ; R4=$00c3
LDL R7,#$c3 ; R7=$00c3
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
;Test BFINS instruction
;Test BFINS instruction *************************************************
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
SEX R4 ; Set R4=$ffff
BFINS R4,R5,R6 ; R4=$ffaf
BPL _FAIL4 ; Negative Flag should be set
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$6f ; R7=$006f
LDH R7,#$ff ; R7=$ff6f
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
SEX R4 ; Set R4=$ffff
BFINS R4,R5,R6 ; R4=$ffaf
BPL _FAIL4 ; Negative Flag should be set
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$6f ; R7=$006f
LDH R7,#$ff ; R7=$ff6f
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
LDL R6,#$b0 ; Set offset to 0 and width to 11(12 bits)
BFINS R4,R5,R6 ; R4=$f3a6
LDL R7,#$a6 ; R7=$00a6
LDH R7,#$f3 ; R7=$f3a6
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
LDL R6,#$b0 ; Set offset to 0 and width to 11(12 bits)
BFINS R4,R5,R6 ; R4=$f3a6
LDL R7,#$a6 ; R7=$00a6
LDH R7,#$f3 ; R7=$f3a6
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
;Test BFINSI instruction
;Test BFINSI instruction ************************************************
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$3c ; Set offset to 12 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
SEX R4 ; Set R4=$ffff
BFINSI R4,R5,R6 ; R4=$9fff
BPL _FAIL4 ; Negative Flag should be set
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$ff ; R7=$00ff
LDH R7,#$9f ; R7=$ff6f
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$3c ; Set offset to 12 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
SEX R4 ; Set R4=$ffff
BFINSI R4,R5,R6 ; R4=$9fff
BPL _FAIL4 ; Negative Flag should be set
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$ff ; R7=$00ff
LDH R7,#$9f ; R7=$ff6f
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
LDL R6,#$78 ; Set offset to 8 and width to 7(8 bits)
BFINSI R4,R5,R6 ; R4=$59ff
LDL R7,#$ff ; R7=$00ff
LDH R7,#$59 ; R7=$59ff
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
LDL R6,#$78 ; Set offset to 8 and width to 7(8 bits)
BFINSI R4,R5,R6 ; R4=$59ff
LDL R7,#$ff ; R7=$00ff
LDH R7,#$59 ; R7=$59ff
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
;Test BFINSX instruction
;Test BFINSX instruction ************************************************
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$38 ; Set offset to 8 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
LDH R4,#$fa ; Set R4=$faff
BFINSX R4,R5,R6 ; R4=$f3ff
BPL _FAIL4 ; Negative Flag should be set
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$ff ; R7=$00ff
LDH R7,#$f3 ; R7=$f3ff
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
LDL R6,#$38 ; Set offset to 8 and width to 3(4 bits)
LDL R5,#$a6 ; Set R5=$00a6
LDH R5,#$c3 ; Set R5=$c3a6
LDL R4,#$ff ; Set R4=$00ff
LDH R4,#$fa ; Set R4=$faff
BFINSX R4,R5,R6 ; R4=$f3ff
BPL _FAIL4 ; Negative Flag should be set
BEQ _FAIL4 ; Zero Flag should be clear
BVS _FAIL4 ; Overflow Flag should be clear
BCS _FAIL4 ; Carry Flag should be clear
LDL R7,#$ff ; R7=$00ff
LDH R7,#$f3 ; R7=$f3ff
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
LDL R6,#$70 ; Set offset to 0 and width to 7(8 bits)
BFINSX R4,R5,R6 ; R4=$f3a6
LDL R7,#$a6 ; R7=$00a6
LDH R7,#$f3 ; R7=$f3a6
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
LDL R6,#$70 ; Set offset to 0 and width to 7(8 bits)
BFINSX R4,R5,R6 ; R4=$f3a6
LDL R7,#$a6 ; R7=$00a6
LDH R7,#$f3 ; R7=$f3a6
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL4
 
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$08
STB R3,(R2,#0)
 
NOP
SIF
RTS
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$08
STB R3,(R2,#0)
 
NOP
SIF
RTS
 
_FAIL4
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$08
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$08
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
896,822 → 907,893
; Test Branch instructions
;-------------------------------------------------------------------------------
_START5
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$09 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$05 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$09 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$05 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
;Test BCC instruction C = 0
;Test BCC instruction C = 0 ******************************************
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BCC _BCC_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BCC _BCC_OK1 ; Take Branch
BRA _BR_ERR
_BCC_OK1
LDL R2,#$01
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BCC _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BCC _BR_ERR ; Don't take branch
 
 
;Test BCS instruction C = 1
;Test BCS instruction C = 1 ******************************************
LDL R2,#$01
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BCS _BCS_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BCS _BCS_OK1 ; Take Branch
BRA _BR_ERR
_BCS_OK1
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BCS _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BCS _BR_ERR ; Don't take branch
 
 
;Test BEQ instruction Z = 1
;Test BEQ instruction Z = 1 ******************************************
LDL R2,#$04
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BEQ _BEQ_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BEQ _BEQ_OK1 ; Take Branch
BRA _BR_ERR
_BEQ_OK1
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BEQ _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BEQ _BR_ERR ; Don't take branch
 
 
;Test BNE instruction Z = 0
;Test BNE instruction Z = 0 ******************************************
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BNE _BNE_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BNE _BNE_OK1 ; Take Branch
BRA _BR_ERR
_BNE_OK1
LDL R2,#$04
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BNE _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BNE _BR_ERR ; Don't take branch
 
 
;Test BPL instruction N = 0
;Test BPL instruction N = 0 ******************************************
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BPL _BPL_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BPL _BPL_OK1 ; Take Branch
BRA _BR_ERR
_BPL_OK1
LDL R2,#$08
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BPL _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BPL _BR_ERR ; Don't take branch
 
 
;Test BMI instruction N = 1
;Test BMI instruction N = 1 ******************************************
LDL R2,#$08
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BMI _BMI_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BMI _BMI_OK1 ; Take Branch
BRA _BR_ERR
_BMI_OK1
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BMI _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BMI _BR_ERR ; Don't take branch
 
 
;Test BVC instruction V = 0
;Test BVC instruction V = 0 ******************************************
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BVC _BVC_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BVC _BVC_OK1 ; Take Branch
BRA _BR_ERR
_BVC_OK1
LDL R2,#$02
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BVC _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BVC _BR_ERR ; Don't take branch
 
 
;Test BVS instruction V = 1
;Test BVS instruction V = 1 ******************************************
LDL R2,#$02
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BVS _BVS_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BVS _BVS_OK1 ; Take Branch
BRA _BR_ERR
_BVS_OK1
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BVS _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BVS _BR_ERR ; Don't take branch
 
 
;Test BLS instruction C | Z = 1
;Test BLS instruction C | Z = 1 **************************************
LDL R2,#$01
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BLS _BLS_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BLS _BLS_OK1 ; Take Branch
BRA _BR_ERR
_BLS_OK1
LDL R2,#$04
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BLS _BLS_OK2 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BLS _BLS_OK2 ; Take Branch
BRA _BR_ERR
_BLS_OK2
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BLS _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BLS _BR_ERR ; Don't take branch
 
 
;Test BGE instruction N ^ V = 0
;Test BGE instruction N ^ V = 0 **************************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BGE _BGE_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BGE _BGE_OK1 ; Take Branch
BRA _BR_ERR
_BGE_OK1
LDL R2,#$05
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
BGE _BGE_OK2 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
BGE _BGE_OK2 ; Take Branch
BRA _BR_ERR
_BGE_OK2
LDL R2,#$08
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BGE _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BGE _BR_ERR ; Don't take branch
 
 
;Test BHI instruction Z | C = 0
;Test BLT instruction N ^ V = 1 **************************************
LDL R2,#$08
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BLT _BLT_OK1 ; Take Branch
BRA _BR_ERR
_BLT_OK1
LDL R2,#$02
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
BLT _BLT_OK2 ; Take Branch
BRA _BR_ERR
_BLT_OK2
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BHI _BHI_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BLT _BR_ERR ; Don't take branch
 
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BLT _BR_ERR ; Don't take branch
 
 
;Test BHI instruction Z | C = 0 **************************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BHI _BHI_OK1 ; Take Branch
BRA _BR_ERR
_BHI_OK1
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
BHI _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
BHI _BR_ERR ; Don't take branch
 
LDL R2,#$0e
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
BHI _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
BHI _BR_ERR ; Don't take branch
 
 
;Test BGT instruction Z | (N ^ V) = 0
;Test BGT instruction Z | (N ^ V) = 0 ********************************
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BGT _BGT_OK1 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BGT _BGT_OK1 ; Take Branch
BRA _BR_ERR
_BGT_OK1
LDL R2,#$01
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BGT _BGT_OK2 ; Take Branch
BRA _BR_ERR
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
BGT _BGT_OK2 ; Take Branch
BRA _BR_ERR
_BGT_OK2
LDL R2,#$0e
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
BGT _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
BGT _BR_ERR ; Don't take branch
 
LDL R2,#$02
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BGT _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BGT _BR_ERR ; Don't take branch
 
LDL R2,#$08
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BGT _BR_ERR ; Don't take branch
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BGT _BR_ERR ; Don't take branch
 
 
BRA BRA_FWARD
;Test BLE instruction Z | (N ^ V) = 1 ********************************
LDL R2,#$04
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
BLE _BLE_OK1 ; Take Branch
BRA _BR_ERR
_BLE_OK1
LDL R2,#$02
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
BLE _BLE_OK2 ; Take Branch
BRA _BR_ERR
_BLE_OK2
LDL R2,#$08
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
BLE _BLE_OK3 ; Take Branch
BRA _BR_ERR
_BLE_OK3
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
BLE _BR_ERR ; Don't take branch
 
LDL R2,#$00
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
BLE _BR_ERR ; Don't take branch
 
 
;Test BRA instruction **************************************************
BRA BRA_FWARD
 
 
_BR_ERR
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$0a
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$0a
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
_BRA_OK
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0a
STB R3,(R2,#0)
_BRA_OK
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0a
STB R3,(R2,#0)
 
SIF
RTS
SIF
RTS
 
BRA_FWARD
BRA _BRA_OK ; Test backward branch caculation
BRA _BRA_OK ; Test backward branch caculation
 
 
;-------------------------------------------------------------------------------
; Test Subroutine Call and return instructions
;-------------------------------------------------------------------------------
_START6
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0b ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$06 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0b ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$06 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
LDL R4,#$00
TFR R5,PC ; Subroutine Call
BRA SUB_TST
LDL R4,#$00
TFR R5,PC ; Subroutine Call
BRA SUB_TST
 
RET_SUB
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0c
STB R3,(R2,#0)
SIF
RTS
 
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0c
STB R3,(R2,#0)
 
SIF
RTS
 
_FAIL6
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$0c
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$0c
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
SUB_TST
LDL R4,#$88 ; If we branch to far then the wrong data will get loaded
LDH R4,#$99 ; and we'll make a bad compare to cause test to fail
LDL R7,#$88 ; R7=$0088
LDH R7,#$99 ; R7=$9988
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL6
JAL R5 ; Jump to return address
LDL R4,#$88 ; If we branch to far then the wrong data will get loaded
LDH R4,#$99 ; and we'll make a bad compare to cause test to fail
LDL R7,#$88 ; R7=$0088
LDH R7,#$99 ; R7=$9988
SUB R0,R7,R4 ; Compare R7 to R4
BNE _FAIL6
JAL R5 ; Jump to return address
 
;-------------------------------------------------------------------------------
; Test 16 bit Addition and Substract instructions
;-------------------------------------------------------------------------------
_START7
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0d ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$07 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0d ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$07 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
;Test SUB instruction
LDL R4,#$0f ; R4=$000f
LDH R4,#$01 ; R4=$010f
LDL R7,#$0e ; R7=$000e
LDH R7,#$01 ; R7=$010e
;Test SUB instruction ***************************************************
LDL R4,#$0f ; R4=$000f
LDH R4,#$01 ; R4=$010f
LDL R7,#$0e ; R7=$000e
LDH R7,#$01 ; R7=$010e
LDL R2,#$0f
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
SUB R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BEQ _FAIL7 ; Zero Flag should be clear
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$01 ; R3=$0001
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
SUB R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BEQ _FAIL7 ; Zero Flag should be clear
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$01 ; R3=$0001
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
 
LDL R7,#$0f ; R7=$000f
LDH R7,#$01 ; R7=$010f
LDL R7,#$0f ; R7=$000f
LDH R7,#$01 ; R7=$010f
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
SUB R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BNE _FAIL7 ; Zero Flag should be set
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
SUB R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BNE _FAIL7 ; Zero Flag should be set
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
 
 
;Test SBC instruction
LDL R4,#$11 ; R4=$0011
LDH R4,#$01 ; R4=$0111
LDL R7,#$0e ; R7=$000e
LDH R7,#$01 ; R7=$010e
;Test SBC instruction ***************************************************
LDL R4,#$11 ; R4=$0011
LDH R4,#$01 ; R4=$0111
LDL R7,#$0e ; R7=$000e
LDH R7,#$01 ; R7=$010e
LDL R2,#$0f
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
SBC R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BEQ _FAIL7 ; Zero Flag should be clear
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$02 ; R3=$0002
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
SBC R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BEQ _FAIL7 ; Zero Flag should be clear
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$02 ; R3=$0002
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
 
LDL R4,#$0f ; R4=$000f
LDH R4,#$01 ; R4=$010f
LDL R7,#$0f ; R7=$000f
LDH R7,#$01 ; R7=$010f
LDL R4,#$0f ; R4=$000f
LDH R4,#$01 ; R4=$010f
LDL R7,#$0f ; R7=$000f
LDH R7,#$01 ; R7=$010f
LDL R2,#$0a
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
SBC R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BEQ _FAIL7 ; Zero Flag should be clear
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
SBC R1,R4,R7 ; R4 - R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BEQ _FAIL7 ; Zero Flag should be clear
BVS _FAIL7 ; Overflow Flag should be clear
BCS _FAIL7 ; Carry Flag should be clear
 
 
;Test ADD instruction
LDL R4,#$0f ; R4=$000f
LDH R4,#$70 ; R4=$700f
LDL R7,#$01 ; R7=$0001
LDH R7,#$10 ; R7=$1001
;Test ADD instruction ***************************************************
LDL R4,#$0f ; R4=$000f
LDH R4,#$70 ; R4=$700f
LDL R7,#$01 ; R7=$0001
LDH R7,#$10 ; R7=$1001
LDL R2,#$05
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
ADD R1,R4,R7 ; R4 + R7 => R1
BPL _FAIL7 ; Negative Flag should be set
BEQ _FAIL7 ; Zero Flag should be clear
BVC _FAIL7 ; Overflow Flag should be set
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$10 ; R3=$0010
LDH R3,#$80 ; R3=$8010
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
ADD R1,R4,R7 ; R4 + R7 => R1
BPL _FAIL7 ; Negative Flag should be set
BEQ _FAIL7 ; Zero Flag should be clear
BVC _FAIL7 ; Overflow Flag should be set
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$10 ; R3=$0010
LDH R3,#$80 ; R3=$8010
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
 
LDL R4,#$00 ; R4=$0000
LDH R4,#$80 ; R4=$8000
LDL R7,#$00 ; R7=$0000
LDH R7,#$80 ; R7=$8000
LDL R4,#$00 ; R4=$0000
LDH R4,#$80 ; R4=$8000
LDL R7,#$00 ; R7=$0000
LDH R7,#$80 ; R7=$8000
LDL R2,#$0f
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
ADD R1,R4,R7 ; R4 + R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BNE _FAIL7 ; Zero Flag should be set
BVC _FAIL7 ; Overflow Flag should be set
BCC _FAIL7 ; Carry Flag should be set
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
BNE _FAIL7
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
ADD R1,R4,R7 ; R4 + R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BNE _FAIL7 ; Zero Flag should be set
BVC _FAIL7 ; Overflow Flag should be set
BCC _FAIL7 ; Carry Flag should be set
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
BNE _FAIL7
 
 
;Test ADC instruction
LDL R4,#$0f ; R4=$000f
LDH R4,#$70 ; R4=$700f
LDL R7,#$01 ; R7=$0001
LDH R7,#$10 ; R7=$1001
;Test ADC instruction ***************************************************
LDL R4,#$0f ; R4=$000f
LDH R4,#$70 ; R4=$700f
LDL R7,#$01 ; R7=$0001
LDH R7,#$10 ; R7=$1001
LDL R2,#$05
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
ADC R1,R4,R7 ; R4 + R7 => R1
BPL _FAIL7 ; Negative Flag should be set
BEQ _FAIL7 ; Zero Flag should be clear
BVC _FAIL7 ; Overflow Flag should be set
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$11 ; R3=$0011
LDH R3,#$80 ; R3=$8011
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
ADC R1,R4,R7 ; R4 + R7 => R1
BPL _FAIL7 ; Negative Flag should be set
BEQ _FAIL7 ; Zero Flag should be clear
BVC _FAIL7 ; Overflow Flag should be set
BCS _FAIL7 ; Carry Flag should be clear
LDL R3,#$11 ; R3=$0011
LDH R3,#$80 ; R3=$8011
SUB R0,R1,R3 ; Compare R1 to R3
BNE _FAIL7
 
LDL R4,#$00 ; R4=$0000
LDH R4,#$80 ; R4=$8000
LDL R7,#$00 ; R7=$0000
LDH R7,#$80 ; R7=$8000
LDL R4,#$00 ; R4=$0000
LDH R4,#$80 ; R4=$8000
LDL R7,#$00 ; R7=$0000
LDH R7,#$80 ; R7=$8000
LDL R2,#$0c
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
ADC R1,R4,R7 ; R4 + R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BNE _FAIL7 ; Zero Flag should be set
BVC _FAIL7 ; Overflow Flag should be set
BCC _FAIL7 ; Carry Flag should be set
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
BNE _FAIL7
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
ADC R1,R4,R7 ; R4 + R7 => R1
BMI _FAIL7 ; Negative Flag should be clear
BNE _FAIL7 ; Zero Flag should be set
BVC _FAIL7 ; Overflow Flag should be set
BCC _FAIL7 ; Carry Flag should be set
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
BNE _FAIL7
 
 
_END_7
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0e
STB R3,(R2,#0)
SIF
RTS
_END_7
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0e
STB R3,(R2,#0)
 
SIF
RTS
 
_FAIL7
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$0e
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$0e
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
;-------------------------------------------------------------------------------
; Test 8 bit Addition and Substract instructions
;-------------------------------------------------------------------------------
_START8
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0f ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$08 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$0f ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$08 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
;Test SUBL instruction
LDL R5,#$0f ; R5=$000f
;Test SUBL instruction **************************************************
LDL R5,#$0f ; R5=$000f
LDL R2,#$0f
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
SUBL R5,#$0e ; R5 - $0e => R5
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCS _FAIL8 ; Carry Flag should be clear
LDL R3,#$01 ; R3=$0001
SUB R0,R5,R3 ; Compare R5 to R3
BNE _FAIL8
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
SUBL R5,#$0e ; R5 - $0e => R5
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCS _FAIL8 ; Carry Flag should be clear
LDL R3,#$01 ; R3=$0001
SUB R0,R5,R3 ; Compare R5 to R3
BNE _FAIL8
 
LDL R7,#$0f ; R7=$000f
LDL R7,#$0f ; R7=$000f
LDL R2,#$0d
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
SUBL R7,#$10 ; R7 - $10 => R7
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
CMPL R7,#$FF ; Result should be -1 or $FFFF
CPCH R7,#$FF
BNE _FAIL8
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
SUBL R7,#$10 ; R7 - $10 => R7
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
CMPL R7,#$FF ; Result should be -1 or $FFFF
CPCH R7,#$FF
BNE _FAIL8
 
;Test SUBH instruction
LDL R6,#$11 ; R4=$0011
LDH R6,#$81 ; R4=$8111
;Test SUBH instruction **************************************************
LDL R6,#$11 ; R4=$0011
LDH R6,#$81 ; R4=$8111
LDL R2,#$0d
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=1
SUBH R6,#$70 ; R6 - $70 => R6
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVC _FAIL8 ; Overflow Flag should be set
BCS _FAIL8 ; Carry Flag should be clear
LDL R3,#$11 ; R3=$0011
LDH R3,#$11 ; R3=$1111
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL8
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=1
SUBH R6,#$70 ; R6 - $70 => R6
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVC _FAIL8 ; Overflow Flag should be set
BCS _FAIL8 ; Carry Flag should be clear
LDL R3,#$11 ; R3=$0011
LDH R3,#$11 ; R3=$1111
SUB R0,R6,R3 ; Compare R6 to R3
BNE _FAIL8
 
LDL R6,#$00 ; R6=$0000
LDH R6,#$01 ; R6=$0100
LDL R6,#$00 ; R6=$0000
LDH R6,#$01 ; R6=$0100
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
SUBH R6,#$02 ; R6 - $70 => R6
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
SUBH R6,#$02 ; R6 - $70 => R6
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
 
 
;Test CMPL instruction
LDL R5,#$0f ; R5=$000f
;Test CMPL instruction **************************************************
LDL R5,#$0f ; R5=$000f
LDL R2,#$0b
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
CMPL R5,#$0f ; R5 - $0f => R5
BMI _FAIL8 ; Negative Flag should be clear
BNE _FAIL8 ; Zero Flag should be set
BVS _FAIL8 ; Overflow Flag should be clear
BCS _FAIL8 ; Carry Flag should be clear
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
CMPL R5,#$0f ; R5 - $0f => R5
BMI _FAIL8 ; Negative Flag should be clear
BNE _FAIL8 ; Zero Flag should be set
BVS _FAIL8 ; Overflow Flag should be clear
BCS _FAIL8 ; Carry Flag should be clear
 
LDL R7,#$0f ; R7=$000f
LDL R7,#$0f ; R7=$000f
LDL R2,#$07
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
CMPL R7,#$10 ; R7 - $10 => R7
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
CMPL R7,#$10 ; R7 - $10 => R7
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
 
 
;Test CPCH instruction
LDL R5,#$00 ; R5=$0000
LDH R5,#$01 ; R5=$0001
;Test CPCH instruction **************************************************
LDL R5,#$00 ; R5=$0000
LDH R5,#$01 ; R5=$0001
LDL R2,#$0f
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
CPCH R5,#$00 ; R5 - $00 - carryflag => nowhere
BMI _FAIL8 ; Negative Flag should be clear
BNE _FAIL8 ; Zero Flag should be set
BVS _FAIL8 ; Overflow Flag should be clear
BCS _FAIL8 ; Carry Flag should be clear
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
CPCH R5,#$00 ; R5 - $00 - carryflag => nowhere
BMI _FAIL8 ; Negative Flag should be clear
BNE _FAIL8 ; Zero Flag should be set
BVS _FAIL8 ; Overflow Flag should be clear
BCS _FAIL8 ; Carry Flag should be clear
LDL R2,#$06
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
CPCH R5,#$02 ; R5 - $00 - carryflag => nowhere
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
CPCH R5,#$02 ; R5 - $00 - carryflag => nowhere
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
 
 
;Test ADDH instruction
LDL R5,#$0f ; R5=$000f
LDH R5,#$70 ; R5=$700f
;Test ADDH instruction **************************************************
LDL R5,#$0f ; R5=$000f
LDH R5,#$70 ; R5=$700f
LDL R2,#$0e
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
ADDH R5,#$a0 ; R5 + $a0 => R5
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
LDL R3,#$0f ; R3=$000f
LDH R3,#$10 ; R3=$100f
SUB R0,R5,R3 ; Compare R5 to R3
BNE _FAIL8
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
ADDH R5,#$a0 ; R5 + $a0 => R5
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
LDL R3,#$0f ; R3=$000f
LDH R3,#$10 ; R3=$100f
SUB R0,R5,R3 ; Compare R5 to R3
BNE _FAIL8
 
LDL R2,#$07
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
ADDH R5,#$70 ; R5 + $70 => R5
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVC _FAIL8 ; Overflow Flag should be set
BCS _FAIL8 ; Carry Flag should be clear
LDL R3,#$0f ; R3=$000f
LDH R3,#$80 ; R3=$800f
SUB R0,R5,R3 ; Compare R5 to R3
BNE _FAIL8
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
ADDH R5,#$70 ; R5 + $70 => R5
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVC _FAIL8 ; Overflow Flag should be set
BCS _FAIL8 ; Carry Flag should be clear
LDL R3,#$0f ; R3=$000f
LDH R3,#$80 ; R3=$800f
SUB R0,R5,R3 ; Compare R5 to R3
BNE _FAIL8
 
 
;Test ADDL instruction
LDL R4,#$ff ; R4=$00ff
LDH R4,#$70 ; R4=$70ff
;Test ADDL instruction **************************************************
LDL R4,#$ff ; R4=$00ff
LDH R4,#$70 ; R4=$70ff
LDL R2,#$0e
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
ADDL R4,#$01 ; R4 + $01 => R4
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
LDL R5,#$00 ; R5=$0000
LDH R5,#$71 ; R5=$7100
SUB R0,R4,R5 ; Compare R4 to R5
BNE _FAIL8
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
ADDL R4,#$01 ; R4 + $01 => R4
BMI _FAIL8 ; Negative Flag should be clear
BEQ _FAIL8 ; Zero Flag should be clear
BVS _FAIL8 ; Overflow Flag should be clear
BCC _FAIL8 ; Carry Flag should be set
LDL R5,#$00 ; R5=$0000
LDH R5,#$71 ; R5=$7100
SUB R0,R4,R5 ; Compare R4 to R5
BNE _FAIL8
 
LDL R4,#$8e ; R4=$008e
LDH R4,#$7f ; R4=$7f8e
LDL R4,#$8e ; R4=$008e
LDH R4,#$7f ; R4=$7f8e
LDL R2,#$0c
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
ADDL R4,#$81 ; R4 + $81 => R4
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVC _FAIL8 ; Overflow Flag should be set
BCC _FAIL8 ; Carry Flag should be set
LDL R6,#$0f ; R6=$000f
LDH R6,#$80 ; R6=$800f
SUB R0,R4,R6 ; Compare R4 to R6
BNE _FAIL8
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
ADDL R4,#$81 ; R4 + $81 => R4
BPL _FAIL8 ; Negative Flag should be set
BEQ _FAIL8 ; Zero Flag should be clear
BVC _FAIL8 ; Overflow Flag should be set
BCC _FAIL8 ; Carry Flag should be set
LDL R6,#$0f ; R6=$000f
LDH R6,#$80 ; R6=$800f
SUB R0,R4,R6 ; Compare R4 to R6
BNE _FAIL8
 
 
_END_8
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$10
STB R3,(R2,#0)
SIF
RTS
_END_8
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$10
STB R3,(R2,#0)
 
SIF
RTS
 
_FAIL8
LDL R2,#$00 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$10
STB R3,(R2,#4)
LDL R2,#$00 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$10
STB R3,(R2,#4)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
; Test Load and Store instructions
;-------------------------------------------------------------------------------
_START9
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$11 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$09 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$11 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$09 ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
LDL R1,#$aa ; R1=$00aa
LDH R1,#$7f ; R1=$7faa
LDL R2,#$55 ; R2=$0055
LDH R2,#$6f ; R2=$6f55
LDL R3,#$66 ; R3=$0066
LDH R3,#$5f ; R3=$5f66
LDL R7,#$ff ; R7=$00ff
LDH R7,#$ff ; R7=$ffff
LDL R1,#$aa ; R1=$00aa
LDH R1,#$7f ; R1=$7faa
LDL R2,#$55 ; R2=$0055
LDH R2,#$6f ; R2=$6f55
LDL R3,#$66 ; R3=$0066
LDH R3,#$5f ; R3=$5f66
LDL R7,#$ff ; R7=$00ff
LDH R7,#$ff ; R7=$ffff
 
;Test STB/LDB instruction
STB R1,(R0,#$00) ;
STB R2,(R0,#$01) ;
STB R3,(R0,#$1f) ;
LDL R4,#$00 ; R4=$0000
LDB R5,(R4,#$00) ;
LDB R6,(R4,#$01) ;
LDB R7,(R4,#$1f) ;
CMPL R5,#$aa ;
BNE _FAIL9
CMPL R6,#$55 ;
BNE _FAIL9
CMPL R7,#$66 ;
BNE _FAIL9
LDL R6,#$66 ; R6=$0066
CMP R6,R7 ; Make sure the high byte has been cleared
BNE _FAIL9
;Test STB/LDB instruction ***********************************************
STB R1,(R0,#$00) ;
STB R2,(R0,#$01) ;
STB R3,(R0,#$1f) ;
LDL R4,#$00 ; R4=$0000
LDB R5,(R4,#$00) ;
LDB R6,(R4,#$01) ;
LDB R7,(R4,#$1f) ;
CMPL R5,#$aa ;
BNE _FAIL9
CMPL R6,#$55 ;
BNE _FAIL9
CMPL R7,#$66 ;
BNE _FAIL9
LDL R6,#$66 ; R6=$0066
CMP R6,R7 ; Make sure the high byte has been cleared
BNE _FAIL9
 
;Test STW/LDW instruction
STW R1,(R0,#$04) ; Should be even offsets
STW R2,(R0,#$06) ;
STW R3,(R0,#$0a) ;
LDL R4,#$00 ; R4=$0000
LDL R5,#$00 ; R5=$0000
LDL R6,#$00 ; R6=$0000
LDL R7,#$00 ; R7=$0000
LDW R5,(R4,#$04) ;
LDW R6,(R4,#$06) ;
LDW R7,(R4,#$0a) ;
CMP R1,R5 ;
BNE _FAIL9
CMP R2,R6 ;
BNE _FAIL9
CMP R3,R7 ;
BNE _FAIL9
;Test STW/LDW instruction ***********************************************
STW R1,(R0,#$04) ; Should be even offsets
STW R2,(R0,#$06) ;
STW R3,(R0,#$0a) ;
LDL R4,#$00 ; R4=$0000
LDL R5,#$00 ; R5=$0000
LDL R6,#$00 ; R6=$0000
LDL R7,#$00 ; R7=$0000
LDW R5,(R4,#$04) ;
LDW R6,(R4,#$06) ;
LDW R7,(R4,#$0a) ;
CMP R1,R5 ;
BNE _FAIL9
CMP R2,R6 ;
BNE _FAIL9
CMP R3,R7 ;
BNE _FAIL9
 
;Test STB/LDB instruction
LDL R1,#$cc ; R1=$00cc
LDH R1,#$1f ; R1=$1f66
LDL R2,#$99 ; R2=$0099
LDH R2,#$2f ; R2=$2f99
;Test STB/LDB instruction ***********************************************
LDL R1,#$cc ; R1=$00cc
LDH R1,#$1f ; R1=$1f66
LDL R2,#$99 ; R2=$0099
LDH R2,#$2f ; R2=$2f99
 
LDL R4,#$20 ; R4=$0020 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$07 ; R6=$0007 - odd offset
STB R1,(R4,R5) ;
STB R2,(R4,R6) ;
LDB R5,(R4,R5) ;
LDB R6,(R4,R6) ;
CMPL R5,#$cc ;
BNE _FAIL9
LDL R3,#$99 ; R3=$0099
CMP R3,R6 ; Make sure the high byte has been cleared
BNE _FAIL9
LDL R4,#$20 ; R4=$0020 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$07 ; R6=$0007 - odd offset
STB R1,(R4,R5) ;
STB R2,(R4,R6) ;
LDB R5,(R4,R5) ;
LDB R6,(R4,R6) ;
CMPL R5,#$cc ;
BNE _FAIL9
LDL R3,#$99 ; R3=$0099
CMP R3,R6 ; Make sure the high byte has been cleared
BNE _FAIL9
 
;Test STW/LDW instruction
LDL R1,#$cc ; R1=$00cc
LDH R1,#$1f ; R1=$1f66
LDL R2,#$99 ; R2=$0099
LDH R2,#$2f ; R2=$2f99
;Test STW/LDW instruction ***********************************************
LDL R1,#$cc ; R1=$00cc
LDH R1,#$1f ; R1=$1f66
LDL R2,#$99 ; R2=$0099
LDH R2,#$2f ; R2=$2f99
 
LDL R4,#$30 ; R3=$0030 - Base Address
LDL R5,#$02 ; R5=$0002
LDL R6,#$08 ; R6=$0008
STW R1,(R4,R5) ;
STW R2,(R4,R6) ;
LDW R5,(R4,R5) ;
LDW R6,(R4,R6) ;
CMP R5,R1 ;
BNE _FAIL9
CMP R6,R2 ;
BNE _FAIL9
LDL R4,#$30 ; R3=$0030 - Base Address
LDL R5,#$02 ; R5=$0002
LDL R6,#$08 ; R6=$0008
STW R1,(R4,R5) ;
STW R2,(R4,R6) ;
LDW R5,(R4,R5) ;
LDW R6,(R4,R6) ;
CMP R5,R1 ;
BNE _FAIL9
CMP R6,R2 ;
BNE _FAIL9
 
;Test STB/LDB instruction
LDL R1,#$33 ; R1=$0033
LDH R1,#$1f ; R1=$1f33
LDL R2,#$55 ; R2=$0055
LDH R2,#$2f ; R2=$2f55
;Test STB/LDB instruction ***********************************************
LDL R1,#$33 ; R1=$0033
LDH R1,#$1f ; R1=$1f33
LDL R2,#$55 ; R2=$0055
LDH R2,#$2f ; R2=$2f55
 
LDL R4,#$40 ; R4=$0040 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$07 ; R6=$0007 - odd offset
STB R1,(R4,R5+) ;
STB R2,(R4,R6+) ;
CMPL R5,#$03 ; Test for 1 byte increment
BNE _FAIL9
CMPL R6,#$08 ; Test for 1 byte increment
BNE _FAIL9
LDB R3,(R4,-R5) ;
LDB R7,(R4,-R6) ;
CMPL R5,#$02 ; Test for 1 byte decrement
BNE _FAIL9
CMPL R6,#$07 ; Test for 1 byte decrement
BNE _FAIL9
CMPL R3,#$33 ;
BNE _FAIL9
LDL R3,#$55 ; R3=$0055
CMP R3,R7 ; Make sure the high byte has been cleared
BNE _FAIL9
LDL R4,#$40 ; R4=$0040 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$07 ; R6=$0007 - odd offset
STB R1,(R4,R5+) ;
STB R2,(R4,R6+) ;
CMPL R5,#$03 ; Test for 1 byte increment
BNE _FAIL9
CMPL R6,#$08 ; Test for 1 byte increment
BNE _FAIL9
LDB R3,(R4,-R5) ;
LDB R7,(R4,-R6) ;
CMPL R5,#$02 ; Test for 1 byte decrement
BNE _FAIL9
CMPL R6,#$07 ; Test for 1 byte decrement
BNE _FAIL9
CMPL R3,#$33 ;
BNE _FAIL9
LDL R3,#$55 ; R3=$0055
CMP R3,R7 ; Make sure the high byte has been cleared
BNE _FAIL9
 
;Test STB/LDB instruction
LDL R1,#$66 ; R1=$0066
LDH R1,#$1f ; R1=$1f66
LDL R2,#$99 ; R2=$0099
LDH R2,#$2f ; R2=$2f99
;Test STB/LDB instruction ***********************************************
LDL R1,#$66 ; R1=$0066
LDH R1,#$1f ; R1=$1f66
LDL R2,#$99 ; R2=$0099
LDH R2,#$2f ; R2=$2f99
 
LDL R4,#$50 ; R4=$0050 - Base Address
LDL R5,#$04 ; R5=$0004 - even offset
LDL R6,#$09 ; R6=$0009 - odd offset
STB R1,(R4,-R5) ;
STB R2,(R4,-R6) ;
CMPL R5,#$03 ; Test for 1 byte decrement
BNE _FAIL9
CMPL R6,#$08 ; Test for 1 byte decrement
BNE _FAIL9
LDB R3,(R4,R5+) ;
LDB R7,(R4,R6+) ;
CMPL R5,#$04 ; Test for 1 byte increment
BNE _FAIL9
CMPL R6,#$09 ; Test for 1 byte increment
BNE _FAIL9
CMPL R3,#$66 ;
BNE _FAIL9
LDL R3,#$99 ; R3=$0099
CMP R3,R7 ; Make sure the high byte has been cleared
BNE _FAIL9
LDL R4,#$50 ; R4=$0050 - Base Address
LDL R5,#$04 ; R5=$0004 - even offset
LDL R6,#$09 ; R6=$0009 - odd offset
STB R1,(R4,-R5) ;
STB R2,(R4,-R6) ;
CMPL R5,#$03 ; Test for 1 byte decrement
BNE _FAIL9
CMPL R6,#$08 ; Test for 1 byte decrement
BNE _FAIL9
LDB R3,(R4,R5+) ;
LDB R7,(R4,R6+) ;
CMPL R5,#$04 ; Test for 1 byte increment
BNE _FAIL9
CMPL R6,#$09 ; Test for 1 byte increment
BNE _FAIL9
CMPL R3,#$66 ;
BNE _FAIL9
LDL R3,#$99 ; R3=$0099
CMP R3,R7 ; Make sure the high byte has been cleared
BNE _FAIL9
 
;Test STW/LDW instruction
LDL R1,#$aa ; R1=$00aa
LDH R1,#$1f ; R1=$1faa
LDL R2,#$cc ; R2=$00cc
LDH R2,#$2f ; R2=$2fcc
;Test STW/LDW instruction ***********************************************
LDL R1,#$aa ; R1=$00aa
LDH R1,#$1f ; R1=$1faa
LDL R2,#$cc ; R2=$00cc
LDH R2,#$2f ; R2=$2fcc
 
LDL R4,#$60 ; R4=$0060 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$08 ; R6=$0008
STW R1,(R4,R5+) ;
STW R2,(R4,R6+) ;
CMPL R5,#$04 ; Test for 2 byte increment
BNE _FAIL9
CMPL R6,#$0a ; Test for 2 byte increment
BNE _FAIL9
LDW R3,(R4,-R5) ;
LDW R7,(R4,-R6) ;
CMPL R5,#$02 ; Test for 2 byte decrement
BNE _FAIL9
CMPL R6,#$08 ; Test for 2 byte decrement
BNE _FAIL9
CMP R1,R3 ;
BNE _FAIL9
CMP R2,R7 ;
BNE _FAIL9
LDL R4,#$60 ; R4=$0060 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$08 ; R6=$0008
STW R1,(R4,R5+) ;
STW R2,(R4,R6+) ;
CMPL R5,#$04 ; Test for 2 byte increment
BNE _FAIL9
CMPL R6,#$0a ; Test for 2 byte increment
BNE _FAIL9
LDW R3,(R4,-R5) ;
LDW R7,(R4,-R6) ;
CMPL R5,#$02 ; Test for 2 byte decrement
BNE _FAIL9
CMPL R6,#$08 ; Test for 2 byte decrement
BNE _FAIL9
CMP R1,R3 ;
BNE _FAIL9
CMP R2,R7 ;
BNE _FAIL9
 
_END_9
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$12
STB R3,(R2,#0)
SIF
RTS
;Test STW/LDW instruction ***********************************************
LDL R1,#$66 ; R1=$0066
LDH R1,#$99 ; R1=$9966
LDL R2,#$33 ; R2=$0033
LDH R2,#$75 ; R2=$7533
 
LDL R4,#$80 ; R4=$0080 - Base Address
LDL R5,#$02 ; R5=$0002 - even offset
LDL R6,#$08 ; R6=$0008
STW R1,(R4,-R5) ;
STW R2,(R4,-R6) ;
CMPL R5,#$00 ; Test for 2 byte increment
BNE _FAIL9
CMPL R6,#$06 ; Test for 2 byte increment
BNE _FAIL9
LDW R3,(R4,R5+) ;
LDW R7,(R4,R6+) ;
CMPL R5,#$02 ; Test for 2 byte decrement
BNE _FAIL9
CMPL R6,#$08 ; Test for 2 byte decrement
BNE _FAIL9
CMP R1,R3 ;
BNE _FAIL9
CMP R2,R7 ;
BNE _FAIL9
 
_END_9
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$12
STB R3,(R2,#0)
 
SIF
RTS
 
_FAIL9
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$12
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$12
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
; Test Semaphore instructions
;-------------------------------------------------------------------------------
_START10
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$13 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$0a ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$13 ; Checkpoint Value
STB R3,(R2,#0)
LDL R3,#$0a ; Thread Value
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
LDL R1,#$5 ; R1=$0005
LDL R1,#$5 ; R1=$0005
 
;Test SSEM instruction
SSEM #7 ; semaphores
BCC _FAIL10 ; Should be set
SSEM R1 ; semaphores
BCC _FAIL10 ; Should be set
SSEM #6 ; semaphore has been set by host
BCS _FAIL10 ; Should be clear
CSEM #7 ; semaphore
CSEM R1 ; semaphore #5
; Host will test that these semaphores are clear
;Test SSEM instruction **************************************************
SSEM #7 ; semaphores
BCC _FAIL10 ; Should be set
SSEM R1 ; semaphores
BCC _FAIL10 ; Should be set
 
SSEM #3 ; set this semaphore for the host to test
SSEM #6 ; semaphore has been set by host
BCS _FAIL10 ; Should be clear
 
CSEM #7 ; semaphore
CSEM R1 ; semaphore #5
; Host will test that these semaphores are clear
 
_END_10
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$14
STB R3,(R2,#0)
SIF
RTS
SSEM #3 ; set this semaphore for the host to test
 
 
_END_10
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
LDH R2,#$80
LDL R3,#$14
STB R3,(R2,#0)
 
SIF
RTS
 
_FAIL10
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$14
STB R3,(R2,#0)
LDL R2,#$04 ; Sent Message to Testbench Error Register
LDH R2,#$80
LDL R3,#$14
STB R3,(R2,#0)
 
SIF
RTS
RTS
 
 
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
TFR R2,CCR ; R2 = CCR
 
 
;empty line
 
BACK_
 
 
SIF R7
BRK
SIF R7
BRK
 
ORG $8000 ; Special Testbench Addresses
_BENCH DS.W 8
ORG $8000 ; Special Testbench Addresses
_BENCH DS.W 8
 
 
 
/trunk/README.txt
3,6 → 3,42
////////////////////////////////////////////////////////////////////////////////
// SVN tag: None
 
November 21,2011
RTL - No Change
 
Code cleanup, converted tabs to blanks. Added code to instruction test to cover
a few base instructions that weren't being tested. Changed instance name of
semaphore registers from "bit" to "sbit" to be compatible with System Verilog.
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
My current idea list for enhancements is:
 
Add to the software apps:
a - It should be possible to write software to emulate some simple hardware modules such as I2C, SPI and UART.
b - DMA controller software
c - Find open source C compiler for Xgate
d - ???
 
It would be interesting to integrate the Xgate with some of the other OpenCores peripheral modules. Again there would be some related software development for verification. The ultimate goal would be to to create full-blown drivers for these modules.
a - Integrate Xgate with I2C controller and develop software to support SMBus and PMBus protocols.
b - ???
 
Another interesting integration project would be to build a processor core with the OpenRISC as the host and the Xgate working as a co-processor. Some type of memory controller module would need to be developed so the Xgate could have some semiprivate RAM to run code from. Also a separate slave bus would be nice to isolate peripherals that could be managed mostly by the Xgate. Some software development would be required for both OpenRISC and Xgate to verify the functionality.
 
Develop hardware debug module. Survey Freescale debugger and other debugger specifications and develop hardware debugger/specification that can optionally be connected to the Xgate module. The debugger should be broken into at least two modules, one the actual debug interface and the second a flexible serial interface adaptor. There are already JTAG modules in the design database that I had thought might be used as one possible interface to the debugger. (A great project on it's own would be to develop a JTAG module that meets the latest JTAG specification including the single wire interface.)
 
Upgrade Xgate to the enhanced version that Freescale now ships. This includes an alternate register set so the Xgate can switch in a few cycles from a low priority interrupt to a higher priority interrupt and then return to the low priority interrupt process.
 
Improvements to the architecture to support high speed operation. The current code was developed in a piecemeal fashion without much pre-planing on the data path from/to RAM and the internal registers.
 
System Verilog class based constrained random verification environment.
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// SVN tag: None
 
August 11,2010
RTL - No Change
 

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