URL
https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
Subversion Repositories xge_mac
Compare Revisions
- This comparison shows the changes necessary to convert path
/xge_mac/trunk/rtl
- from Rev 10 to Rev 7
- ↔ Reverse comparison
Rev 10 → Rev 7
/verilog/tx_dequeue.v
113,11 → 113,11
reg [63:0] next_xgxs_txd; |
reg [7:0] next_xgxs_txc; |
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reg [2:0] curr_state_enc; |
reg [2:0] next_state_enc; |
reg [2:0] curr_state; |
reg [2:0] next_state; |
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reg [0:0] curr_state_pad; |
reg [0:0] next_state_pad; |
reg [0:0] curr_state_rd; |
reg [0:0] next_state_rd; |
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reg start_on_lane0; |
reg next_start_on_lane0; |
173,8 → 173,8
SM_IFG = 3'd6; |
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parameter [0:0] |
SM_PAD_EQ = 1'd0, |
SM_PAD_PAD = 1'd1; |
SM_RD_EQ = 1'd0, |
SM_RD_PAD = 1'd1; |
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//--- |
225,7 → 225,7
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if (reset_xgmii_tx_n == 1'b0) begin |
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curr_state_enc <= SM_IDLE; |
curr_state <= SM_IDLE; |
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start_on_lane0 <= 1'b1; |
ifg_deficit <= 3'b0; |
250,7 → 250,7
end |
else begin |
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curr_state_enc <= next_state_enc; |
curr_state <= next_state; |
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start_on_lane0 <= next_start_on_lane0; |
ifg_deficit <= next_ifg_deficit; |
296,13 → 296,13
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end |
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always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop |
always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state or eop |
or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add |
or ifg_deficit or start_on_lane0 or status_local_fault_ctx |
or txhfifo_ralmost_empty or txhfifo_rdata_d1 |
or txhfifo_rempty or txhfifo_rstatus) begin |
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next_state_enc = curr_state_enc; |
next_state = curr_state; |
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next_start_on_lane0 = start_on_lane0; |
next_ifg_deficit = ifg_deficit; |
319,7 → 319,7
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next_frame_available = frame_available; |
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case (curr_state_enc) |
case (curr_state) |
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SM_IDLE: |
begin |
335,7 → 335,7
!status_local_fault_ctx && !status_local_fault_ctx) begin |
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txhfifo_ren = 1'b1; |
next_state_enc = SM_PREAMBLE; |
next_state = SM_PREAMBLE; |
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end |
else begin |
359,13 → 359,13
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txhfifo_ren = 1'b1; |
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next_state_enc = SM_TX; |
next_state = SM_TX; |
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end |
else begin |
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next_frame_available = 1'b0; |
next_state_enc = SM_IDLE; |
next_state = SM_IDLE; |
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end |
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399,7 → 399,7
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txhfifo_ren = 1'b0; |
next_frame_available = !txhfifo_ralmost_empty; |
next_state_enc = SM_EOP; |
next_state = SM_EOP; |
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end |
else if (txhfifo_rempty || txhfifo_rstatus[`TXSTATUS_SOP]) begin |
407,7 → 407,7
// Failure condition, we did not see EOP and there |
// is no more data in fifo or SOP, force end of packet transmit. |
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next_state_enc = SM_TERM_FAIL; |
next_state = SM_TERM_FAIL; |
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end |
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600,24 → 600,24
// Skip idle state if needed. |
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if (next_ifg_8b2_add) begin |
next_state_enc = SM_IFG; |
next_state = SM_IFG; |
end |
else if (next_ifg_8b_add) begin |
next_state_enc = SM_IDLE; |
next_state = SM_IDLE; |
end |
else begin |
txhfifo_ren = 1'b1; |
next_state_enc = SM_PREAMBLE; |
next_state = SM_PREAMBLE; |
end |
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end |
else begin |
next_state_enc = SM_IFG; |
next_state = SM_IFG; |
end |
end |
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if (|eop[7:3]) begin |
next_state_enc = SM_TERM; |
next_state = SM_TERM; |
end |
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end |
658,13 → 658,13
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if (frame_available && !ifg_8b_add) begin |
txhfifo_ren = 1'b1; |
next_state_enc = SM_PREAMBLE; |
next_state = SM_PREAMBLE; |
end |
else if (frame_available) begin |
next_state_enc = SM_IDLE; |
next_state = SM_IDLE; |
end |
else begin |
next_state_enc = SM_IFG; |
next_state = SM_IFG; |
end |
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end |
674,7 → 674,7
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next_xgxs_txd = {{7{`IDLE}}, `TERMINATE}; |
next_xgxs_txc = 8'b11111111; |
next_state_enc = SM_IFG; |
next_state = SM_IFG; |
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end |
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681,13 → 681,13
SM_IFG: |
begin |
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next_state_enc = SM_IDLE; |
next_state = SM_IDLE; |
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end |
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default: |
begin |
next_state_enc = SM_IDLE; |
next_state = SM_IDLE; |
end |
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endcase |
706,11 → 706,11
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end |
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always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata |
always @(/*AS*/byte_cnt or curr_state_rd or txdfifo_rdata |
or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus |
or txhfifo_walmost_full) begin |
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next_state_pad = curr_state_pad; |
next_state_rd = curr_state_rd; |
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next_txhfifo_wdata = txdfifo_rdata; |
next_txhfifo_wstatus = txdfifo_rstatus; |
718,9 → 718,9
txdfifo_ren = 1'b0; |
next_txhfifo_wen = 1'b0; |
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case (curr_state_pad) |
case (curr_state_rd) |
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SM_PAD_EQ: begin |
SM_RD_EQ: begin |
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//--- |
750,7 → 750,7
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next_txhfifo_wstatus = `TXSTATUS_NONE; |
txdfifo_ren = 1'b0; |
next_state_pad = SM_PAD_PAD; |
next_state_rd = SM_RD_PAD; |
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end |
else if (byte_cnt == 14'd56 && |
787,7 → 787,7
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end |
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SM_PAD_PAD: begin |
SM_RD_PAD: begin |
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//--- |
// Pad packet to 64 bytes by writting zeros to holding fifo. |
807,7 → 807,7
next_txhfifo_wstatus[`TXSTATUS_EOP] = 1'b1; |
next_txhfifo_wstatus[2:0] = 3'd4; |
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next_state_pad = SM_PAD_EQ; |
next_state_rd = SM_RD_EQ; |
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end |
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817,7 → 817,7
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default: |
begin |
next_state_pad = SM_PAD_EQ; |
next_state_rd = SM_RD_EQ; |
end |
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endcase |
829,7 → 829,7
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if (reset_xgmii_tx_n == 1'b0) begin |
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curr_state_pad <= SM_PAD_EQ; |
curr_state_rd <= SM_RD_EQ; |
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txdfifo_ren_d1 <= 1'b0; |
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846,7 → 846,7
end |
else begin |
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curr_state_pad <= next_state_pad; |
curr_state_rd <= next_state_rd; |
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txdfifo_ren_d1 <= txdfifo_ren; |
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