OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xge_mac/trunk/rtl
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/include/defines.v
51,7 → 51,7
`define SEQUENCE 8'h9c
`define SFD 8'hd5
`define START 8'hfb
`define TERMINATE 8'hfd
`define TERMINATE 8'hfd
`define ERROR 8'hfe
 
 
107,3 → 107,6
`define MEM_AUTO_MEDIUM 2
 
 
// Changed system packet interface to big endian (12/12/2009)
// Comment out to use legacy mode
`define BIGENDIAN
/verilog/sync_clk_core.v
52,12 → 52,8
 
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
//wire [0:0] sig_out;
 
/verilog/sync_clk_xgmii_tx.v
40,10 → 40,9
 
module sync_clk_xgmii_tx(/*AUTOARG*/
// Outputs
ctrl_tx_enable_ctx, status_local_fault_ctx,
status_remote_fault_ctx,
ctrl_tx_enable_ctx, status_local_fault_ctx, status_remote_fault_ctx,
// Inputs
clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable,
clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable,
status_local_fault_crx, status_remote_fault_crx
);
 
61,18 → 60,14
output status_remote_fault_ctx;
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
wire [2:0] sig_out;
 
assign {ctrl_tx_enable_ctx,
status_local_fault_ctx,
status_remote_fault_ctx} = sig_out;
assign ctrl_tx_enable_ctx = sig_out[2];
assign status_local_fault_ctx = sig_out[1];
assign status_remote_fault_ctx = sig_out[0];
 
meta_sync #(.DWIDTH (3)) meta_sync0 (
// Outputs
87,4 → 82,3
}));
 
endmodule
 
/verilog/rx_enqueue.v
40,14 → 40,14
 
module rx_enqueue(/*AUTOARG*/
// Outputs
rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren,
rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
remote_fault_msg_det, status_crc_error_tog,
status_fragment_error_tog, status_rxdfifo_ovflow_tog,
status_pause_frame_rx_tog,
rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren,
rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
remote_fault_msg_det, status_crc_error_tog,
status_fragment_error_tog, status_rxdfifo_ovflow_tog,
status_pause_frame_rx_tog,
// Inputs
clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc,
rxdfifo_wfull, rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull,
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
rxhfifo_ralmost_empty
);
 
108,8 → 108,6
// End of automatics
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
 
reg [63:32] xgmii_rxd_d1;
/verilog/tx_enqueue.v
40,10 → 40,10
 
module tx_enqueue(/*AUTOARG*/
// Outputs
pkt_tx_full, txdfifo_wdata, txdfifo_wstatus, txdfifo_wen,
status_txdfifo_ovflow_tog,
pkt_tx_full, txdfifo_wdata, txdfifo_wstatus, txdfifo_wen,
status_txdfifo_ovflow_tog,
// Inputs
clk_156m25, reset_156m25_n, pkt_tx_data, pkt_tx_val, pkt_tx_sop,
clk_156m25, reset_156m25_n, pkt_tx_data, pkt_tx_val, pkt_tx_sop,
pkt_tx_eop, pkt_tx_mod, txdfifo_wfull, txdfifo_walmost_full
);
 
53,7 → 53,7
 
input clk_156m25;
input reset_156m25_n;
 
input [63:0] pkt_tx_data;
input pkt_tx_val;
input pkt_tx_sop;
80,8 → 80,6
// End of automatics
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
 
reg txd_ovflow;
112,7 → 110,7
 
//---
// FIFO errors, used to generate interrupts
 
if (next_txd_ovflow && !txd_ovflow) begin
status_txdfifo_ovflow_tog <= ~status_txdfifo_ovflow_tog;
end
125,14 → 123,20
or pkt_tx_val or txd_ovflow or txdfifo_wfull) begin
 
txdfifo_wstatus = `TXSTATUS_NONE;
txdfifo_wdata = pkt_tx_data;
txdfifo_wen = pkt_tx_val;
 
next_txd_ovflow = txd_ovflow;
 
`ifdef BIGENDIAN
txdfifo_wdata = {pkt_tx_data[7:0], pkt_tx_data[15:8], pkt_tx_data[23:16], pkt_tx_data[31:24],
pkt_tx_data[39:32], pkt_tx_data[47:40], pkt_tx_data[55:48],
pkt_tx_data[63:56]};
`else
txdfifo_wdata = pkt_tx_data;
`endif
 
// Write SOP marker to fifo.
 
if (pkt_tx_val && pkt_tx_sop) begin
 
txdfifo_wstatus[`TXSTATUS_SOP] = 1'b1;
139,9 → 143,9
 
end
 
 
// Write EOP marker to fifo.
 
if (pkt_tx_val) begin
 
if (pkt_tx_eop) begin
172,4 → 176,3
 
 
endmodule
 
/verilog/rx_data_fifo.v
40,10 → 40,10
 
module rx_data_fifo(/*AUTOARG*/
// Outputs
rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty,
rxdfifo_ralmost_empty,
rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty,
rxdfifo_ralmost_empty,
// Inputs
clk_xgmii_rx, clk_156m25, reset_xgmii_rx_n, reset_156m25_n,
clk_xgmii_rx, clk_156m25, reset_xgmii_rx_n, reset_156m25_n,
rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxdfifo_ren
);
 
/verilog/tx_data_fifo.v
40,10 → 40,10
 
module tx_data_fifo(/*AUTOARG*/
// Outputs
txdfifo_wfull, txdfifo_walmost_full, txdfifo_rdata,
txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
txdfifo_wfull, txdfifo_walmost_full, txdfifo_rdata, txdfifo_rstatus,
txdfifo_rempty, txdfifo_ralmost_empty,
// Inputs
clk_xgmii_tx, clk_156m25, reset_xgmii_tx_n, reset_156m25_n,
clk_xgmii_tx, clk_156m25, reset_xgmii_tx_n, reset_156m25_n,
txdfifo_wdata, txdfifo_wstatus, txdfifo_wen, txdfifo_ren
);
 
/verilog/wishbone_if.v
40,12 → 40,11
 
module wishbone_if(/*AUTOARG*/
// Outputs
wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,
wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,
// Inputs
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i,
wb_cyc_i, status_crc_error, status_fragment_error,
status_txdfifo_ovflow, status_txdfifo_udflow,
status_rxdfifo_ovflow, status_rxdfifo_udflow,
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
status_pause_frame_rx, status_local_fault, status_remote_fault
);
 
99,8 → 98,6
 
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
wire [8:0] int_sources;
 
/verilog/sync_clk_wb.v
40,24 → 40,23
 
module sync_clk_wb(/*AUTOARG*/
// Outputs
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
status_txdfifo_udflow, status_rxdfifo_ovflow,
status_rxdfifo_udflow, status_pause_frame_rx, status_local_fault,
status_remote_fault,
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
status_pause_frame_rx, status_local_fault, status_remote_fault,
// Inputs
wb_clk_i, wb_rst_i, status_crc_error_tog,
status_fragment_error_tog, status_txdfifo_ovflow_tog,
status_txdfifo_udflow_tog, status_rxdfifo_ovflow_tog,
status_rxdfifo_udflow_tog, status_pause_frame_rx_tog,
status_local_fault_crx, status_remote_fault_crx
wb_clk_i, wb_rst_i, status_crc_error_tog, status_fragment_error_tog,
status_txdfifo_ovflow_tog, status_txdfifo_udflow_tog,
status_rxdfifo_ovflow_tog, status_rxdfifo_udflow_tog,
status_pause_frame_rx_tog, status_local_fault_crx,
status_remote_fault_crx
);
 
input wb_clk_i;
input wb_rst_i;
input status_crc_error_tog;
input status_fragment_error_tog;
 
input status_crc_error_tog;
input status_fragment_error_tog;
 
input status_txdfifo_ovflow_tog;
 
input status_txdfifo_udflow_tog;
73,7 → 72,7
 
output status_crc_error;
output status_fragment_error;
 
output status_txdfifo_ovflow;
 
output status_txdfifo_udflow;
88,26 → 87,22
output status_remote_fault;
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
wire [6:0] sig_out1;
wire [1:0] sig_out2;
 
assign {status_crc_error,
status_fragment_error,
status_txdfifo_ovflow,
status_txdfifo_udflow,
status_rxdfifo_ovflow,
status_rxdfifo_udflow,
status_pause_frame_rx} = sig_out1;
assign status_crc_error = sig_out1[6];
assign status_fragment_error = sig_out1[5];
assign status_txdfifo_ovflow = sig_out1[4];
assign status_txdfifo_udflow = sig_out1[3];
assign status_rxdfifo_ovflow = sig_out1[2];
assign status_rxdfifo_udflow = sig_out1[1];
assign status_pause_frame_rx = sig_out1[0];
 
assign {status_local_fault,
status_remote_fault} = sig_out2;
assign status_local_fault = sig_out2[1];
assign status_remote_fault = sig_out2[0];
 
meta_sync #(.DWIDTH (7), .EDGE_DETECT (1)) meta_sync0 (
// Outputs
137,4 → 132,3
}));
 
endmodule
 
/verilog/rx_hold_fifo.v
40,10 → 40,10
 
module rx_hold_fifo(/*AUTOARG*/
// Outputs
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
rxhfifo_ralmost_empty,
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
rxhfifo_ralmost_empty,
// Inputs
clk_xgmii_rx, reset_xgmii_rx_n, rxhfifo_wdata, rxhfifo_wstatus,
clk_xgmii_rx, reset_xgmii_rx_n, rxhfifo_wdata, rxhfifo_wstatus,
rxhfifo_wen, rxhfifo_ren
);
 
/verilog/xge_mac.v
40,13 → 40,13
 
module xge_mac(/*AUTOARG*/
// Outputs
xgmii_txd, xgmii_txc, wb_int_o, wb_dat_o, wb_ack_o, pkt_tx_full,
pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop,
pkt_rx_data, pkt_rx_avail,
xgmii_txd, xgmii_txc, wb_int_o, wb_dat_o, wb_ack_o, pkt_tx_full,
pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop,
pkt_rx_data, pkt_rx_avail,
// Inputs
xgmii_rxd, xgmii_rxc, wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i,
wb_cyc_i, wb_clk_i, wb_adr_i, reset_xgmii_tx_n, reset_xgmii_rx_n,
reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop,
xgmii_rxd, xgmii_rxc, wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i,
wb_cyc_i, wb_clk_i, wb_adr_i, reset_xgmii_tx_n, reset_xgmii_rx_n,
reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop,
pkt_tx_data, pkt_rx_ren, clk_xgmii_tx, clk_xgmii_rx, clk_156m25
);
 
205,34 → 205,34
rx_data_fifo rx_data_fifo0(/*AUTOINST*/
// Outputs
.rxdfifo_wfull(rxdfifo_wfull),
.rxdfifo_rdata(rxdfifo_rdata[63:0]),
.rxdfifo_rstatus(rxdfifo_rstatus[7:0]),
.rxdfifo_rempty(rxdfifo_rempty),
.rxdfifo_wfull (rxdfifo_wfull),
.rxdfifo_rdata (rxdfifo_rdata[63:0]),
.rxdfifo_rstatus (rxdfifo_rstatus[7:0]),
.rxdfifo_rempty (rxdfifo_rempty),
.rxdfifo_ralmost_empty(rxdfifo_ralmost_empty),
// Inputs
.clk_xgmii_rx(clk_xgmii_rx),
.clk_156m25 (clk_156m25),
.reset_xgmii_rx_n(reset_xgmii_rx_n),
.reset_156m25_n(reset_156m25_n),
.rxdfifo_wdata(rxdfifo_wdata[63:0]),
.rxdfifo_wstatus(rxdfifo_wstatus[7:0]),
.rxdfifo_wen (rxdfifo_wen),
.rxdfifo_ren (rxdfifo_ren));
.clk_xgmii_rx (clk_xgmii_rx),
.clk_156m25 (clk_156m25),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
.reset_156m25_n (reset_156m25_n),
.rxdfifo_wdata (rxdfifo_wdata[63:0]),
.rxdfifo_wstatus (rxdfifo_wstatus[7:0]),
.rxdfifo_wen (rxdfifo_wen),
.rxdfifo_ren (rxdfifo_ren));
 
rx_hold_fifo rx_hold_fifo0(/*AUTOINST*/
// Outputs
.rxhfifo_rdata(rxhfifo_rdata[63:0]),
.rxhfifo_rstatus(rxhfifo_rstatus[7:0]),
.rxhfifo_rempty(rxhfifo_rempty),
.rxhfifo_rdata (rxhfifo_rdata[63:0]),
.rxhfifo_rstatus (rxhfifo_rstatus[7:0]),
.rxhfifo_rempty (rxhfifo_rempty),
.rxhfifo_ralmost_empty(rxhfifo_ralmost_empty),
// Inputs
.clk_xgmii_rx(clk_xgmii_rx),
.reset_xgmii_rx_n(reset_xgmii_rx_n),
.rxhfifo_wdata(rxhfifo_wdata[63:0]),
.rxhfifo_wstatus(rxhfifo_wstatus[7:0]),
.rxhfifo_wen (rxhfifo_wen),
.rxhfifo_ren (rxhfifo_ren));
.clk_xgmii_rx (clk_xgmii_rx),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
.rxhfifo_wdata (rxhfifo_wdata[63:0]),
.rxhfifo_wstatus (rxhfifo_wstatus[7:0]),
.rxhfifo_wen (rxhfifo_wen),
.rxhfifo_ren (rxhfifo_ren));
 
tx_enqueue tx_eq0 (/*AUTOINST*/
// Outputs
281,37 → 281,37
 
tx_data_fifo tx_data_fifo0(/*AUTOINST*/
// Outputs
.txdfifo_wfull(txdfifo_wfull),
.txdfifo_wfull (txdfifo_wfull),
.txdfifo_walmost_full(txdfifo_walmost_full),
.txdfifo_rdata(txdfifo_rdata[63:0]),
.txdfifo_rstatus(txdfifo_rstatus[7:0]),
.txdfifo_rempty(txdfifo_rempty),
.txdfifo_rdata (txdfifo_rdata[63:0]),
.txdfifo_rstatus (txdfifo_rstatus[7:0]),
.txdfifo_rempty (txdfifo_rempty),
.txdfifo_ralmost_empty(txdfifo_ralmost_empty),
// Inputs
.clk_xgmii_tx(clk_xgmii_tx),
.clk_156m25 (clk_156m25),
.reset_xgmii_tx_n(reset_xgmii_tx_n),
.reset_156m25_n(reset_156m25_n),
.txdfifo_wdata(txdfifo_wdata[63:0]),
.txdfifo_wstatus(txdfifo_wstatus[7:0]),
.txdfifo_wen (txdfifo_wen),
.txdfifo_ren (txdfifo_ren));
.clk_xgmii_tx (clk_xgmii_tx),
.clk_156m25 (clk_156m25),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
.reset_156m25_n (reset_156m25_n),
.txdfifo_wdata (txdfifo_wdata[63:0]),
.txdfifo_wstatus (txdfifo_wstatus[7:0]),
.txdfifo_wen (txdfifo_wen),
.txdfifo_ren (txdfifo_ren));
 
tx_hold_fifo tx_hold_fifo0(/*AUTOINST*/
// Outputs
.txhfifo_wfull(txhfifo_wfull),
.txhfifo_wfull (txhfifo_wfull),
.txhfifo_walmost_full(txhfifo_walmost_full),
.txhfifo_rdata(txhfifo_rdata[63:0]),
.txhfifo_rstatus(txhfifo_rstatus[7:0]),
.txhfifo_rempty(txhfifo_rempty),
.txhfifo_rdata (txhfifo_rdata[63:0]),
.txhfifo_rstatus (txhfifo_rstatus[7:0]),
.txhfifo_rempty (txhfifo_rempty),
.txhfifo_ralmost_empty(txhfifo_ralmost_empty),
// Inputs
.clk_xgmii_tx(clk_xgmii_tx),
.reset_xgmii_tx_n(reset_xgmii_tx_n),
.txhfifo_wdata(txhfifo_wdata[63:0]),
.txhfifo_wstatus(txhfifo_wstatus[7:0]),
.txhfifo_wen (txhfifo_wen),
.txhfifo_ren (txhfifo_ren));
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
.txhfifo_wdata (txhfifo_wdata[63:0]),
.txhfifo_wstatus (txhfifo_wstatus[7:0]),
.txhfifo_wen (txhfifo_wen),
.txhfifo_ren (txhfifo_ren));
 
fault_sm fault_sm0(/*AUTOINST*/
// Outputs
325,19 → 325,19
 
sync_clk_wb sync_clk_wb0(/*AUTOINST*/
// Outputs
.status_crc_error(status_crc_error),
.status_fragment_error(status_fragment_error),
.status_txdfifo_ovflow(status_txdfifo_ovflow),
.status_txdfifo_udflow(status_txdfifo_udflow),
.status_rxdfifo_ovflow(status_rxdfifo_ovflow),
.status_rxdfifo_udflow(status_rxdfifo_udflow),
.status_pause_frame_rx(status_pause_frame_rx),
.status_local_fault(status_local_fault),
.status_remote_fault(status_remote_fault),
.status_crc_error (status_crc_error),
.status_fragment_error (status_fragment_error),
.status_txdfifo_ovflow (status_txdfifo_ovflow),
.status_txdfifo_udflow (status_txdfifo_udflow),
.status_rxdfifo_ovflow (status_rxdfifo_ovflow),
.status_rxdfifo_udflow (status_rxdfifo_udflow),
.status_pause_frame_rx (status_pause_frame_rx),
.status_local_fault (status_local_fault),
.status_remote_fault (status_remote_fault),
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.status_crc_error_tog(status_crc_error_tog),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.status_crc_error_tog (status_crc_error_tog),
.status_fragment_error_tog(status_fragment_error_tog),
.status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog),
.status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
353,40 → 353,40
.status_local_fault_ctx(status_local_fault_ctx),
.status_remote_fault_ctx(status_remote_fault_ctx),
// Inputs
.clk_xgmii_tx(clk_xgmii_tx),
.reset_xgmii_tx_n(reset_xgmii_tx_n),
.ctrl_tx_enable(ctrl_tx_enable),
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
.ctrl_tx_enable (ctrl_tx_enable),
.status_local_fault_crx(status_local_fault_crx),
.status_remote_fault_crx(status_remote_fault_crx));
 
sync_clk_core sync_clk_core0(/*AUTOINST*/
// Inputs
.clk_xgmii_tx(clk_xgmii_tx),
.reset_xgmii_tx_n(reset_xgmii_tx_n));
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_tx_n (reset_xgmii_tx_n));
 
wishbone_if wishbone_if0(/*AUTOINST*/
// Outputs
.wb_dat_o (wb_dat_o[31:0]),
.wb_ack_o (wb_ack_o),
.wb_int_o (wb_int_o),
.ctrl_tx_enable(ctrl_tx_enable),
.wb_dat_o (wb_dat_o[31:0]),
.wb_ack_o (wb_ack_o),
.wb_int_o (wb_int_o),
.ctrl_tx_enable (ctrl_tx_enable),
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wb_adr_i[7:0]),
.wb_dat_i (wb_dat_i[31:0]),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_stb_i),
.wb_cyc_i (wb_cyc_i),
.status_crc_error(status_crc_error),
.status_fragment_error(status_fragment_error),
.status_txdfifo_ovflow(status_txdfifo_ovflow),
.status_txdfifo_udflow(status_txdfifo_udflow),
.status_rxdfifo_ovflow(status_rxdfifo_ovflow),
.status_rxdfifo_udflow(status_rxdfifo_udflow),
.status_pause_frame_rx(status_pause_frame_rx),
.status_local_fault(status_local_fault),
.status_remote_fault(status_remote_fault));
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wb_adr_i[7:0]),
.wb_dat_i (wb_dat_i[31:0]),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_stb_i),
.wb_cyc_i (wb_cyc_i),
.status_crc_error (status_crc_error),
.status_fragment_error (status_fragment_error),
.status_txdfifo_ovflow (status_txdfifo_ovflow),
.status_txdfifo_udflow (status_txdfifo_udflow),
.status_rxdfifo_ovflow (status_rxdfifo_ovflow),
.status_rxdfifo_udflow (status_rxdfifo_udflow),
.status_pause_frame_rx (status_pause_frame_rx),
.status_local_fault (status_local_fault),
.status_remote_fault (status_remote_fault));
 
endmodule
 
/verilog/tx_hold_fifo.v
40,10 → 40,10
 
module tx_hold_fifo(/*AUTOARG*/
// Outputs
txhfifo_wfull, txhfifo_walmost_full, txhfifo_rdata,
txhfifo_rstatus, txhfifo_rempty, txhfifo_ralmost_empty,
txhfifo_wfull, txhfifo_walmost_full, txhfifo_rdata, txhfifo_rstatus,
txhfifo_rempty, txhfifo_ralmost_empty,
// Inputs
clk_xgmii_tx, reset_xgmii_tx_n, txhfifo_wdata, txhfifo_wstatus,
clk_xgmii_tx, reset_xgmii_tx_n, txhfifo_wdata, txhfifo_wstatus,
txhfifo_wen, txhfifo_ren
);
 
/verilog/rx_dequeue.v
40,16 → 40,16
 
module rx_dequeue(/*AUTOARG*/
// Outputs
rxdfifo_ren, pkt_rx_data, pkt_rx_val, pkt_rx_sop, pkt_rx_eop,
pkt_rx_err, pkt_rx_mod, pkt_rx_avail, status_rxdfifo_udflow_tog,
rxdfifo_ren, pkt_rx_data, pkt_rx_val, pkt_rx_sop, pkt_rx_eop,
pkt_rx_err, pkt_rx_mod, pkt_rx_avail, status_rxdfifo_udflow_tog,
// Inputs
clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus,
clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus,
rxdfifo_rempty, rxdfifo_ralmost_empty, pkt_rx_ren
);
 
input clk_156m25;
input reset_156m25_n;
 
input [63:0] rxdfifo_rdata;
input [7:0] rxdfifo_rstatus;
input rxdfifo_rempty;
58,7 → 58,7
input pkt_rx_ren;
 
output rxdfifo_ren;
 
output [63:0] pkt_rx_data;
output pkt_rx_val;
output pkt_rx_sop;
84,8 → 84,6
reg end_eop;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
 
// End eop to force one cycle between packets
124,7 → 122,7
// packet. The fifo is designed to output data early. On last read,
// data from next packet will appear at the output of fifo. Modulus
// of packet length is in lower bits.
 
pkt_rx_eop <= rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP];
pkt_rx_mod <= {3{rxdfifo_ren & rxdfifo_rstatus[`RXSTATUS_EOP]}} & rxdfifo_rstatus[2:0];
 
133,7 → 131,18
 
if (rxdfifo_ren) begin
 
`ifdef BIGENDIAN
pkt_rx_data <= {rxdfifo_rdata[7:0],
rxdfifo_rdata[15:8],
rxdfifo_rdata[23:16],
rxdfifo_rdata[31:24],
rxdfifo_rdata[39:32],
rxdfifo_rdata[47:40],
rxdfifo_rdata[55:48],
rxdfifo_rdata[63:56]};
`else
pkt_rx_data <= rxdfifo_rdata;
`endif
 
end
 
173,7 → 182,7
 
//---
// EOP indication at the end of the frame. Cleared otherwise.
 
if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP]) begin
end_eop <= 1'b1;
end
185,7 → 194,7
 
//---
// FIFO errors, used to generate interrupts
 
if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
status_rxdfifo_udflow_tog <= ~status_rxdfifo_udflow_tog;
end
194,4 → 203,3
end
 
endmodule
 
/verilog/tx_dequeue.v
40,13 → 40,13
 
module tx_dequeue(/*AUTOARG*/
// Outputs
txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
// Inputs
clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
txhfifo_ralmost_empty, txhfifo_wfull, txhfifo_walmost_full
);
`include "CRC32_D64.v"
103,8 → 103,6
// End of automatics
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
 
reg [63:0] xgxs_txd;
/verilog/fault_sm.v
40,9 → 40,9
 
module fault_sm(/*AUTOARG*/
// Outputs
status_local_fault_crx, status_remote_fault_crx,
status_local_fault_crx, status_remote_fault_crx,
// Inputs
clk_xgmii_rx, reset_xgmii_rx_n, local_fault_msg_det,
clk_xgmii_rx, reset_xgmii_rx_n, local_fault_msg_det,
remote_fault_msg_det
);
 
73,8 → 73,6
reg [1:0] seq_add;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
 
 
parameter [1:0]

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.