URL
https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
Subversion Repositories xge_mac
Compare Revisions
- This comparison shows the changes necessary to convert path
/xge_mac/trunk/rtl
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/verilog/rx_enqueue.v
57,12 → 57,12
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input clk_xgmii_rx; |
input reset_xgmii_rx_n; |
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input [63:0] xgmii_rxd; |
input [7:0] xgmii_rxc; |
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input rxdfifo_wfull; |
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input [63:0] rxhfifo_rdata; |
input [7:0] rxhfifo_rstatus; |
input rxhfifo_rempty; |
70,7 → 70,7
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output [63:0] rxdfifo_wdata; |
output [7:0] rxdfifo_wstatus; |
output rxdfifo_wen; |
output rxdfifo_wen; |
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output rxhfifo_ren; |
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171,6 → 171,38
SM_IDLE = 3'd0, |
SM_RX = 3'd1; |
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// count the number of set bits in a nibble |
function [2:0] bit_cnt4; |
input [3:0] bits; |
begin |
case (bits) |
0: bit_cnt4 = 0; |
1: bit_cnt4 = 1; |
2: bit_cnt4 = 1; |
3: bit_cnt4 = 2; |
4: bit_cnt4 = 1; |
5: bit_cnt4 = 2; |
6: bit_cnt4 = 2; |
7: bit_cnt4 = 3; |
8: bit_cnt4 = 1; |
9: bit_cnt4 = 2; |
10: bit_cnt4 = 2; |
11: bit_cnt4 = 3; |
12: bit_cnt4 = 2; |
13: bit_cnt4 = 3; |
14: bit_cnt4 = 3; |
15: bit_cnt4 = 4; |
endcase |
end |
endfunction |
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function [3:0] bit_cnt8; |
input [7:0] bits; |
begin |
bit_cnt8 = bit_cnt4(bits[3:0]) + bit_cnt4(bits[7:4]); |
end |
endfunction |
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always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin |
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if (reset_xgmii_rx_n == 1'b0) begin |
213,7 → 245,7
// Look for local/remote messages on lower 4 lanes and upper |
// 4 lanes. This is a 64-bit interface but look at each 32-bit |
// independantly. |
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local_fault_msg_det[1] <= (xgmii_rxd[63:32] == |
{`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} && |
xgmii_rxc[7:4] == 4'b0001); |
240,7 → 272,7
xgmii_rxc_d1[7:4] <= xgmii_rxc[7:4]; |
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if (xgmii_rxd[`LANE0] == `START && xgmii_rxc[0]) begin |
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xgxs_rxd_barrel <= xgmii_rxd; |
xgxs_rxc_barrel <= xgmii_rxc; |
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323,7 → 355,7
// Per Clause 46. Control code during data must be reported |
// as a CRC error. Indicated here by coding_error. Corrupt CRC |
// if coding error is detected. |
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if (coding_error || next_coding_error) begin |
crc32_d8 <= ~crc32_d64; |
end |
383,7 → 415,7
end |
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end |
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always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin |
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if (reset_xgmii_rx_n == 1'b0) begin |
455,10 → 487,10
crc_clear = 1'b1; |
next_coding_error = 1'b0; |
next_pause_frame = 1'b0; |
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// Detect the start of a frame |
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if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] && |
xgxs_rxd_barrel_d1[`LANE1] == `PREAMBLE && !xgxs_rxc_barrel_d1[1] && |
xgxs_rxd_barrel_d1[`LANE2] == `PREAMBLE && !xgxs_rxc_barrel_d1[2] && |
477,7 → 509,7
begin |
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// Pause frames are filtered |
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rxhfifo_wen = !pause_frame; |
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527,7 → 559,7
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// Control character during data phase, force CRC error |
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if (|(xgxs_rxc_barrel_d1 & datamask)) begin |
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next_coding_error = 1'b1; |
541,23 → 573,24
end |
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/* verilator lint_off WIDTH */ |
next_byte_cnt = curr_byte_cnt + |
addmask[0] + addmask[1] + addmask[2] + addmask[3] + |
addmask[4] + addmask[5] + addmask[6] + addmask[7]; |
//next_byte_cnt = curr_byte_cnt + |
// addmask[0] + addmask[1] + addmask[2] + addmask[3] + |
// addmask[4] + addmask[5] + addmask[6] + addmask[7]; |
/* verilator lint_on WIDTH */ |
// don't infer a chain of adders |
next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(addmask[7:0])}; |
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// We will not write to the fifo if all is left |
// are four or less bytes of crc. We also strip off the |
// crc, which requires looking one cycle ahead |
// wstatus: |
// wstatus: |
// [2:0] modulus of packet length |
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// Look one cycle ahead for TERMINATE in lanes 0 to 4 |
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if (xgxs_rxd_barrel[`LANE4] == `TERMINATE && xgxs_rxc_barrel[4]) begin |
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rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1; |
rxhfifo_wstatus[2:0] = 3'd0; |
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577,11 → 610,11
crc_start_8b = 1'b1; |
next_crc_bytes = 4'd7; |
next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]}; |
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next_state = SM_IDLE; |
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end |
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if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin |
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rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1; |
607,7 → 640,7
next_state = SM_IDLE; |
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end |
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if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin |
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rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1; |
636,7 → 669,7
next_state = SM_IDLE; |
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end |
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if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE && |
xgxs_rxc_barrel_d1[6]) begin |
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650,7 → 683,7
next_state = SM_IDLE; |
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end |
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if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE && |
xgxs_rxc_barrel_d1[5]) begin |
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721,12 → 754,12
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rxhfifo_ren = !rxhfifo_ralmost_empty_d1 || |
(pkt_pending && !rxhfifo_rstatus[`RXSTATUS_EOP]); |
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if (rxhfifo_ren_d1 && rxhfifo_rstatus[`RXSTATUS_SOP]) begin |
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// Reset drop flag on SOP |
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next_drop_data = 1'b0; |
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end |
751,7 → 784,7
if (crc_done && !crc_good) begin |
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// Flag packet with error when CRC error is detected |
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rxdfifo_wstatus[`RXSTATUS_ERR] = 1'b1; |
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end |
759,4 → 792,3
end |
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endmodule |
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/verilog/generic_mem_small.v
87,6 → 87,7
// Registers |
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reg [DWIDTH-1:0] mem_rdata; |
reg [AWIDTH-1:0] raddr_d1; |
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// Memory |
113,6 → 114,31
// Memory Read |
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// Generate registered memory read |
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`ifdef XIL |
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//always @(posedge rclk) |
//begin |
// if (ren) begin |
// raddr_d1 <= raddr; |
// end |
//end |
//always @(raddr_d1, rclk) |
//begin |
// mem_rdata = mem[raddr_d1[AWIDTH-1:0]]; |
//end |
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always @(posedge rclk) |
begin |
if (!rrst_n) begin |
mem_rdata <= {(DWIDTH){1'b0}}; |
end else if (ren) begin |
mem_rdata <= mem[raddr[AWIDTH-1:0]]; |
end |
end |
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`else |
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always @(posedge rclk or negedge rrst_n) |
begin |
if (!rrst_n) begin |
122,6 → 148,8
end |
end |
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`endif |
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generate |
if (REGISTER_READ) begin |
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/verilog/tx_dequeue.v
297,8 → 297,8
always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop |
or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add |
or ifg_deficit or start_on_lane0 or status_local_fault_ctx |
or txhfifo_ralmost_empty or txhfifo_rdata_d1 |
or txhfifo_rempty or txhfifo_rstatus) begin |
or status_remote_fault_ctx or txhfifo_ralmost_empty |
or txhfifo_rdata_d1 or txhfifo_rempty or txhfifo_rstatus) begin |
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next_state_enc = curr_state_enc; |
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/verilog/generic_mem_medium.v
87,8 → 87,8
// Registers |
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reg [DWIDTH-1:0] mem_rdata; |
reg [AWIDTH-1:0] raddr_d1; |
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// Memory |
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reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1]; |
113,6 → 113,31
// Memory Read |
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// Generate registered memory read |
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`ifdef XIL |
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//always @(posedge rclk) |
//begin |
// if (ren) begin |
// raddr_d1 <= raddr; |
// end |
//end |
//always @(raddr_d1, rclk) |
//begin |
// mem_rdata = mem[raddr_d1[AWIDTH-1:0]]; |
//end |
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always @(posedge rclk) |
begin |
if (!rrst_n) begin |
mem_rdata <= {(DWIDTH){1'b0}}; |
end else if (ren) begin |
mem_rdata <= mem[raddr[AWIDTH-1:0]]; |
end |
end |
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`else |
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always @(posedge rclk or negedge rrst_n) |
begin |
if (!rrst_n) begin |
122,6 → 147,8
end |
end |
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`endif |
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generate |
if (REGISTER_READ) begin |
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/auto_verilog.sh
18,4 → 18,6
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emacs -batch verilog/xge_mac.v -l ../custom.el -f verilog-auto -f save-buffer |
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emacs -batch examples/test_chip.v -l ../custom.el -f verilog-auto -f save-buffer |
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emacs -batch ../tbench/verilog/tb_xge_mac.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer |