URL
https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
Subversion Repositories xge_mac
Compare Revisions
- This comparison shows the changes necessary to convert path
/xge_mac/trunk/rtl
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/include/defines.v
45,6 → 45,8
`define CPUREG_INT_STATUS 8'h0c |
`define CPUREG_INT_MASK 8'h10 |
|
`define CPUREG_STATSTXPKTS 8'h84 |
`define CPUREG_STATSRXPKTS 8'h94 |
|
// Ethernet codes |
|
/verilog/rx_enqueue.v
44,7 → 44,8
rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det, |
remote_fault_msg_det, status_crc_error_tog, |
status_fragment_error_tog, status_rxdfifo_ovflow_tog, |
status_pause_frame_rx_tog, |
status_pause_frame_rx_tog, status_good_frame_rx_tog, |
status_good_frame_rx_size, |
// Inputs |
clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull, |
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty, |
87,9 → 88,12
|
output status_pause_frame_rx_tog; |
|
output status_good_frame_rx_tog; |
output [13:0] status_good_frame_rx_size; |
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|
|
|
/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg [1:0] local_fault_msg_det; |
103,6 → 107,8
reg [7:0] rxhfifo_wstatus; |
reg status_crc_error_tog; |
reg status_fragment_error_tog; |
reg [13:0] status_good_frame_rx_size; |
reg status_good_frame_rx_tog; |
reg status_pause_frame_rx_tog; |
reg status_rxdfifo_ovflow_tog; |
// End of automatics |
142,6 → 148,12
reg [13:0] curr_byte_cnt; |
reg [13:0] next_byte_cnt; |
|
reg frame_end_flag; |
reg next_frame_end_flag; |
|
reg [2:0] frame_end_bytes; |
reg [2:0] next_frame_end_bytes; |
|
reg fragment_error; |
reg rxd_ovflow_error; |
|
237,6 → 249,9
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status_pause_frame_rx_tog <= 1'b0; |
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status_good_frame_rx_tog <= 1'b0; |
status_good_frame_rx_size <= 14'b0; |
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end |
else begin |
|
392,6 → 407,11
status_pause_frame_rx_tog <= ~status_pause_frame_rx_tog; |
end |
|
if (frame_end_flag) begin |
status_good_frame_rx_tog <= ~status_good_frame_rx_tog; |
status_good_frame_rx_size <= curr_byte_cnt + {11'b0, frame_end_bytes}; |
end |
|
end |
|
end |
422,6 → 442,8
|
curr_state <= SM_IDLE; |
curr_byte_cnt <= 14'b0; |
frame_end_flag <= 1'b0; |
frame_end_bytes <= 3'b0; |
coding_error <= 1'b0; |
pause_frame <= 1'b0; |
|
430,6 → 452,8
|
curr_state <= next_state; |
curr_byte_cnt <= next_byte_cnt; |
frame_end_flag <= next_frame_end_flag; |
frame_end_bytes <= next_frame_end_bytes; |
coding_error <= next_coding_error; |
pause_frame <= next_pause_frame; |
|
472,6 → 496,8
crc_clear = 1'b0; |
|
next_byte_cnt = curr_byte_cnt; |
next_frame_end_flag = 1'b0; |
next_frame_end_bytes = 3'b0; |
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fragment_error = 1'b0; |
|
578,7 → 604,7
// addmask[4] + addmask[5] + addmask[6] + addmask[7]; |
/* verilator lint_on WIDTH */ |
// don't infer a chain of adders |
next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(addmask[7:0])}; |
next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(datamask[7:0])}; |
|
|
// We will not write to the fifo if all is left |
598,6 → 624,9
next_crc_bytes = 4'd8; |
next_crc_rx = xgxs_rxd_barrel[31:0]; |
|
next_frame_end_flag = 1'b1; |
next_frame_end_bytes = 3'd4; |
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next_state = SM_IDLE; |
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end |
611,6 → 640,9
next_crc_bytes = 4'd7; |
next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]}; |
|
next_frame_end_flag = 1'b1; |
next_frame_end_bytes = 3'd3; |
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next_state = SM_IDLE; |
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end |
624,6 → 656,9
next_crc_bytes = 4'd6; |
next_crc_rx = {xgxs_rxd_barrel[15:0], xgxs_rxd_barrel_d1[63:48]}; |
|
next_frame_end_flag = 1'b1; |
next_frame_end_bytes = 3'd2; |
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next_state = SM_IDLE; |
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end |
637,6 → 672,9
next_crc_bytes = 4'd5; |
next_crc_rx = {xgxs_rxd_barrel[7:0], xgxs_rxd_barrel_d1[63:40]}; |
|
next_frame_end_flag = 1'b1; |
next_frame_end_bytes = 3'd1; |
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next_state = SM_IDLE; |
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end |
650,6 → 688,8
next_crc_bytes = 4'd4; |
next_crc_rx = xgxs_rxd_barrel_d1[63:32]; |
|
next_frame_end_flag = 1'b1; |
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next_state = SM_IDLE; |
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end |
666,6 → 706,8
next_crc_bytes = 4'd3; |
next_crc_rx = xgxs_rxd_barrel_d1[55:24]; |
|
next_frame_end_flag = 1'b1; |
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next_state = SM_IDLE; |
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end |
680,6 → 722,8
next_crc_bytes = 4'd2; |
next_crc_rx = xgxs_rxd_barrel_d1[47:16]; |
|
next_frame_end_flag = 1'b1; |
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next_state = SM_IDLE; |
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end |
694,6 → 738,8
next_crc_bytes = 4'd1; |
next_crc_rx = xgxs_rxd_barrel_d1[39:8]; |
|
next_frame_end_flag = 1'b1; |
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next_state = SM_IDLE; |
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end |
/verilog/wishbone_if.v
45,7 → 45,8
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i, |
status_crc_error, status_fragment_error, status_txdfifo_ovflow, |
status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow, |
status_pause_frame_rx, status_local_fault, status_remote_fault |
status_pause_frame_rx, status_local_fault, status_remote_fault, |
stats_tx_pkts, stats_rx_pkts |
); |
|
|
78,6 → 79,9
input status_local_fault; |
input status_remote_fault; |
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input [31:0] stats_tx_pkts; |
input [31:0] stats_rx_pkts; |
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output ctrl_tx_enable; |
|
|
186,6 → 190,14
wb_dat_o <= {23'b0, cpureg_int_mask}; |
end |
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`CPUREG_STATSTXPKTS: begin |
wb_dat_o <= stats_tx_pkts; |
end |
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`CPUREG_STATSRXPKTS: begin |
wb_dat_o <= stats_rx_pkts; |
end |
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default: begin |
end |
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/verilog/stats.v
0,0 → 1,119
////////////////////////////////////////////////////////////////////// |
//// //// |
//// File name "wishbone.v" //// |
//// //// |
//// This file is part of the "10GE MAC" project //// |
//// http://www.opencores.org/cores/xge_mac/ //// |
//// //// |
//// Author(s): //// |
//// - A. Tanguay (antanguay@opencores.org) //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2008 AUTHORS. All rights reserved. //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
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`include "defines.v" |
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module stats(/*AUTOARG*/ |
// Outputs |
stats_tx_pkts, stats_rx_pkts, |
// Inputs |
wb_clk_i, wb_rst_i, status_good_frame_tx_tog, |
status_good_frame_tx_size, status_good_frame_rx_tog, |
status_good_frame_rx_size |
); |
|
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input wb_clk_i; |
input wb_rst_i; |
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input status_good_frame_tx_tog; |
input [13:0] status_good_frame_tx_size; |
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input status_good_frame_rx_tog; |
input [13:0] status_good_frame_rx_size; |
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output [31:0] stats_tx_pkts; |
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output [31:0] stats_rx_pkts; |
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/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg [31:0] stats_rx_pkts; |
reg [31:0] stats_tx_pkts; |
// End of automatics |
|
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/*AUTOWIRE*/ |
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reg status_good_frame_tx_tog_d1; |
reg status_good_frame_rx_tog_d1; |
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reg [31:0] next_stats_rx_pkts; |
reg [31:0] next_stats_tx_pkts; |
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always @(posedge wb_clk_i or posedge wb_rst_i) begin |
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if (wb_rst_i == 1'b1) begin |
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status_good_frame_tx_tog_d1 <= status_good_frame_tx_tog; |
status_good_frame_rx_tog_d1 <= status_good_frame_rx_tog; |
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stats_tx_pkts <= 32'b0; |
stats_rx_pkts <= 32'b0; |
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end |
else begin |
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status_good_frame_tx_tog_d1 <= status_good_frame_tx_tog; |
status_good_frame_rx_tog_d1 <= status_good_frame_rx_tog; |
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stats_tx_pkts <= next_stats_tx_pkts; |
stats_rx_pkts <= next_stats_rx_pkts; |
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end |
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end |
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always @(/*AS*/stats_rx_pkts or stats_tx_pkts |
or status_good_frame_rx_tog or status_good_frame_rx_tog_d1 |
or status_good_frame_tx_tog or status_good_frame_tx_tog_d1) begin |
|
next_stats_tx_pkts = stats_tx_pkts; |
next_stats_rx_pkts = stats_rx_pkts; |
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if (status_good_frame_tx_tog_d1 != status_good_frame_tx_tog) begin |
next_stats_tx_pkts = stats_tx_pkts + 32'b1; |
end |
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if (status_good_frame_rx_tog_d1 != status_good_frame_rx_tog) begin |
next_stats_rx_pkts = stats_rx_pkts + 32'b1; |
end |
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end |
|
endmodule |
verilog/stats.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/xge_mac.v
===================================================================
--- verilog/xge_mac.v (revision 22)
+++ verilog/xge_mac.v (revision 23)
@@ -115,10 +115,16 @@
wire [63:0] rxhfifo_wdata; // From rx_eq0 of rx_enqueue.v
wire rxhfifo_wen; // From rx_eq0 of rx_enqueue.v
wire [7:0] rxhfifo_wstatus; // From rx_eq0 of rx_enqueue.v
+wire [31:0] stats_rx_pkts; // From stats0 of stats.v
+wire [31:0] stats_tx_pkts; // From stats0 of stats.v
wire status_crc_error; // From sync_clk_wb0 of sync_clk_wb.v
wire status_crc_error_tog; // From rx_eq0 of rx_enqueue.v
wire status_fragment_error; // From sync_clk_wb0 of sync_clk_wb.v
wire status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v
+wire [13:0] status_good_frame_rx_size;// From rx_eq0 of rx_enqueue.v
+wire status_good_frame_rx_tog;// From rx_eq0 of rx_enqueue.v
+wire [13:0] status_good_frame_tx_size;// From tx_dq0 of tx_dequeue.v
+wire status_good_frame_tx_tog;// From tx_dq0 of tx_dequeue.v
wire status_local_fault; // From sync_clk_wb0 of sync_clk_wb.v
wire status_local_fault_crx; // From fault_sm0 of fault_sm.v
wire status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
@@ -172,6 +178,8 @@
.status_fragment_error_tog(status_fragment_error_tog),
.status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
.status_pause_frame_rx_tog(status_pause_frame_rx_tog),
+ .status_good_frame_rx_tog(status_good_frame_rx_tog),
+ .status_good_frame_rx_size(status_good_frame_rx_size[13:0]),
// Inputs
.clk_xgmii_rx (clk_xgmii_rx),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
@@ -262,6 +270,8 @@
.xgmii_txd (xgmii_txd[63:0]),
.xgmii_txc (xgmii_txc[7:0]),
.status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
+ .status_good_frame_tx_tog(status_good_frame_tx_tog),
+ .status_good_frame_tx_size(status_good_frame_tx_size[13:0]),
// Inputs
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
@@ -359,6 +369,18 @@
.status_local_fault_crx(status_local_fault_crx),
.status_remote_fault_crx(status_remote_fault_crx));
+stats stats0(/*AUTOINST*/
+ // Outputs
+ .stats_tx_pkts (stats_tx_pkts[31:0]),
+ .stats_rx_pkts (stats_rx_pkts[31:0]),
+ // Inputs
+ .wb_clk_i (wb_clk_i),
+ .wb_rst_i (wb_rst_i),
+ .status_good_frame_tx_tog (status_good_frame_tx_tog),
+ .status_good_frame_tx_size (status_good_frame_tx_size[13:0]),
+ .status_good_frame_rx_tog (status_good_frame_rx_tog),
+ .status_good_frame_rx_size (status_good_frame_rx_size[13:0]));
+
//sync_clk_core sync_clk_core0(/*AUTOINST*/
// // Inputs
// .clk_xgmii_tx (clk_xgmii_tx),
@@ -386,6 +408,8 @@
.status_rxdfifo_udflow (status_rxdfifo_udflow),
.status_pause_frame_rx (status_pause_frame_rx),
.status_local_fault (status_local_fault),
- .status_remote_fault (status_remote_fault));
+ .status_remote_fault (status_remote_fault),
+ .stats_tx_pkts (stats_tx_pkts[31:0]),
+ .stats_rx_pkts (stats_rx_pkts[31:0]));
endmodule
/verilog/tx_dequeue.v
42,6 → 42,7
// Outputs |
txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus, |
txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog, |
status_good_frame_tx_tog, status_good_frame_tx_size, |
// Inputs |
clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx, |
status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata, |
87,11 → 88,15
|
output status_txdfifo_udflow_tog; |
|
output status_good_frame_tx_tog; |
output [13:0] status_good_frame_tx_size; |
|
|
|
/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg [13:0] status_good_frame_tx_size; |
reg status_good_frame_tx_tog; |
reg status_txdfifo_udflow_tog; |
reg txdfifo_ren; |
reg txhfifo_ren; |
161,6 → 166,8
|
reg txdfifo_ren_d1; |
|
reg frame_end; |
|
parameter [2:0] |
SM_IDLE = 3'd0, |
SM_PREAMBLE = 3'd1, |
245,6 → 252,9
|
status_txdfifo_udflow_tog <= 1'b0; |
|
status_good_frame_tx_tog <= 1'b0; |
status_good_frame_tx_size <= 14'b0; |
|
end |
else begin |
|
290,6 → 300,14
status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog; |
end |
|
//--- |
// Frame count and size |
|
if (frame_end) begin |
status_good_frame_tx_tog <= ~status_good_frame_tx_tog; |
status_good_frame_tx_size <= byte_cnt; |
end |
|
end |
|
end |
744,7 → 762,7
|
if (txdfifo_rstatus[`TXSTATUS_EOP]) begin |
|
if (byte_cnt < 14'd56) begin |
if (byte_cnt < 14'd60) begin |
|
next_txhfifo_wstatus = `TXSTATUS_NONE; |
txdfifo_ren = 1'b0; |
751,7 → 769,7
next_state_pad = SM_PAD_PAD; |
|
end |
else if (byte_cnt == 14'd56 && |
else if (byte_cnt == 14'd60 && |
(txdfifo_rstatus[2:0] == 3'd1 || |
txdfifo_rstatus[2:0] == 3'd2 || |
txdfifo_rstatus[2:0] == 3'd3)) begin |
796,7 → 814,7
next_txhfifo_wstatus = `TXSTATUS_NONE; |
next_txhfifo_wen = 1'b1; |
|
if (byte_cnt == 14'd56) begin |
if (byte_cnt == 14'd60) begin |
|
|
// Pad up to LANE3, keep the other 4 bytes for crc that will |
845,6 → 863,8
crc32_d8 <= 32'b0; |
crc32_tx <= 32'b0; |
|
frame_end <= 1'b0; |
|
end |
else begin |
|
856,6 → 876,7
txhfifo_wstatus <= next_txhfifo_wstatus; |
txhfifo_wen <= next_txhfifo_wen; |
|
frame_end <= 1'b0; |
|
//--- |
// Reset byte count on SOP |
864,15 → 885,28
|
if (next_txhfifo_wstatus[`TXSTATUS_SOP]) begin |
|
byte_cnt <= 14'd8; |
// Init byte count, 8-bytes + 4-bytes for CRC at the end of frame |
|
byte_cnt <= 14'd12; |
|
end |
else begin |
|
byte_cnt <= byte_cnt + 14'd8; |
if (next_txhfifo_wstatus[`TXSTATUS_EOP] && next_txhfifo_wstatus[2:0] != 3'b0) begin |
|
byte_cnt <= byte_cnt + {11'b0, next_txhfifo_wstatus[2:0]}; |
|
end |
else begin |
|
byte_cnt <= byte_cnt + 14'd8; |
|
end |
|
end |
|
frame_end <= next_txhfifo_wstatus[`TXSTATUS_EOP]; |
|
end |
|
|
/auto_verilog.sh
5,6 → 5,7
|
emacs -batch verilog/wishbone_if.v -l ../custom.el -f verilog-auto -f save-buffer |
emacs -batch verilog/fault_sm.v -l ../custom.el -f verilog-auto -f save-buffer |
emacs -batch verilog/stats.v -l ../custom.el -f verilog-auto -f save-buffer |
|
emacs -batch verilog/rx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer |
emacs -batch verilog/rx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer |