OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xge_mac/trunk/rtl
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/include/defines.v
40,14 → 40,17
 
// CPU Registers
 
`define CPUREG_CONFIG0 8'h00
`define CPUREG_INT_PENDING 8'h08
`define CPUREG_INT_STATUS 8'h0c
`define CPUREG_INT_MASK 8'h10
`define CPUREG_CONFIG0 8'h00
`define CPUREG_INT_PENDING 8'h08
`define CPUREG_INT_STATUS 8'h0c
`define CPUREG_INT_MASK 8'h10
 
`define CPUREG_STATSTXPKTS 8'h84
`define CPUREG_STATSRXPKTS 8'h94
`define CPUREG_STATSTXOCTETS 8'h80
`define CPUREG_STATSTXPKTS 8'h84
 
`define CPUREG_STATSRXOCTETS 8'h90
`define CPUREG_STATSRXPKTS 8'h94
 
// Ethernet codes
 
`define IDLE 8'h07
106,6 → 109,13
`define RX_HOLD_FIFO_AWIDTH 4
 
 
//
// FIFO Size: Statistics FIFOs are 16 deep
//
`define TX_STAT_FIFO_AWIDTH 4
`define RX_STAT_FIFO_AWIDTH 4
 
 
// Memory types
`define MEM_AUTO_SMALL 1
`define MEM_AUTO_MEDIUM 2
/verilog/tx_stats_fifo.v
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "tx_hold_fifo.v" ////
//// ////
//// This file is part of the "10GE MAC" project ////
//// http://www.opencores.org/cores/xge_mac/ ////
//// ////
//// Author(s): ////
//// - A. Tanguay (antanguay@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
`include "defines.v"
 
module tx_stats_fifo(/*AUTOARG*/
// Outputs
txsfifo_rdata, txsfifo_rempty,
// Inputs
clk_xgmii_tx, reset_xgmii_tx_n, wb_clk_i, wb_rst_i, txsfifo_wdata,
txsfifo_wen
);
 
input clk_xgmii_tx;
input reset_xgmii_tx_n;
input wb_clk_i;
input wb_rst_i;
 
input [13:0] txsfifo_wdata;
input txsfifo_wen;
 
output [13:0] txsfifo_rdata;
output txsfifo_rempty;
 
generic_fifo #(
.DWIDTH (14),
.AWIDTH (`TX_STAT_FIFO_AWIDTH),
.REGISTER_READ (1),
.EARLY_READ (1),
.CLOCK_CROSSING (1),
.ALMOST_EMPTY_THRESH (7),
.ALMOST_FULL_THRESH (12),
.MEM_TYPE (`MEM_AUTO_SMALL)
)
fifo0(
.wclk (clk_xgmii_tx),
.wrst_n (reset_xgmii_tx_n),
.wen (txsfifo_wen),
.wdata (txsfifo_wdata),
.wfull (),
.walmost_full (),
 
.rclk (wb_clk_i),
.rrst_n (~wb_rst_i),
.ren (1'b1),
.rdata (txsfifo_rdata),
.rempty (txsfifo_rempty),
.ralmost_empty ()
);
 
endmodule
verilog/tx_stats_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/rx_enqueue.v =================================================================== --- verilog/rx_enqueue.v (revision 23) +++ verilog/rx_enqueue.v (revision 24) @@ -44,8 +44,7 @@ rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det, remote_fault_msg_det, status_crc_error_tog, status_fragment_error_tog, status_rxdfifo_ovflow_tog, - status_pause_frame_rx_tog, status_good_frame_rx_tog, - status_good_frame_rx_size, + status_pause_frame_rx_tog, rxsfifo_wen, rxsfifo_wdata, // Inputs clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull, rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty, @@ -88,12 +87,11 @@ output status_pause_frame_rx_tog; -output status_good_frame_rx_tog; -output [13:0] status_good_frame_rx_size; +output rxsfifo_wen; +output [13:0] rxsfifo_wdata; - /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [1:0] local_fault_msg_det; @@ -105,10 +103,10 @@ reg [63:0] rxhfifo_wdata; reg rxhfifo_wen; reg [7:0] rxhfifo_wstatus; +reg [13:0] rxsfifo_wdata; +reg rxsfifo_wen; reg status_crc_error_tog; reg status_fragment_error_tog; -reg [13:0] status_good_frame_rx_size; -reg status_good_frame_rx_tog; reg status_pause_frame_rx_tog; reg status_rxdfifo_ovflow_tog; // End of automatics @@ -249,12 +247,15 @@ status_pause_frame_rx_tog <= 1'b0; - status_good_frame_rx_tog <= 1'b0; - status_good_frame_rx_size <= 14'b0; + rxsfifo_wen <= 1'b0; + rxsfifo_wdata <= 14'b0; end else begin + rxsfifo_wen <= 1'b0; + rxsfifo_wdata <= curr_byte_cnt + {11'b0, frame_end_bytes}; + //--- // Link status RC layer // Look for local/remote messages on lower 4 lanes and upper @@ -408,8 +409,7 @@ end if (frame_end_flag) begin - status_good_frame_rx_tog <= ~status_good_frame_rx_tog; - status_good_frame_rx_size <= curr_byte_cnt + {11'b0, frame_end_bytes}; + rxsfifo_wen <= 1'b1; end end
/verilog/wishbone_if.v
46,7 → 46,7
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
status_pause_frame_rx, status_local_fault, status_remote_fault,
stats_tx_pkts, stats_rx_pkts
stats_tx_octets, stats_tx_pkts, stats_rx_octets, stats_rx_pkts
);
 
 
79,7 → 79,10
input status_local_fault;
input status_remote_fault;
 
input [31:0] stats_tx_octets;
input [31:0] stats_tx_pkts;
 
input [31:0] stats_rx_octets;
input [31:0] stats_rx_pkts;
 
output ctrl_tx_enable;
190,10 → 193,18
wb_dat_o <= {23'b0, cpureg_int_mask};
end
 
`CPUREG_STATSTXOCTETS: begin
wb_dat_o <= stats_tx_octets;
end
 
`CPUREG_STATSTXPKTS: begin
wb_dat_o <= stats_tx_pkts;
end
 
`CPUREG_STATSRXOCTETS: begin
wb_dat_o <= stats_rx_octets;
end
 
`CPUREG_STATSRXPKTS: begin
wb_dat_o <= stats_rx_pkts;
end
/verilog/stats_sm.v
0,0 → 1,136
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "wishbone.v" ////
//// ////
//// This file is part of the "10GE MAC" project ////
//// http://www.opencores.org/cores/xge_mac/ ////
//// ////
//// Author(s): ////
//// - A. Tanguay (antanguay@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
`include "defines.v"
 
module stats_sm(/*AUTOARG*/
// Outputs
stats_tx_octets, stats_tx_pkts, stats_rx_octets, stats_rx_pkts,
// Inputs
wb_clk_i, wb_rst_i, txsfifo_rdata, txsfifo_rempty, rxsfifo_rdata,
rxsfifo_rempty
);
 
 
input wb_clk_i;
input wb_rst_i;
 
input [13:0] txsfifo_rdata;
input txsfifo_rempty;
 
input [13:0] rxsfifo_rdata;
input rxsfifo_rempty;
 
output [31:0] stats_tx_octets;
output [31:0] stats_tx_pkts;
 
output [31:0] stats_rx_octets;
output [31:0] stats_rx_pkts;
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] stats_rx_octets;
reg [31:0] stats_rx_pkts;
reg [31:0] stats_tx_octets;
reg [31:0] stats_tx_pkts;
// End of automatics
 
 
/*AUTOWIRE*/
 
reg txsfifo_rempty_d1;
reg rxsfifo_rempty_d1;
 
reg [31:0] next_stats_tx_octets;
reg [31:0] next_stats_tx_pkts;
 
reg [31:0] next_stats_rx_octets;
reg [31:0] next_stats_rx_pkts;
 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
 
if (wb_rst_i == 1'b1) begin
 
txsfifo_rempty_d1 <= 1'b1;
rxsfifo_rempty_d1 <= 1'b1;
 
stats_tx_octets <= 32'b0;
stats_tx_pkts <= 32'b0;
 
stats_rx_octets <= 32'b0;
stats_rx_pkts <= 32'b0;
 
end
else begin
 
txsfifo_rempty_d1 <= txsfifo_rempty;
rxsfifo_rempty_d1 <= rxsfifo_rempty;
 
stats_tx_octets <= next_stats_tx_octets;
stats_tx_pkts <= next_stats_tx_pkts;
 
stats_rx_octets <= next_stats_rx_octets;
stats_rx_pkts <= next_stats_rx_pkts;
 
end
 
end
 
always @(/*AS*/rxsfifo_rdata or rxsfifo_rempty_d1 or stats_rx_octets
or stats_rx_pkts or stats_tx_octets or stats_tx_pkts
or txsfifo_rdata or txsfifo_rempty_d1) begin
 
next_stats_tx_octets = stats_tx_octets;
next_stats_tx_pkts = stats_tx_pkts;
 
next_stats_rx_octets = stats_rx_octets;
next_stats_rx_pkts = stats_rx_pkts;
 
if (!txsfifo_rempty_d1) begin
next_stats_tx_octets = stats_tx_octets + {18'b0, txsfifo_rdata};
next_stats_tx_pkts = stats_tx_pkts + 32'b1;
end
 
if (!rxsfifo_rempty_d1) begin
next_stats_rx_octets = stats_rx_octets + {18'b0, rxsfifo_rdata};
next_stats_rx_pkts = stats_rx_pkts + 32'b1;
end
 
end
 
endmodule
verilog/stats_sm.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/stats.v =================================================================== --- verilog/stats.v (revision 23) +++ verilog/stats.v (revision 24) @@ -40,80 +40,80 @@ module stats(/*AUTOARG*/ // Outputs - stats_tx_pkts, stats_rx_pkts, + stats_tx_pkts, stats_tx_octets, stats_rx_pkts, stats_rx_octets, // Inputs - wb_clk_i, wb_rst_i, status_good_frame_tx_tog, - status_good_frame_tx_size, status_good_frame_rx_tog, - status_good_frame_rx_size + wb_rst_i, wb_clk_i, txsfifo_wen, txsfifo_wdata, rxsfifo_wen, + rxsfifo_wdata, reset_xgmii_tx_n, reset_xgmii_rx_n, clk_xgmii_tx, + clk_xgmii_rx ); -input wb_clk_i; -input wb_rst_i; +/*AUTOINPUT*/ +// Beginning of automatic inputs (from unused autoinst inputs) +input clk_xgmii_rx; // To rx_stats_fifo0 of rx_stats_fifo.v +input clk_xgmii_tx; // To tx_stats_fifo0 of tx_stats_fifo.v +input reset_xgmii_rx_n; // To rx_stats_fifo0 of rx_stats_fifo.v +input reset_xgmii_tx_n; // To tx_stats_fifo0 of tx_stats_fifo.v +input [13:0] rxsfifo_wdata; // To rx_stats_fifo0 of rx_stats_fifo.v +input rxsfifo_wen; // To rx_stats_fifo0 of rx_stats_fifo.v +input [13:0] txsfifo_wdata; // To tx_stats_fifo0 of tx_stats_fifo.v +input txsfifo_wen; // To tx_stats_fifo0 of tx_stats_fifo.v +input wb_clk_i; // To tx_stats_fifo0 of tx_stats_fifo.v, ... +input wb_rst_i; // To tx_stats_fifo0 of tx_stats_fifo.v, ... +// End of automatics -input status_good_frame_tx_tog; -input [13:0] status_good_frame_tx_size; - -input status_good_frame_rx_tog; -input [13:0] status_good_frame_rx_size; - -output [31:0] stats_tx_pkts; - -output [31:0] stats_rx_pkts; - -/*AUTOREG*/ -// Beginning of automatic regs (for this module's undeclared outputs) -reg [31:0] stats_rx_pkts; -reg [31:0] stats_tx_pkts; +/*AUTOOUTPUT*/ +// Beginning of automatic outputs (from unused autoinst outputs) +output [31:0] stats_rx_octets; // From stats_sm0 of stats_sm.v +output [31:0] stats_rx_pkts; // From stats_sm0 of stats_sm.v +output [31:0] stats_tx_octets; // From stats_sm0 of stats_sm.v +output [31:0] stats_tx_pkts; // From stats_sm0 of stats_sm.v // End of automatics - /*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +wire [13:0] rxsfifo_rdata; // From rx_stats_fifo0 of rx_stats_fifo.v +wire rxsfifo_rempty; // From rx_stats_fifo0 of rx_stats_fifo.v +wire [13:0] txsfifo_rdata; // From tx_stats_fifo0 of tx_stats_fifo.v +wire txsfifo_rempty; // From tx_stats_fifo0 of tx_stats_fifo.v +// End of automatics -reg status_good_frame_tx_tog_d1; -reg status_good_frame_rx_tog_d1; +tx_stats_fifo tx_stats_fifo0(/*AUTOINST*/ + // Outputs + .txsfifo_rdata (txsfifo_rdata[13:0]), + .txsfifo_rempty (txsfifo_rempty), + // Inputs + .clk_xgmii_tx (clk_xgmii_tx), + .reset_xgmii_tx_n (reset_xgmii_tx_n), + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .txsfifo_wdata (txsfifo_wdata[13:0]), + .txsfifo_wen (txsfifo_wen)); -reg [31:0] next_stats_rx_pkts; -reg [31:0] next_stats_tx_pkts; +rx_stats_fifo rx_stats_fifo0(/*AUTOINST*/ + // Outputs + .rxsfifo_rdata (rxsfifo_rdata[13:0]), + .rxsfifo_rempty (rxsfifo_rempty), + // Inputs + .clk_xgmii_rx (clk_xgmii_rx), + .reset_xgmii_rx_n (reset_xgmii_rx_n), + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .rxsfifo_wdata (rxsfifo_wdata[13:0]), + .rxsfifo_wen (rxsfifo_wen)); -always @(posedge wb_clk_i or posedge wb_rst_i) begin +stats_sm stats_sm0(/*AUTOINST*/ + // Outputs + .stats_tx_octets (stats_tx_octets[31:0]), + .stats_tx_pkts (stats_tx_pkts[31:0]), + .stats_rx_octets (stats_rx_octets[31:0]), + .stats_rx_pkts (stats_rx_pkts[31:0]), + // Inputs + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .txsfifo_rdata (txsfifo_rdata[13:0]), + .txsfifo_rempty (txsfifo_rempty), + .rxsfifo_rdata (rxsfifo_rdata[13:0]), + .rxsfifo_rempty (rxsfifo_rempty)); - if (wb_rst_i == 1'b1) begin - - status_good_frame_tx_tog_d1 <= status_good_frame_tx_tog; - status_good_frame_rx_tog_d1 <= status_good_frame_rx_tog; - - stats_tx_pkts <= 32'b0; - stats_rx_pkts <= 32'b0; - - end - else begin - - status_good_frame_tx_tog_d1 <= status_good_frame_tx_tog; - status_good_frame_rx_tog_d1 <= status_good_frame_rx_tog; - - stats_tx_pkts <= next_stats_tx_pkts; - stats_rx_pkts <= next_stats_rx_pkts; - - end - -end - -always @(/*AS*/stats_rx_pkts or stats_tx_pkts - or status_good_frame_rx_tog or status_good_frame_rx_tog_d1 - or status_good_frame_tx_tog or status_good_frame_tx_tog_d1) begin - - next_stats_tx_pkts = stats_tx_pkts; - next_stats_rx_pkts = stats_rx_pkts; - - if (status_good_frame_tx_tog_d1 != status_good_frame_tx_tog) begin - next_stats_tx_pkts = stats_tx_pkts + 32'b1; - end - - if (status_good_frame_rx_tog_d1 != status_good_frame_rx_tog) begin - next_stats_rx_pkts = stats_rx_pkts + 32'b1; - end - -end - endmodule
/verilog/xge_mac.v
115,16 → 115,16
wire [63:0] rxhfifo_wdata; // From rx_eq0 of rx_enqueue.v
wire rxhfifo_wen; // From rx_eq0 of rx_enqueue.v
wire [7:0] rxhfifo_wstatus; // From rx_eq0 of rx_enqueue.v
wire [13:0] rxsfifo_wdata; // From rx_eq0 of rx_enqueue.v
wire rxsfifo_wen; // From rx_eq0 of rx_enqueue.v
wire [31:0] stats_rx_octets; // From stats0 of stats.v
wire [31:0] stats_rx_pkts; // From stats0 of stats.v
wire [31:0] stats_tx_octets; // From stats0 of stats.v
wire [31:0] stats_tx_pkts; // From stats0 of stats.v
wire status_crc_error; // From sync_clk_wb0 of sync_clk_wb.v
wire status_crc_error_tog; // From rx_eq0 of rx_enqueue.v
wire status_fragment_error; // From sync_clk_wb0 of sync_clk_wb.v
wire status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v
wire [13:0] status_good_frame_rx_size;// From rx_eq0 of rx_enqueue.v
wire status_good_frame_rx_tog;// From rx_eq0 of rx_enqueue.v
wire [13:0] status_good_frame_tx_size;// From tx_dq0 of tx_dequeue.v
wire status_good_frame_tx_tog;// From tx_dq0 of tx_dequeue.v
wire status_local_fault; // From sync_clk_wb0 of sync_clk_wb.v
wire status_local_fault_crx; // From fault_sm0 of fault_sm.v
wire status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
161,6 → 161,8
wire txhfifo_wen; // From tx_dq0 of tx_dequeue.v
wire txhfifo_wfull; // From tx_hold_fifo0 of tx_hold_fifo.v
wire [7:0] txhfifo_wstatus; // From tx_dq0 of tx_dequeue.v
wire [13:0] txsfifo_wdata; // From tx_dq0 of tx_dequeue.v
wire txsfifo_wen; // From tx_dq0 of tx_dequeue.v
// End of automatics
 
rx_enqueue rx_eq0(/*AUTOINST*/
178,8 → 180,8
.status_fragment_error_tog(status_fragment_error_tog),
.status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
.status_pause_frame_rx_tog(status_pause_frame_rx_tog),
.status_good_frame_rx_tog(status_good_frame_rx_tog),
.status_good_frame_rx_size(status_good_frame_rx_size[13:0]),
.rxsfifo_wen (rxsfifo_wen),
.rxsfifo_wdata (rxsfifo_wdata[13:0]),
// Inputs
.clk_xgmii_rx (clk_xgmii_rx),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
270,8 → 272,8
.xgmii_txd (xgmii_txd[63:0]),
.xgmii_txc (xgmii_txc[7:0]),
.status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
.status_good_frame_tx_tog(status_good_frame_tx_tog),
.status_good_frame_tx_size(status_good_frame_tx_size[13:0]),
.txsfifo_wen (txsfifo_wen),
.txsfifo_wdata (txsfifo_wdata[13:0]),
// Inputs
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
371,15 → 373,21
 
stats stats0(/*AUTOINST*/
// Outputs
.stats_rx_octets (stats_rx_octets[31:0]),
.stats_rx_pkts (stats_rx_pkts[31:0]),
.stats_tx_octets (stats_tx_octets[31:0]),
.stats_tx_pkts (stats_tx_pkts[31:0]),
.stats_rx_pkts (stats_rx_pkts[31:0]),
// Inputs
.clk_xgmii_rx (clk_xgmii_rx),
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
.rxsfifo_wdata (rxsfifo_wdata[13:0]),
.rxsfifo_wen (rxsfifo_wen),
.txsfifo_wdata (txsfifo_wdata[13:0]),
.txsfifo_wen (txsfifo_wen),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.status_good_frame_tx_tog (status_good_frame_tx_tog),
.status_good_frame_tx_size (status_good_frame_tx_size[13:0]),
.status_good_frame_rx_tog (status_good_frame_rx_tog),
.status_good_frame_rx_size (status_good_frame_rx_size[13:0]));
.wb_rst_i (wb_rst_i));
 
//sync_clk_core sync_clk_core0(/*AUTOINST*/
// // Inputs
409,7 → 417,9
.status_pause_frame_rx (status_pause_frame_rx),
.status_local_fault (status_local_fault),
.status_remote_fault (status_remote_fault),
.stats_tx_octets (stats_tx_octets[31:0]),
.stats_tx_pkts (stats_tx_pkts[31:0]),
.stats_rx_octets (stats_rx_octets[31:0]),
.stats_rx_pkts (stats_rx_pkts[31:0]));
 
endmodule
/verilog/tx_dequeue.v
42,7 → 42,7
// Outputs
txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
status_good_frame_tx_tog, status_good_frame_tx_size,
txsfifo_wen, txsfifo_wdata,
// Inputs
clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
88,15 → 88,12
 
output status_txdfifo_udflow_tog;
 
output status_good_frame_tx_tog;
output [13:0] status_good_frame_tx_size;
output txsfifo_wen;
output [13:0] txsfifo_wdata;
 
 
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [13:0] status_good_frame_tx_size;
reg status_good_frame_tx_tog;
reg status_txdfifo_udflow_tog;
reg txdfifo_ren;
reg txhfifo_ren;
103,6 → 100,8
reg [63:0] txhfifo_wdata;
reg txhfifo_wen;
reg [7:0] txhfifo_wstatus;
reg [13:0] txsfifo_wdata;
reg txsfifo_wen;
reg [7:0] xgmii_txc;
reg [63:0] xgmii_txd;
// End of automatics
252,8 → 251,8
 
status_txdfifo_udflow_tog <= 1'b0;
 
status_good_frame_tx_tog <= 1'b0;
status_good_frame_tx_size <= 14'b0;
txsfifo_wen <= 1'b0;
txsfifo_wdata <= 14'b0;
 
end
else begin
275,6 → 274,9
 
frame_available <= next_frame_available;
 
txsfifo_wen <= 1'b0;
txsfifo_wdata <= byte_cnt;
 
//---
// Barrel shifter. Previous stage always align packet with LANE0.
// This stage allow us to shift packet to align with LANE4 if needed
304,8 → 306,7
// Frame count and size
 
if (frame_end) begin
status_good_frame_tx_tog <= ~status_good_frame_tx_tog;
status_good_frame_tx_size <= byte_cnt;
txsfifo_wen <= 1'b1;
end
 
end
/verilog/rx_stats_fifo.v
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "tx_hold_fifo.v" ////
//// ////
//// This file is part of the "10GE MAC" project ////
//// http://www.opencores.org/cores/xge_mac/ ////
//// ////
//// Author(s): ////
//// - A. Tanguay (antanguay@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
`include "defines.v"
 
module rx_stats_fifo(/*AUTOARG*/
// Outputs
rxsfifo_rdata, rxsfifo_rempty,
// Inputs
clk_xgmii_rx, reset_xgmii_rx_n, wb_clk_i, wb_rst_i, rxsfifo_wdata,
rxsfifo_wen
);
 
input clk_xgmii_rx;
input reset_xgmii_rx_n;
input wb_clk_i;
input wb_rst_i;
 
input [13:0] rxsfifo_wdata;
input rxsfifo_wen;
 
output [13:0] rxsfifo_rdata;
output rxsfifo_rempty;
 
generic_fifo #(
.DWIDTH (14),
.AWIDTH (`RX_STAT_FIFO_AWIDTH),
.REGISTER_READ (1),
.EARLY_READ (1),
.CLOCK_CROSSING (1),
.ALMOST_EMPTY_THRESH (7),
.ALMOST_FULL_THRESH (12),
.MEM_TYPE (`MEM_AUTO_SMALL)
)
fifo0(
.wclk (clk_xgmii_rx),
.wrst_n (reset_xgmii_rx_n),
.wen (rxsfifo_wen),
.wdata (rxsfifo_wdata),
.wfull (),
.walmost_full (),
 
.rclk (wb_clk_i),
.rrst_n (~wb_rst_i),
.ren (1'b1),
.rdata (rxsfifo_rdata),
.rempty (rxsfifo_rempty),
.ralmost_empty ()
);
 
endmodule
verilog/rx_stats_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: auto_verilog.sh =================================================================== --- auto_verilog.sh (revision 23) +++ auto_verilog.sh (revision 24) @@ -5,6 +5,10 @@ emacs -batch verilog/wishbone_if.v -l ../custom.el -f verilog-auto -f save-buffer emacs -batch verilog/fault_sm.v -l ../custom.el -f verilog-auto -f save-buffer + +emacs -batch verilog/tx_stats_fifo.v -l ../custom.el -f verilog-auto -f save-buffer +emacs -batch verilog/rx_stats_fifo.v -l ../custom.el -f verilog-auto -f save-buffer +emacs -batch verilog/stats_sm.v -l ../custom.el -f verilog-auto -f save-buffer emacs -batch verilog/stats.v -l ../custom.el -f verilog-auto -f save-buffer emacs -batch verilog/rx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.