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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

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  • This comparison shows the changes necessary to convert path 
    /xge_mac/trunk/rtl
    from Rev 24 to Rev 25
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  •

Rev 24 → Rev 25

/include/defines.v
97,10 → 97,10
 
//
// FIFO Size: 8 * (2^AWIDTH) will be the size in bytes
// 7 --> 128 entries, 1024 bytes for data fifo
// 6 --> 128 entries, 512 bytes for data fifo
//
`define TX_DATA_FIFO_AWIDTH 7
`define RX_DATA_FIFO_AWIDTH 7
`define TX_DATA_FIFO_AWIDTH 6
`define RX_DATA_FIFO_AWIDTH 6
 
//
// FIFO Size: Holding FIFOs are 16 deep
/verilog/rx_enqueue.v
250,6 → 250,8
rxsfifo_wen <= 1'b0;
rxsfifo_wdata <= 14'b0;
 
datamask <= 8'b0;
 
end
else begin
 
319,7 → 321,18
xgxs_rxd_barrel_d1 <= xgxs_rxd_barrel;
xgxs_rxc_barrel_d1 <= xgxs_rxc_barrel;
 
//---
// Mask for end-of-frame
 
datamask[0] <= addmask[0];
datamask[1] <= &addmask[1:0];
datamask[2] <= &addmask[2:0];
datamask[3] <= &addmask[3:0];
datamask[4] <= &addmask[4:0];
datamask[5] <= &addmask[5:0];
datamask[6] <= &addmask[6:0];
datamask[7] <= &addmask[7:0];
 
//---
// When final CRC calculation begins we capture info relevant to
// current frame CRC claculation continues while next frame is
463,8 → 476,9
 
 
always @(/*AS*/coding_error or crc_rx or curr_byte_cnt or curr_state
or pause_frame or xgxs_rxc_barrel or xgxs_rxc_barrel_d1
or xgxs_rxd_barrel or xgxs_rxd_barrel_d1) begin
or datamask or pause_frame or xgxs_rxc_barrel
or xgxs_rxc_barrel_d1 or xgxs_rxd_barrel
or xgxs_rxd_barrel_d1) begin
 
next_state = curr_state;
 
472,24 → 486,6
rxhfifo_wstatus = `RXSTATUS_NONE;
rxhfifo_wen = 1'b0;
 
addmask[0] = !(xgxs_rxd_barrel_d1[`LANE0] == `TERMINATE && xgxs_rxc_barrel_d1[0]);
addmask[1] = !(xgxs_rxd_barrel_d1[`LANE1] == `TERMINATE && xgxs_rxc_barrel_d1[1]);
addmask[2] = !(xgxs_rxd_barrel_d1[`LANE2] == `TERMINATE && xgxs_rxc_barrel_d1[2]);
addmask[3] = !(xgxs_rxd_barrel_d1[`LANE3] == `TERMINATE && xgxs_rxc_barrel_d1[3]);
addmask[4] = !(xgxs_rxd_barrel_d1[`LANE4] == `TERMINATE && xgxs_rxc_barrel_d1[4]);
addmask[5] = !(xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE && xgxs_rxc_barrel_d1[5]);
addmask[6] = !(xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE && xgxs_rxc_barrel_d1[6]);
addmask[7] = !(xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE && xgxs_rxc_barrel_d1[7]);
 
datamask[0] = addmask[0];
datamask[1] = &addmask[1:0];
datamask[2] = &addmask[2:0];
datamask[3] = &addmask[3:0];
datamask[4] = &addmask[4:0];
datamask[5] = &addmask[5:0];
datamask[6] = &addmask[6:0];
datamask[7] = &addmask[7:0];
 
next_crc_bytes = 4'b0;
next_crc_rx = crc_rx;
crc_start_8b = 1'b0;
504,6 → 500,15
next_coding_error = coding_error;
next_pause_frame = pause_frame;
 
addmask[0] = !(xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]);
addmask[1] = !(xgxs_rxd_barrel[`LANE1] == `TERMINATE && xgxs_rxc_barrel[1]);
addmask[2] = !(xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]);
addmask[3] = !(xgxs_rxd_barrel[`LANE3] == `TERMINATE && xgxs_rxc_barrel[3]);
addmask[4] = !(xgxs_rxd_barrel[`LANE4] == `TERMINATE && xgxs_rxc_barrel[4]);
addmask[5] = !(xgxs_rxd_barrel[`LANE5] == `TERMINATE && xgxs_rxc_barrel[5]);
addmask[6] = !(xgxs_rxd_barrel[`LANE6] == `TERMINATE && xgxs_rxc_barrel[6]);
addmask[7] = !(xgxs_rxd_barrel[`LANE7] == `TERMINATE && xgxs_rxc_barrel[7]);
 
case (curr_state)
 
SM_IDLE:
/verilog/generic_mem_small.v
141,14 → 141,25
 
`else
 
always @(posedge rclk or negedge rrst_n)
//always @(posedge rclk or negedge rrst_n)
//begin
// if (!rrst_n) begin
// mem_rdata <= {(DWIDTH){1'b0}};
// end else if (ren) begin
// mem_rdata <= mem[raddr[AWIDTH-1:0]];
// end
//end
 
always @(posedge rclk)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
if (ren) begin
raddr_d1 <= raddr;
end
end
always @(raddr_d1, rclk)
begin
mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
end
 
`endif
 
/verilog/tx_dequeue.v
893,16 → 893,16
end
else begin
 
if (next_txhfifo_wstatus[`TXSTATUS_EOP] && next_txhfifo_wstatus[2:0] != 3'b0) begin
// if (next_txhfifo_wstatus[`TXSTATUS_EOP] && next_txhfifo_wstatus[2:0] != 3'b0) begin
 
byte_cnt <= byte_cnt + {11'b0, next_txhfifo_wstatus[2:0]};
// byte_cnt <= byte_cnt + {11'b0, next_txhfifo_wstatus[2:0]};
 
end
else begin
// end
// else begin
 
byte_cnt <= byte_cnt + 14'd8;
 
end
// end
 
end
 
/verilog/generic_mem_medium.v
140,14 → 140,25
 
`else
 
always @(posedge rclk or negedge rrst_n)
//always @(posedge rclk or negedge rrst_n)
//begin
// if (!rrst_n) begin
// mem_rdata <= {(DWIDTH){1'b0}};
// end else if (ren) begin
// mem_rdata <= mem[raddr[AWIDTH-1:0]];
// end
//end
 
always @(posedge rclk)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
if (ren) begin
raddr_d1 <= raddr;
end
end
always @(raddr_d1, rclk)
begin
mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
end
 
`endif
 

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