Subversion Repositories xge_mac

/proto_systemverilog/irunScript

proto_systemverilog/irunScript Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: proto_systemverilog/irunForOOP =================================================================== --- proto_systemverilog/irunForOOP (nonexistent) +++ proto_systemverilog/irunForOOP (revision 22) @@ -0,0 +1 @@ +irun ../../verification/macCoreInterface.sv ../../verification/testbench.sv ../../rtl/verilog/*.v testcase.sv +incdir+../../rtl/include/ +svseed=random

proto_systemverilog/irunForOOP Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: proto_systemverilog/CLEAN =================================================================== --- proto_systemverilog/CLEAN (nonexistent) +++ proto_systemverilog/CLEAN (revision 22) @@ -0,0 +1 @@ +\rm -rf simv* csrc *.log vcdplus.vpd *DVE* *INCA* transcript work

proto_systemverilog/CLEAN Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: proto_systemverilog/irun.log =================================================================== --- proto_systemverilog/irun.log (nonexistent) +++ proto_systemverilog/irun.log (revision 22) @@ -0,0 +1,30 @@ +irun: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc. +TOOL: irun 09.20-p007: Started on Oct 28, 2012 at 18:11:47 PDT +irun + ../../verification/macCoreInterface.sv + ../../verification/testbench.sv + ../../rtl/verilog/fault_sm.v + ../../rtl/verilog/generic_fifo_ctrl.v + ../../rtl/verilog/generic_fifo.v + ../../rtl/verilog/generic_mem_medium.v + ../../rtl/verilog/generic_mem_small.v + ../../rtl/verilog/meta_sync_single.v + ../../rtl/verilog/meta_sync.v + ../../rtl/verilog/rx_data_fifo.v + ../../rtl/verilog/rx_dequeue.v + ../../rtl/verilog/rx_enqueue.v + ../../rtl/verilog/rx_hold_fifo.v + ../../rtl/verilog/sync_clk_core.v + ../../rtl/verilog/sync_clk_wb.v + ../../rtl/verilog/sync_clk_xgmii_tx.v + ../../rtl/verilog/tx_data_fifo.v + ../../rtl/verilog/tx_dequeue.v + ../../rtl/verilog/tx_enqueue.v + ../../rtl/verilog/tx_hold_fifo.v + ../../rtl/verilog/wishbone_if.v + ../../rtl/verilog/xge_mac.v + testcase.sv + +incdir+../../rtl/include/ + +svseed=random +irun: *E,FILEMIS: Cannot find the provided file testcase.sv. +TOOL: irun 09.20-p007: Exiting on Oct 28, 2012 at 18:11:48 PDT (total: 00:00:01)

proto_systemverilog/irun.log Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: proto_systemverilog/runsim =================================================================== --- proto_systemverilog/runsim (nonexistent) +++ proto_systemverilog/runsim (revision 22) @@ -0,0 +1,5 @@ +vcs +vcs+lic+wait -sverilog -R -l vcs.log \ +-override_timescale=1ps/1ps \ +../../rtl/verilog/*.v \ ++incdir+../../rtl/include \ +../../testbench/verilog/tb_xge_mac.sv

proto_systemverilog/runsim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property