URL
https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
Subversion Repositories xge_mac
Compare Revisions
- This comparison shows the changes necessary to convert path
/xge_mac/trunk/tbench/verilog
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/tb_xge_mac.sv
67,6 → 67,9
reg pkt_tx_eop; |
reg [2:0] pkt_tx_mod; |
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integer tx_count; |
integer rx_count; |
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/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire pkt_rx_avail; // From dut of xge_mac.v |
244,6 → 247,11
assign wb_we_i = 1'b0; |
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initial begin |
tx_count = 0; |
rx_count = 0; |
end |
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//--- |
// XGMII Loopback |
// This test is done with loopback on XGMII or using one of the tranceiver examples |
370,6 → 378,8
pkt_tx_eop = 1'b0; |
pkt_tx_mod = 3'b0; |
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tx_count = tx_count + 1; |
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end |
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endtask |
471,6 → 481,8
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if (pkt_rx_sop) begin |
$display("\n\n------------------------"); |
$display("Received Packet"); |
$display("------------------------"); |
end |
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$display("%x", pkt_rx_data); |
490,6 → 502,8
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end |
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rx_count = rx_count + 1; |
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end |
endtask |
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498,7 → 512,13
forever begin |
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if (pkt_rx_avail) begin |
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RxPacket(); |
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if (rx_count == tx_count) begin |
$display("All packets received. Sumulation done!!!\n"); |
end |
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end |
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@(posedge clk_156m25); |